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authorTarun Kanti DebBarma <tarun.kanti@ti.com>2011-09-20 07:30:24 -0400
committerTony Lindgren <tony@atomide.com>2011-09-21 20:07:34 -0400
commitb481113a8af65f49afed46d4c9132b7af9426684 (patch)
treef468369003b3d0e70342aee8d0cce6b1c637e1a7 /arch/arm/plat-omap/include/plat/dmtimer.h
parent0dad9faeaeb0fa3524068a94e1745b91e5597c17 (diff)
ARM: OMAP: dmtimer: low-power mode support
Clock is enabled only when timer is started and disabled when the the timer is stopped. Therefore before accessing registers in functions clock is enabled and then disabled back at the end of access. Context save is done dynamically whenever the registers are modified. Context restore is called when context is lost. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [tony@atomide.com: updated to use revision instead of tidr] Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat/dmtimer.h')
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h35
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 29764c34f57..9519d87179e 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -73,11 +73,38 @@ struct omap_timer_capability_dev_attr {
73struct omap_dm_timer; 73struct omap_dm_timer;
74struct clk; 74struct clk;
75 75
76struct timer_regs {
77 u32 tidr;
78 u32 tiocp_cfg;
79 u32 tistat;
80 u32 tisr;
81 u32 tier;
82 u32 twer;
83 u32 tclr;
84 u32 tcrr;
85 u32 tldr;
86 u32 ttrg;
87 u32 twps;
88 u32 tmar;
89 u32 tcar1;
90 u32 tsicr;
91 u32 tcar2;
92 u32 tpir;
93 u32 tnir;
94 u32 tcvr;
95 u32 tocr;
96 u32 towr;
97};
98
76struct dmtimer_platform_data { 99struct dmtimer_platform_data {
77 int (*set_timer_src)(struct platform_device *pdev, int source); 100 int (*set_timer_src)(struct platform_device *pdev, int source);
78 int timer_ip_version; 101 int timer_ip_version;
79 u32 needs_manual_reset:1; 102 u32 needs_manual_reset:1;
80 bool reserved; 103 bool reserved;
104
105 bool loses_context;
106
107 u32 (*get_context_loss_count)(struct device *dev);
81}; 108};
82 109
83struct omap_dm_timer *omap_dm_timer_request(void); 110struct omap_dm_timer *omap_dm_timer_request(void);
@@ -245,8 +272,14 @@ struct omap_dm_timer {
245 unsigned long rate; 272 unsigned long rate;
246 unsigned reserved:1; 273 unsigned reserved:1;
247 unsigned posted:1; 274 unsigned posted:1;
275 struct timer_regs context;
276 bool loses_context;
277 int ctx_loss_count;
278 int revision;
248 struct platform_device *pdev; 279 struct platform_device *pdev;
249 struct list_head node; 280 struct list_head node;
281
282 u32 (*get_context_loss_count)(struct device *dev);
250}; 283};
251 284
252int omap_dm_timer_prepare(struct omap_dm_timer *timer); 285int omap_dm_timer_prepare(struct omap_dm_timer *timer);
@@ -278,6 +311,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
278 /* Assume v1 ip if bits [31:16] are zero */ 311 /* Assume v1 ip if bits [31:16] are zero */
279 tidr = __raw_readl(timer->io_base); 312 tidr = __raw_readl(timer->io_base);
280 if (!(tidr >> 16)) { 313 if (!(tidr >> 16)) {
314 timer->revision = 1;
281 timer->sys_stat = timer->io_base + 315 timer->sys_stat = timer->io_base +
282 OMAP_TIMER_V1_SYS_STAT_OFFSET; 316 OMAP_TIMER_V1_SYS_STAT_OFFSET;
283 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; 317 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
@@ -286,6 +320,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
286 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; 320 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
287 timer->func_base = timer->io_base; 321 timer->func_base = timer->io_base;
288 } else { 322 } else {
323 timer->revision = 2;
289 timer->sys_stat = 0; 324 timer->sys_stat = 0;
290 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; 325 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
291 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; 326 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;