diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-06-19 21:08:27 -0400 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-06-19 21:09:31 -0400 |
commit | d0ba3922ae241a87d22a1c3ffad72b96fe993c9a (patch) | |
tree | 3f23d60fbbf2ffceef44b01c8579db7be7d20025 /arch/arm/plat-omap/include/mach/sram.h | |
parent | c9812d042a21eb492a36cfabf9f41107f5ecee3d (diff) |
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include/mach/sram.h')
-rw-r--r-- | arch/arm/plat-omap/include/mach/sram.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h index c32fa0a220d..4f87056a367 100644 --- a/arch/arm/plat-omap/include/mach/sram.h +++ b/arch/arm/plat-omap/include/mach/sram.h | |||
@@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); | |||
24 | extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, | 24 | extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, |
25 | u32 sdrc_actim_ctrla, | 25 | u32 sdrc_actim_ctrla, |
26 | u32 sdrc_actim_ctrlb, u32 m2, | 26 | u32 sdrc_actim_ctrlb, u32 m2, |
27 | u32 unlock_dll, u32 f); | 27 | u32 unlock_dll, u32 f, u32 sdrc_mr); |
28 | 28 | ||
29 | /* Do not use these */ | 29 | /* Do not use these */ |
30 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); | 30 | extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); |
@@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; | |||
62 | extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, | 62 | extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, |
63 | u32 sdrc_actim_ctrla, | 63 | u32 sdrc_actim_ctrla, |
64 | u32 sdrc_actim_ctrlb, u32 m2, | 64 | u32 sdrc_actim_ctrlb, u32 m2, |
65 | u32 unlock_dll, u32 f); | 65 | u32 unlock_dll, u32 f, u32 sdrc_mr); |
66 | extern unsigned long omap3_sram_configure_core_dpll_sz; | 66 | extern unsigned long omap3_sram_configure_core_dpll_sz; |
67 | 67 | ||
68 | #endif | 68 | #endif |