Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc power management changes from Arnd Bergmann:
 "These are various power management related changes, mainly concerning
  cpuidle on i.MX and OMAP, as well as a the move of the omap
  smartreflex driver to live in the power subsystem."

Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h}

* tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
  ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
  ARM: OMAP2+: do not allow SmartReflex to be built as a module
  ARM: OMAP2: Use hwmod to initialize mmc for 2420
  ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
  ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
  ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
  ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
  ARM: OMAP3: PM: call pre/post transition per powerdomain
  ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
  ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
  ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
  ARM: OMAP3+: PRM: Enable IO wake up
  ARM: OMAP4: PRM: Add IO Daisychain support
  ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
  ARM: OMAP3: PM: correct enable/disable of daisy io chain
  ARM: OMAP2+: PRM: fix compile for OMAP4-only build
  W1: OMAP HDQ1W: use runtime PM
  ARM: OMAP2+: HDQ1W: use omap_device
  W1: OMAP HDQ1W: use 32-bit register accesses
  W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
  ...

6 files changed, 126 insertions, 12 deletions

diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e81290c27c6..63b064b5c1d 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/cpuidle.c b/arch/arm/plat-mxc/cpuidle.c
new file mode 100644
index 00000000000..d4cb511a44a
--- /dev/null
+++ b/arch/arm/plat-mxc/cpuidle.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/err.h>
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+static struct cpuidle_device __percpu * imx_cpuidle_devices;
+
+static void __init imx_cpuidle_devices_uninit(void)
+{
+        int cpu_id;
+        struct cpuidle_device *dev;
+
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
+                cpuidle_unregister_device(dev);
+        }
+
+        free_percpu(imx_cpuidle_devices);
+}
+
+int __init imx_cpuidle_init(struct cpuidle_driver *drv)
+{
+        struct cpuidle_device *dev;
+        int cpu_id, ret;
+
+        if (drv->state_count > CPUIDLE_STATE_MAX) {
+                pr_err("%s: state_count exceeds maximum\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = cpuidle_register_driver(drv);
+        if (ret) {
+                pr_err("%s: Failed to register cpuidle driver with error: %d\n",
+                         __func__, ret);
+                return ret;
+        }
+
+        imx_cpuidle_devices = alloc_percpu(struct cpuidle_device);
+        if (imx_cpuidle_devices == NULL) {
+                ret = -ENOMEM;
+                goto unregister_drv;
+        }
+
+        /* initialize state data for each cpuidle_device */
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
+                dev->cpu = cpu_id;
+                dev->state_count = drv->state_count;
+
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("%s: Failed to register cpu %u, error: %d\n",
+                                __func__, cpu_id, ret);
+                        goto uninit;
+                }
+        }
+
+        return 0;
+
+uninit:
+        imx_cpuidle_devices_uninit();
+
+unregister_drv:
+        cpuidle_unregister_driver(drv);
+        return ret;
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7cfcc44537f..7128e971041 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -54,6 +54,7 @@ extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
 extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
+extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
 extern void mxc_timer_init(void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
@@ -96,7 +97,6 @@ enum mx3_cpu_pwr_mode {
 };
 
 extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
@@ -147,8 +147,12 @@ extern void imx6q_clock_map_io(void);
 
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
+extern void imx51_pm_init(void);
+extern void imx53_pm_init(void);
 #else
 static inline void imx6q_pm_init(void) {}
+static inline void imx51_pm_init(void) {}
+static inline void imx53_pm_init(void) {}
 #endif
 
 #ifdef CONFIG_NEON
diff --git a/arch/arm/plat-mxc/include/mach/cpuidle.h b/arch/arm/plat-mxc/include/mach/cpuidle.h
new file mode 100644
index 00000000000..bc932d1af37
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpuidle.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+
+#ifdef CONFIG_CPU_IDLE
+extern int imx_cpuidle_init(struct cpuidle_driver *drv);
+#else
+static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
+{
+        return -ENODEV;
+}
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 1d432a75e40..ebf10654bb4 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -50,7 +50,7 @@
  *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
  * mx21:
  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
  * mx25:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
@@ -58,47 +58,50 @@
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
  * mx27:
  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
  * mx31:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  * mx35:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  * mx50:
  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx51:
- *      TZIC    0xe0000000+0x004000     ->      0xf5000000+0x004000
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
  *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
+ *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
- *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ *      AIPS2   0x83f00000+0x100000     ->      0xf5300000+0x100000
  * mx53:
  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      DEBUG   0x40000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx6q:
- *      SCU     0x00a00000+0x001000     ->      0xf4000000+0x001000
+ *      SCU     0x00a00000+0x004000     ->      0xf4000000+0x004000
  *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
- *      ANATOP  0x020c8000+0x001000     ->      0xf42c8000+0x001000
+ *      ANATOP  0x020c8000+0x004000     ->      0xf42c8000+0x004000
  *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
  */
 #define IMX_IO_P2V(x)   (                                               \
-                        0xf4000000 +                                    \
+                        (((x) & 0x80000000) >> 7) |                     \
+                        (0xf4000000 +                                   \
                         (((x) & 0x50000000) >> 6) +                     \
                         (((x) & 0x0b000000) >> 4) +                     \
-                        (((x) & 0x000fffff)))
+                        (((x) & 0x000fffff))))
 
 #define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
 
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index c60a7e41638..c2193178210 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -202,6 +202,10 @@ void __init tzic_init_irq(void __iomem *irqbase)
  * tzic_enable_wake() - enable wakeup interrupt
  *
  * @return                      0 if successful; non-zero otherwise
+ *
+ * This function provides an interrupt synchronization point that is required
+ * by tzic enabled platforms before entering imx specific low power modes (ie,
+ * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
  */
 int tzic_enable_wake(void)
 {