aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-mxc/include/mach/mx27.h
diff options
context:
space:
mode:
authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-01-07 05:27:17 -0500
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-01-08 10:45:24 -0500
commita8dfb6462a033984b99fee4122fe0799a31f5bb4 (patch)
treebc71dbed2b59a897d1f5f90b541fc7d0f6b4ae48 /arch/arm/plat-mxc/include/mach/mx27.h
parent3cdd54417d0f821825a353f7273d356399112f56 (diff)
imx: define functions to configure chip selects in the WEIM
This has the addional effect that the macros CSCR_U, CSCR_L and CSCR_A are not used anymore in mach-pcm038.c and mach-qong.c. These still use the deprecated IO_ADDRESS macro and shouldn't be used in new code. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Dmitriy Taychenachev <dimichxp@gmail.com>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx27.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 832b5804dcb..bae9cd75bee 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,6 +24,10 @@
24#ifndef __MACH_MX27_H__ 24#ifndef __MACH_MX27_H__
25#define __MACH_MX27_H__ 25#define __MACH_MX27_H__
26 26
27#ifndef __ASSEMBLER__
28#include <linux/io.h>
29#endif
30
27#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
28#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
29#define MX27_AIPI_SIZE SZ_1M 33#define MX27_AIPI_SIZE SZ_1M
@@ -109,6 +113,11 @@
109#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) 113#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
110#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) 114#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
111 115
116#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
117#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
118#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
119#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
120
112#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 121#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
113 122
114/* IRAM */ 123/* IRAM */
@@ -119,6 +128,16 @@
119 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ 128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
120 IMX_IO_ADDRESS(x, MX27_X_MEMC)) 129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
121 130
131#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
134{
135 __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
138}
139#endif
140
122/* fixed interrupt numbers */ 141/* fixed interrupt numbers */
123#define MX27_INT_I2C2 1 142#define MX27_INT_I2C2 1
124#define MX27_INT_GPT6 2 143#define MX27_INT_GPT6 2