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authorCatalin Marinas <catalin.marinas@arm.com>2010-12-07 10:56:29 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-12 18:25:58 -0500
commitda30e0ac0f9a521f0cfec8145ddd1ad131f66d61 (patch)
tree4a9002e6fca4d4763b40908403fc177153b9a6a8 /arch/arm/mm
parentf91e2c3bd427239c198351f44814dd39db91afe0 (diff)
ARM: 6528/1: Use CTR for the I-cache line size on ARMv7
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-v7.S27
-rw-r--r--arch/arm/mm/proc-macros.S10
2 files changed, 27 insertions, 10 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a3ebf7a4f49..6136e68ce95 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -173,15 +173,22 @@ ENTRY(v7_coherent_user_range)
173 UNWIND(.fnstart ) 173 UNWIND(.fnstart )
174 dcache_line_size r2, r3 174 dcache_line_size r2, r3
175 sub r3, r2, #1 175 sub r3, r2, #1
176 bic r0, r0, r3 176 bic r12, r0, r3
1771: 1771:
178 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification 178 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
179 add r12, r12, r2
180 cmp r12, r1
181 blo 1b
179 dsb 182 dsb
180 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line 183 icache_line_size r2, r3
181 add r0, r0, r2 184 sub r3, r2, #1
185 bic r12, r0, r3
1822: 1862:
183 cmp r0, r1 187 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
184 blo 1b 188 add r12, r12, r2
189 cmp r12, r1
190 blo 2b
1913:
185 mov r0, #0 192 mov r0, #0
186 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 193 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
187 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 194 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
@@ -194,10 +201,10 @@ ENTRY(v7_coherent_user_range)
194 * isn't mapped, just try the next page. 201 * isn't mapped, just try the next page.
195 */ 202 */
1969001: 2039001:
197 mov r0, r0, lsr #12 204 mov r12, r12, lsr #12
198 mov r0, r0, lsl #12 205 mov r12, r12, lsl #12
199 add r0, r0, #4096 206 add r12, r12, #4096
200 b 2b 207 b 3b
201 UNWIND(.fnend ) 208 UNWIND(.fnend )
202ENDPROC(v7_coherent_kern_range) 209ENDPROC(v7_coherent_kern_range)
203ENDPROC(v7_coherent_user_range) 210ENDPROC(v7_coherent_user_range)
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 321555b894d..b795afd0a2c 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -72,6 +72,16 @@
72 mov \reg, \reg, lsl \tmp @ actual cache line size 72 mov \reg, \reg, lsl \tmp @ actual cache line size
73 .endm 73 .endm
74 74
75/*
76 * icache_line_size - get the minimum I-cache line size from the CTR register
77 * on ARMv7.
78 */
79 .macro icache_line_size, reg, tmp
80 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
81 and \tmp, \tmp, #0xf @ cache line size encoding
82 mov \reg, #4 @ bytes per word
83 mov \reg, \reg, lsl \tmp @ actual cache line size
84 .endm
75 85
76/* 86/*
77 * Sanity check the PTE configuration for the code below - which makes 87 * Sanity check the PTE configuration for the code below - which makes