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authorCatalin Marinas <catalin.marinas@arm.com>2007-07-20 06:42:24 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-20 16:42:35 -0400
commit11179d8ca28d669e3d4cc7573a5f5fdda3e6f02d (patch)
tree48ebac19f2ca133a5108d4fc779332b9e696d59a /arch/arm/mm/mmu.c
parent2eb8c82bc492d5f185150e63eba5eac4dff24178 (diff)
[ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later
Currently, Linux doesn't generate correct page tables for ARMv6 and later cores if the cache policy is different from the default one (it may lead to strongly ordered or shared device mappings). This patch disallows cache policies other than writeback and the CPU_[ID]CACHE_DISABLE options only affect the CP15 system control register rather than the page tables. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/mmu.c')
-rw-r--r--arch/arm/mm/mmu.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3b5e47dc0c9..e5d61ee3d4a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p)
114 } 114 }
115 if (i == ARRAY_SIZE(cache_policies)) 115 if (i == ARRAY_SIZE(cache_policies))
116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
117 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
118 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
119 cachepolicy = CPOLICY_WRITEBACK;
120 }
117 flush_cache_all(); 121 flush_cache_all();
118 set_cr(cr_alignment); 122 set_cr(cr_alignment);
119} 123}
@@ -252,13 +256,15 @@ static void __init build_mem_type_table(void)
252 int cpu_arch = cpu_architecture(); 256 int cpu_arch = cpu_architecture();
253 int i; 257 int i;
254 258
259 if (cpu_arch < CPU_ARCH_ARMv6) {
255#if defined(CONFIG_CPU_DCACHE_DISABLE) 260#if defined(CONFIG_CPU_DCACHE_DISABLE)
256 if (cachepolicy > CPOLICY_BUFFERED) 261 if (cachepolicy > CPOLICY_BUFFERED)
257 cachepolicy = CPOLICY_BUFFERED; 262 cachepolicy = CPOLICY_BUFFERED;
258#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 263#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
259 if (cachepolicy > CPOLICY_WRITETHROUGH) 264 if (cachepolicy > CPOLICY_WRITETHROUGH)
260 cachepolicy = CPOLICY_WRITETHROUGH; 265 cachepolicy = CPOLICY_WRITETHROUGH;
261#endif 266#endif
267 }
262 if (cpu_arch < CPU_ARCH_ARMv5) { 268 if (cpu_arch < CPU_ARCH_ARMv5) {
263 if (cachepolicy >= CPOLICY_WRITEALLOC) 269 if (cachepolicy >= CPOLICY_WRITEALLOC)
264 cachepolicy = CPOLICY_WRITEBACK; 270 cachepolicy = CPOLICY_WRITEBACK;