ARM: entry: data abort: avoid using r2 in abort helpers

This allows us to pass the pt_regs pointer in to these functions
ready for tail-calling the abort handler.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 17 insertions, 17 deletions

diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index fea7514225a..d032b1f2067 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -64,12 +64,12 @@ ENTRY(v4t_late_abort)
         mov     r7, #0x11
         orr     r7, r7, #0x1100
         and     r6, r8, r7
-        and     r2, r8, r7, lsl #1
-        add     r6, r6, r2, lsr #1
-        and     r2, r8, r7, lsl #2
-        add     r6, r6, r2, lsr #2
-        and     r2, r8, r7, lsl #3
-        add     r6, r6, r2, lsr #3
+        and     r9, r8, r7, lsl #1
+        add     r6, r6, r9, lsr #1
+        and     r9, r8, r7, lsl #2
+        add     r6, r6, r9, lsr #2
+        and     r9, r8, r7, lsl #3
+        add     r6, r6, r9, lsr #3
         add     r6, r6, r6, lsr #8
         add     r6, r6, r6, lsr #4
         and     r6, r6, #15                     @ r6 = no. of registers to transfer.
@@ -103,13 +103,13 @@ ENTRY(v4t_late_abort)
         tst     r8, #1 << 21                    @ check writeback bit
         moveq   pc, lr                          @ no writeback -> no fixup
 .data_arm_lateldrpostconst:
-        movs    r2, r8, lsl #20                 @ Get offset
+        movs    r9, r8, lsl #20                 @ Get offset
         moveq   pc, lr                          @ zero -> no fixup
         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
         ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
         tst     r8, #1 << 23                    @ Check U bit
-        subne   r7, r7, r2, lsr #20             @ Undo increment
-        addeq   r7, r7, r2, lsr #20             @ Undo decrement
+        subne   r7, r7, r9, lsr #20             @ Undo increment
+        addeq   r7, r7, r9, lsr #20             @ Undo decrement
         str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
         mov     pc, lr
 
@@ -194,11 +194,11 @@ ENTRY(v4t_late_abort)
         tst     r8, #1 << 10
         beq     .data_unknown
         and     r6, r8, #0x55                   @ hweight8(r8) + R bit
-        and     r2, r8, #0xaa
-        add     r6, r6, r2, lsr #1
-        and     r2, r6, #0xcc
+        and     r9, r8, #0xaa
+        add     r6, r6, r9, lsr #1
+        and     r9, r6, #0xcc
         and     r6, r6, #0x33
-        add     r6, r6, r2, lsr #2
+        add     r6, r6, r9, lsr #2
         movs    r7, r8, lsr #9                  @ C = r8 bit 8 (R bit)
         adc     r6, r6, r6, lsr #4              @ high + low nibble + R bit
         and     r6, r6, #15                     @ number of regs to transfer
@@ -211,11 +211,11 @@ ENTRY(v4t_late_abort)
 
 .data_thumb_ldmstm:
         and     r6, r8, #0x55                   @ hweight8(r8)
-        and     r2, r8, #0xaa
-        add     r6, r6, r2, lsr #1
-        and     r2, r6, #0xcc
+        and     r9, r8, #0xaa
+        add     r6, r6, r9, lsr #1
+        and     r9, r6, #0xcc
         and     r6, r6, #0x33
-        add     r6, r6, r2, lsr #2
+        add     r6, r6, r9, lsr #2
         add     r6, r6, r6, lsr #4
         and     r5, r8, #7 << 8
         ldr     r7, [sp, r5, lsr #6]