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authorwanzongshun <mcuos.com@gmail.com>2010-07-28 22:25:19 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-29 09:03:49 -0400
commitf4f5e28d2ee02e3b68da4a8b6156f3b4872d03be (patch)
treedc5b2b13a1dca9a5360f1edbdfc487f55ecb539d /arch/arm/mach-w90x900/include
parentc6ca2e466f22dee01a97f04bcc6bec8062d79847 (diff)
ARM: 6274/1: add global control registers definition header file for nuc900
add global control registers definition header file for nuc900 Signed-off-by: Wan ZongShun <mcuos.com@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-w90x900/include')
-rw-r--r--arch/arm/mach-w90x900/include/mach/regs-gcr.h39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-w90x900/include/mach/regs-gcr.h b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
new file mode 100644
index 00000000000..6087abd93ef
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-gcr.h
@@ -0,0 +1,39 @@
1/*
2 * arch/arm/mach-w90x900/include/mach/regs-gcr.h
3 *
4 * Copyright (c) 2010 Nuvoton technology corporation
5 * All rights reserved.
6 *
7 * Wan ZongShun <mcuos.com@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#ifndef __ASM_ARCH_REGS_GCR_H
17#define __ASM_ARCH_REGS_GCR_H
18
19/* Global control registers */
20
21#define GCR_BA W90X900_VA_GCR
22#define REG_PDID (GCR_BA+0x000)
23#define REG_PWRON (GCR_BA+0x004)
24#define REG_ARBCON (GCR_BA+0x008)
25#define REG_MFSEL (GCR_BA+0x00C)
26#define REG_EBIDPE (GCR_BA+0x010)
27#define REG_LCDDPE (GCR_BA+0x014)
28#define REG_GPIOCPE (GCR_BA+0x018)
29#define REG_GPIODPE (GCR_BA+0x01C)
30#define REG_GPIOEPE (GCR_BA+0x020)
31#define REG_GPIOFPE (GCR_BA+0x024)
32#define REG_GPIOGPE (GCR_BA+0x028)
33#define REG_GPIOHPE (GCR_BA+0x02C)
34#define REG_GPIOIPE (GCR_BA+0x030)
35#define REG_GTMP1 (GCR_BA+0x034)
36#define REG_GTMP2 (GCR_BA+0x038)
37#define REG_GTMP3 (GCR_BA+0x03C)
38
39#endif /* __ASM_ARCH_REGS_GCR_H */