Merge branch 'tegra/soc' into next/cleanup2

Conflicts:
	arch/arm/mach-tegra/Makefile

Signed-off-by: Olof Johansson <olof@lixom.net>

3 files changed, 17 insertions, 3 deletions

diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index fc3ecb66de0..d97e403303a 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -22,10 +22,20 @@
 
 struct clk;
 
+enum tegra_clk_ex_param {
+        TEGRA_CLK_VI_INP_SEL,
+        TEGRA_CLK_DTV_INVERT,
+        TEGRA_CLK_NAND_PAD_DIV2_ENB,
+        TEGRA_CLK_PLLD_CSI_OUT_ENB,
+        TEGRA_CLK_PLLD_DSI_OUT_ENB,
+        TEGRA_CLK_PLLD_MIPI_MUX_SEL,
+};
+
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
 unsigned long clk_get_rate_all_locked(struct clk *c);
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index c05b311ee4f..2fd94725913 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -74,6 +74,9 @@
 #define TEGRA_QUATERNARY_ICTLR_BASE     0x60004300
 #define TEGRA_QUATERNARY_ICTLR_SIZE     SZ_64
 
+#define TEGRA_QUINARY_ICTLR_BASE        0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE        SZ_64
+
 #define TEGRA_TMR1_BASE                 0x60005000
 #define TEGRA_TMR1_SIZE                 SZ_8
 
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index a2146cd6867..aad1a2c1d71 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -165,11 +165,12 @@
 #define INT_QUAD_RES_30                 (INT_QUAD_BASE + 30)
 #define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
 
-#define INT_MAIN_NR                     (INT_QUAD_BASE + 32 - INT_PRI_BASE)
-
+/* Tegra30 has 5 banks of 32 IRQs */
+#define INT_MAIN_NR                     (32 * 5)
 #define INT_GPIO_BASE                   (INT_PRI_BASE + INT_MAIN_NR)
 
-#define INT_GPIO_NR                     (28 * 8)
+/* Tegra30 has 8 banks of 32 GPIOs */
+#define INT_GPIO_NR                     (32 * 8)
 
 #define TEGRA_NR_IRQS                   (INT_GPIO_BASE + INT_GPIO_NR)