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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-tegra/devices.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-tegra/devices.c')
-rw-r--r--arch/arm/mach-tegra/devices.c1692
1 files changed, 1692 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
new file mode 100644
index 00000000000..202c767550e
--- /dev/null
+++ b/arch/arm/mach-tegra/devices.c
@@ -0,0 +1,1692 @@
1/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 * Erik Gilling <ccross@android.com>
7 *
8 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21
22#include <linux/resource.h>
23#include <linux/dma-mapping.h>
24#include <linux/fsl_devices.h>
25#include <linux/serial_8250.h>
26#include <linux/i2c-tegra.h>
27#include <linux/platform_data/tegra_usb.h>
28#include <linux/tegra_avp.h>
29#include <linux/nvhost.h>
30#include <linux/clk.h>
31#include <asm/pmu.h>
32#include <mach/irqs.h>
33#include <mach/iomap.h>
34#include <mach/dma.h>
35#include <mach/usb_phy.h>
36#include <mach/tegra_smmu.h>
37
38#include "gpio-names.h"
39#include "devices.h"
40
41static struct resource i2c_resource1[] = {
42 [0] = {
43 .start = INT_I2C,
44 .end = INT_I2C,
45 .flags = IORESOURCE_IRQ,
46 },
47 [1] = {
48 .start = TEGRA_I2C_BASE,
49 .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
50 .flags = IORESOURCE_MEM,
51 },
52};
53
54static struct resource i2c_resource2[] = {
55 [0] = {
56 .start = INT_I2C2,
57 .end = INT_I2C2,
58 .flags = IORESOURCE_IRQ,
59 },
60 [1] = {
61 .start = TEGRA_I2C2_BASE,
62 .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
63 .flags = IORESOURCE_MEM,
64 },
65};
66
67static struct resource i2c_resource3[] = {
68 [0] = {
69 .start = INT_I2C3,
70 .end = INT_I2C3,
71 .flags = IORESOURCE_IRQ,
72 },
73 [1] = {
74 .start = TEGRA_I2C3_BASE,
75 .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
76 .flags = IORESOURCE_MEM,
77 },
78};
79
80#ifdef CONFIG_ARCH_TEGRA_2x_SOC
81static struct resource i2c_resource4[] = {
82 [0] = {
83 .start = INT_DVC,
84 .end = INT_DVC,
85 .flags = IORESOURCE_IRQ,
86 },
87 [1] = {
88 .start = TEGRA_DVC_BASE,
89 .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
90 .flags = IORESOURCE_MEM,
91 },
92};
93
94#else
95static struct resource i2c_resource4[] = {
96 [0] = {
97 .start = INT_I2C4,
98 .end = INT_I2C4,
99 .flags = IORESOURCE_IRQ,
100 },
101 [1] = {
102 .start = TEGRA_I2C4_BASE,
103 .end = TEGRA_I2C4_BASE + TEGRA_I2C4_SIZE-1,
104 .flags = IORESOURCE_MEM,
105 },
106};
107
108static struct resource i2c_resource5[] = {
109 [0] = {
110 .start = INT_I2C5,
111 .end = INT_I2C5,
112 .flags = IORESOURCE_IRQ,
113 },
114 [1] = {
115 .start = TEGRA_I2C5_BASE,
116 .end = TEGRA_I2C5_BASE + TEGRA_I2C5_SIZE-1,
117 .flags = IORESOURCE_MEM,
118 },
119};
120#endif
121
122static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
123 .bus_clk_rate = { 400000 },
124};
125
126static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
127 .bus_clk_rate = { 400000 },
128};
129
130static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
131 .bus_clk_rate = { 400000 },
132};
133
134static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
135 .bus_clk_rate = { 400000 },
136};
137
138struct platform_device tegra_i2c_device1 = {
139 .name = "tegra-i2c",
140 .id = 0,
141 .resource = i2c_resource1,
142 .num_resources = ARRAY_SIZE(i2c_resource1),
143 .dev = {
144 .platform_data = &tegra_i2c1_platform_data,
145 },
146};
147
148struct platform_device tegra_i2c_device2 = {
149 .name = "tegra-i2c",
150 .id = 1,
151 .resource = i2c_resource2,
152 .num_resources = ARRAY_SIZE(i2c_resource2),
153 .dev = {
154 .platform_data = &tegra_i2c2_platform_data,
155 },
156};
157
158struct platform_device tegra_i2c_device3 = {
159 .name = "tegra-i2c",
160 .id = 2,
161 .resource = i2c_resource3,
162 .num_resources = ARRAY_SIZE(i2c_resource3),
163 .dev = {
164 .platform_data = &tegra_i2c3_platform_data,
165 },
166};
167
168struct platform_device tegra_i2c_device4 = {
169 .name = "tegra-i2c",
170 .id = 3,
171 .resource = i2c_resource4,
172 .num_resources = ARRAY_SIZE(i2c_resource4),
173 .dev = {
174 .platform_data = &tegra_dvc_platform_data,
175 },
176};
177
178#ifndef CONFIG_ARCH_TEGRA_2x_SOC
179struct platform_device tegra_i2c_device5 = {
180 .name = "tegra-i2c",
181 .id = 4,
182 .resource = i2c_resource5,
183 .num_resources = ARRAY_SIZE(i2c_resource5),
184 .dev = {
185 .platform_data = 0,
186 },
187};
188#endif
189
190static struct resource spi_resource1[] = {
191 [0] = {
192 .start = INT_SPI_1,
193 .end = INT_SPI_1,
194 .flags = IORESOURCE_IRQ,
195 },
196 [1] = {
197 .start = TEGRA_SPI1_BASE,
198 .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
199 .flags = IORESOURCE_MEM,
200 },
201};
202
203static struct resource spi_resource2[] = {
204 [0] = {
205 .start = INT_SPI_2,
206 .end = INT_SPI_2,
207 .flags = IORESOURCE_IRQ,
208 },
209 [1] = {
210 .start = TEGRA_SPI2_BASE,
211 .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
212 .flags = IORESOURCE_MEM,
213 },
214};
215
216static struct resource spi_resource3[] = {
217 [0] = {
218 .start = INT_SPI_3,
219 .end = INT_SPI_3,
220 .flags = IORESOURCE_IRQ,
221 },
222 [1] = {
223 .start = TEGRA_SPI3_BASE,
224 .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
225 .flags = IORESOURCE_MEM,
226 },
227};
228
229static struct resource spi_resource4[] = {
230 [0] = {
231 .start = INT_SPI_4,
232 .end = INT_SPI_4,
233 .flags = IORESOURCE_IRQ,
234 },
235 [1] = {
236 .start = TEGRA_SPI4_BASE,
237 .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
238 .flags = IORESOURCE_MEM,
239 },
240};
241#ifndef CONFIG_ARCH_TEGRA_2x_SOC
242static struct resource spi_resource5[] = {
243 [0] = {
244 .start = INT_SPI_5,
245 .end = INT_SPI_5,
246 .flags = IORESOURCE_IRQ,
247 },
248 [1] = {
249 .start = TEGRA_SPI5_BASE,
250 .end = TEGRA_SPI5_BASE + TEGRA_SPI5_SIZE-1,
251 .flags = IORESOURCE_MEM,
252 },
253};
254
255static struct resource spi_resource6[] = {
256 [0] = {
257 .start = INT_SPI_6,
258 .end = INT_SPI_6,
259 .flags = IORESOURCE_IRQ,
260 },
261 [1] = {
262 .start = TEGRA_SPI6_BASE,
263 .end = TEGRA_SPI6_BASE + TEGRA_SPI6_SIZE-1,
264 .flags = IORESOURCE_MEM,
265 },
266};
267#endif
268
269#ifndef CONFIG_ARCH_TEGRA_2x_SOC
270static struct resource dtv_resource[] = {
271 [0] = {
272 .start = INT_DTV,
273 .end = INT_DTV,
274 .flags = IORESOURCE_IRQ,
275 },
276 [1] = {
277 .start = TEGRA_DTV_BASE,
278 .end = TEGRA_DTV_BASE + TEGRA_DTV_SIZE - 1,
279 .flags = IORESOURCE_MEM,
280 },
281 [2] = {
282 .start = TEGRA_DMA_REQ_SEL_DTV,
283 .end = TEGRA_DMA_REQ_SEL_DTV,
284 .flags = IORESOURCE_DMA
285 },
286};
287#endif
288
289
290struct platform_device tegra_spi_device1 = {
291 .name = "spi_tegra",
292 .id = 0,
293 .resource = spi_resource1,
294 .num_resources = ARRAY_SIZE(spi_resource1),
295 .dev = {
296 .coherent_dma_mask = 0xffffffff,
297 },
298};
299
300struct platform_device tegra_spi_device2 = {
301 .name = "spi_tegra",
302 .id = 1,
303 .resource = spi_resource2,
304 .num_resources = ARRAY_SIZE(spi_resource2),
305 .dev = {
306 .coherent_dma_mask = 0xffffffff,
307 },
308};
309
310struct platform_device tegra_spi_device3 = {
311 .name = "spi_tegra",
312 .id = 2,
313 .resource = spi_resource3,
314 .num_resources = ARRAY_SIZE(spi_resource3),
315 .dev = {
316 .coherent_dma_mask = 0xffffffff,
317 },
318};
319
320struct platform_device tegra_spi_device4 = {
321 .name = "spi_tegra",
322 .id = 3,
323 .resource = spi_resource4,
324 .num_resources = ARRAY_SIZE(spi_resource4),
325 .dev = {
326 .coherent_dma_mask = 0xffffffff,
327 },
328};
329#ifndef CONFIG_ARCH_TEGRA_2x_SOC
330struct platform_device tegra_spi_device5 = {
331 .name = "spi_tegra",
332 .id = 4,
333 .resource = spi_resource5,
334 .num_resources = ARRAY_SIZE(spi_resource5),
335 .dev = {
336 .coherent_dma_mask = 0xffffffff,
337 },
338};
339
340struct platform_device tegra_spi_device6 = {
341 .name = "spi_tegra",
342 .id = 5,
343 .resource = spi_resource6,
344 .num_resources = ARRAY_SIZE(spi_resource6),
345 .dev = {
346 .coherent_dma_mask = 0xffffffff,
347 },
348};
349#endif
350
351struct platform_device tegra_spi_slave_device1 = {
352 .name = "spi_slave_tegra",
353 .id = 0,
354 .resource = spi_resource1,
355 .num_resources = ARRAY_SIZE(spi_resource1),
356 .dev = {
357 .coherent_dma_mask = 0xffffffff,
358 },
359};
360
361struct platform_device tegra_spi_slave_device2 = {
362 .name = "spi_slave_tegra",
363 .id = 1,
364 .resource = spi_resource2,
365 .num_resources = ARRAY_SIZE(spi_resource2),
366 .dev = {
367 .coherent_dma_mask = 0xffffffff,
368 },
369};
370
371struct platform_device tegra_spi_slave_device3 = {
372 .name = "spi_slave_tegra",
373 .id = 2,
374 .resource = spi_resource3,
375 .num_resources = ARRAY_SIZE(spi_resource3),
376 .dev = {
377 .coherent_dma_mask = 0xffffffff,
378 },
379};
380
381struct platform_device tegra_spi_slave_device4 = {
382 .name = "spi_slave_tegra",
383 .id = 3,
384 .resource = spi_resource4,
385 .num_resources = ARRAY_SIZE(spi_resource4),
386 .dev = {
387 .coherent_dma_mask = 0xffffffff,
388 },
389};
390#ifndef CONFIG_ARCH_TEGRA_2x_SOC
391struct platform_device tegra_spi_slave_device5 = {
392 .name = "spi_slave_tegra",
393 .id = 4,
394 .resource = spi_resource5,
395 .num_resources = ARRAY_SIZE(spi_resource5),
396 .dev = {
397 .coherent_dma_mask = 0xffffffff,
398 },
399};
400
401struct platform_device tegra_spi_slave_device6 = {
402 .name = "spi_slave_tegra",
403 .id = 5,
404 .resource = spi_resource6,
405 .num_resources = ARRAY_SIZE(spi_resource6),
406 .dev = {
407 .coherent_dma_mask = 0xffffffff,
408 },
409};
410#endif
411
412static struct resource resources_nor[] = {
413 [0] = {
414 .start = INT_SNOR,
415 .end = INT_SNOR,
416 .flags = IORESOURCE_IRQ,
417 },
418 [1] = {
419 /* Map SNOR Controller */
420 .start = TEGRA_SNOR_BASE,
421 .end = TEGRA_SNOR_BASE + TEGRA_SNOR_SIZE - 1,
422 .flags = IORESOURCE_MEM,
423 },
424 [2] = {
425 /* Map the size of flash */
426 .start = TEGRA_NOR_FLASH_BASE,
427 .end = TEGRA_NOR_FLASH_BASE + TEGRA_NOR_FLASH_SIZE - 1,
428 .flags = IORESOURCE_MEM,
429 }
430};
431
432struct platform_device tegra_nor_device = {
433 .name = "tegra-nor",
434 .id = -1,
435 .num_resources = ARRAY_SIZE(resources_nor),
436 .resource = resources_nor,
437 .dev = {
438 .coherent_dma_mask = 0xffffffff,
439 },
440};
441
442#ifndef CONFIG_ARCH_TEGRA_2x_SOC
443struct platform_device tegra_dtv_device = {
444 .name = "tegra_dtv",
445 .id = -1,
446 .resource = dtv_resource,
447 .num_resources = ARRAY_SIZE(dtv_resource),
448 .dev = {
449 .init_name = "dtv",
450 .coherent_dma_mask = 0xffffffff,
451 },
452};
453#endif
454
455static struct resource sdhci_resource1[] = {
456 [0] = {
457 .start = INT_SDMMC1,
458 .end = INT_SDMMC1,
459 .flags = IORESOURCE_IRQ,
460 },
461 [1] = {
462 .start = TEGRA_SDMMC1_BASE,
463 .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
464 .flags = IORESOURCE_MEM,
465 },
466};
467
468static struct resource sdhci_resource2[] = {
469 [0] = {
470 .start = INT_SDMMC2,
471 .end = INT_SDMMC2,
472 .flags = IORESOURCE_IRQ,
473 },
474 [1] = {
475 .start = TEGRA_SDMMC2_BASE,
476 .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
477 .flags = IORESOURCE_MEM,
478 },
479};
480
481static struct resource sdhci_resource3[] = {
482 [0] = {
483 .start = INT_SDMMC3,
484 .end = INT_SDMMC3,
485 .flags = IORESOURCE_IRQ,
486 },
487 [1] = {
488 .start = TEGRA_SDMMC3_BASE,
489 .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
490 .flags = IORESOURCE_MEM,
491 },
492};
493
494static struct resource sdhci_resource4[] = {
495 [0] = {
496 .start = INT_SDMMC4,
497 .end = INT_SDMMC4,
498 .flags = IORESOURCE_IRQ,
499 },
500 [1] = {
501 .start = TEGRA_SDMMC4_BASE,
502 .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
503 .flags = IORESOURCE_MEM,
504 },
505};
506
507struct platform_device tegra_pci_device = {
508 .name = "tegra-pcie",
509 .id = 0,
510 .resource = 0,
511 .num_resources = 0,
512 .dev = {
513 .platform_data = 0,
514 },
515};
516
517/* board files should fill in platform_data register the devices themselvs.
518 * See board-harmony.c for an example
519 */
520struct platform_device tegra_sdhci_device1 = {
521 .name = "sdhci-tegra",
522 .id = 0,
523 .resource = sdhci_resource1,
524 .num_resources = ARRAY_SIZE(sdhci_resource1),
525};
526
527struct platform_device tegra_sdhci_device2 = {
528 .name = "sdhci-tegra",
529 .id = 1,
530 .resource = sdhci_resource2,
531 .num_resources = ARRAY_SIZE(sdhci_resource2),
532};
533
534struct platform_device tegra_sdhci_device3 = {
535 .name = "sdhci-tegra",
536 .id = 2,
537 .resource = sdhci_resource3,
538 .num_resources = ARRAY_SIZE(sdhci_resource3),
539};
540
541struct platform_device tegra_sdhci_device4 = {
542 .name = "sdhci-tegra",
543 .id = 3,
544 .resource = sdhci_resource4,
545 .num_resources = ARRAY_SIZE(sdhci_resource4),
546};
547
548static struct resource tegra_usb1_resources[] = {
549 [0] = {
550 .start = TEGRA_USB_BASE,
551 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
552 .flags = IORESOURCE_MEM,
553 },
554 [1] = {
555 .start = INT_USB,
556 .end = INT_USB,
557 .flags = IORESOURCE_IRQ,
558 },
559};
560
561static struct resource tegra_usb2_resources[] = {
562 [0] = {
563 .start = TEGRA_USB2_BASE,
564 .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
565 .flags = IORESOURCE_MEM,
566 },
567 [1] = {
568 .start = INT_USB2,
569 .end = INT_USB2,
570 .flags = IORESOURCE_IRQ,
571 },
572};
573
574static struct resource tegra_usb3_resources[] = {
575 [0] = {
576 .start = TEGRA_USB3_BASE,
577 .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
578 .flags = IORESOURCE_MEM,
579 },
580 [1] = {
581 .start = INT_USB3,
582 .end = INT_USB3,
583 .flags = IORESOURCE_IRQ,
584 },
585};
586
587static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
588 /* All existing boards use GPIO PV0 for phy reset */
589 .reset_gpio = TEGRA_GPIO_PV0,
590 .clk = "cdev2",
591};
592
593static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
594 .operating_mode = TEGRA_USB_OTG,
595 .power_down_on_bus_suspend = 1,
596};
597
598static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
599 .phy_config = &tegra_ehci2_ulpi_phy_config,
600 .operating_mode = TEGRA_USB_HOST,
601 .power_down_on_bus_suspend = 1,
602};
603
604static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
605 .operating_mode = TEGRA_USB_HOST,
606 .power_down_on_bus_suspend = 1,
607};
608
609static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
610
611struct platform_device tegra_ehci1_device = {
612 .name = "tegra-ehci",
613 .id = 0,
614 .dev = {
615 .dma_mask = &tegra_ehci_dmamask,
616 .coherent_dma_mask = DMA_BIT_MASK(32),
617 .platform_data = &tegra_ehci1_pdata,
618 },
619 .resource = tegra_usb1_resources,
620 .num_resources = ARRAY_SIZE(tegra_usb1_resources),
621};
622
623struct platform_device tegra_ehci2_device = {
624 .name = "tegra-ehci",
625 .id = 1,
626 .dev = {
627 .dma_mask = &tegra_ehci_dmamask,
628 .coherent_dma_mask = DMA_BIT_MASK(32),
629 .platform_data = &tegra_ehci2_pdata,
630 },
631 .resource = tegra_usb2_resources,
632 .num_resources = ARRAY_SIZE(tegra_usb2_resources),
633};
634
635struct platform_device tegra_ehci3_device = {
636 .name = "tegra-ehci",
637 .id = 2,
638 .dev = {
639 .dma_mask = &tegra_ehci_dmamask,
640 .coherent_dma_mask = DMA_BIT_MASK(32),
641 .platform_data = &tegra_ehci3_pdata,
642 },
643 .resource = tegra_usb3_resources,
644 .num_resources = ARRAY_SIZE(tegra_usb3_resources),
645};
646
647static struct resource tegra_pmu_resources[] = {
648 [0] = {
649 .start = INT_CPU0_PMU_INTR,
650 .end = INT_CPU0_PMU_INTR,
651 .flags = IORESOURCE_IRQ,
652 },
653 [1] = {
654 .start = INT_CPU1_PMU_INTR,
655 .end = INT_CPU1_PMU_INTR,
656 .flags = IORESOURCE_IRQ,
657 },
658#ifndef CONFIG_ARCH_TEGRA_2x_SOC
659 [2] = {
660 .start = INT_CPU2_PMU_INTR,
661 .end = INT_CPU2_PMU_INTR,
662 .flags = IORESOURCE_IRQ,
663 },
664 [3] = {
665 .start = INT_CPU3_PMU_INTR,
666 .end = INT_CPU3_PMU_INTR,
667 .flags = IORESOURCE_IRQ,
668 },
669#endif
670};
671
672struct platform_device tegra_pmu_device = {
673 .name = "arm-pmu",
674 .id = ARM_PMU_DEVICE_CPU,
675 .num_resources = ARRAY_SIZE(tegra_pmu_resources),
676 .resource = tegra_pmu_resources,
677};
678
679static struct resource tegra_uarta_resources[] = {
680 [0] = {
681 .start = TEGRA_UARTA_BASE,
682 .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
683 .flags = IORESOURCE_MEM,
684 },
685 [1] = {
686 .start = INT_UARTA,
687 .end = INT_UARTA,
688 .flags = IORESOURCE_IRQ,
689 },
690};
691
692static struct resource tegra_uartb_resources[] = {
693 [0] = {
694 .start = TEGRA_UARTB_BASE,
695 .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
696 .flags = IORESOURCE_MEM,
697 },
698 [1] = {
699 .start = INT_UARTB,
700 .end = INT_UARTB,
701 .flags = IORESOURCE_IRQ,
702 },
703};
704
705static struct resource tegra_uartc_resources[] = {
706 [0] = {
707 .start = TEGRA_UARTC_BASE,
708 .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
709 .flags = IORESOURCE_MEM,
710 },
711 [1] = {
712 .start = INT_UARTC,
713 .end = INT_UARTC,
714 .flags = IORESOURCE_IRQ,
715 },
716};
717
718static struct resource tegra_uartd_resources[] = {
719 [0] = {
720 .start = TEGRA_UARTD_BASE,
721 .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
722 .flags = IORESOURCE_MEM,
723 },
724 [1] = {
725 .start = INT_UARTD,
726 .end = INT_UARTD,
727 .flags = IORESOURCE_IRQ,
728 },
729};
730
731static struct resource tegra_uarte_resources[] = {
732 [0] = {
733 .start = TEGRA_UARTE_BASE,
734 .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
735 .flags = IORESOURCE_MEM,
736 },
737 [1] = {
738 .start = INT_UARTE,
739 .end = INT_UARTE,
740 .flags = IORESOURCE_IRQ,
741 },
742};
743
744struct platform_device tegra_uarta_device = {
745 .name = "tegra_uart",
746 .id = 0,
747 .num_resources = ARRAY_SIZE(tegra_uarta_resources),
748 .resource = tegra_uarta_resources,
749 .dev = {
750 .coherent_dma_mask = DMA_BIT_MASK(32),
751 },
752};
753
754struct platform_device tegra_uartb_device = {
755 .name = "tegra_uart",
756 .id = 1,
757 .num_resources = ARRAY_SIZE(tegra_uartb_resources),
758 .resource = tegra_uartb_resources,
759 .dev = {
760 .coherent_dma_mask = DMA_BIT_MASK(32),
761 },
762};
763
764struct platform_device tegra_uartc_device = {
765 .name = "tegra_uart",
766 .id = 2,
767 .num_resources = ARRAY_SIZE(tegra_uartc_resources),
768 .resource = tegra_uartc_resources,
769 .dev = {
770 .coherent_dma_mask = DMA_BIT_MASK(32),
771 },
772};
773
774struct platform_device tegra_uartd_device = {
775 .name = "tegra_uart",
776 .id = 3,
777 .num_resources = ARRAY_SIZE(tegra_uartd_resources),
778 .resource = tegra_uartd_resources,
779 .dev = {
780 .coherent_dma_mask = DMA_BIT_MASK(32),
781 },
782};
783
784struct platform_device tegra_uarte_device = {
785 .name = "tegra_uart",
786 .id = 4,
787 .num_resources = ARRAY_SIZE(tegra_uarte_resources),
788 .resource = tegra_uarte_resources,
789 .dev = {
790 .coherent_dma_mask = DMA_BIT_MASK(32),
791 },
792};
793
794static struct plat_serial8250_port debug_uarta_platform_data[] = {
795 {
796 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
797 .mapbase = TEGRA_UARTA_BASE,
798 .irq = INT_UARTA,
799 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
800 .type = PORT_TEGRA,
801 .iotype = UPIO_MEM,
802 .regshift = 2,
803 },
804 {
805 .flags = 0,
806 },
807};
808
809static struct plat_serial8250_port debug_uartb_platform_data[] = {
810 {
811 .membase = IO_ADDRESS(TEGRA_UARTB_BASE),
812 .mapbase = TEGRA_UARTB_BASE,
813 .irq = INT_UARTB,
814 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
815 .type = PORT_TEGRA,
816 .iotype = UPIO_MEM,
817 .regshift = 2,
818 },
819 {
820 .flags = 0,
821 },
822};
823
824static struct plat_serial8250_port debug_uartc_platform_data[] = {
825 {
826 .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
827 .mapbase = TEGRA_UARTC_BASE,
828 .irq = INT_UARTC,
829 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
830 .type = PORT_TEGRA,
831 .iotype = UPIO_MEM,
832 .regshift = 2,
833 },
834 {
835 .flags = 0,
836 },
837};
838
839static struct plat_serial8250_port debug_uartd_platform_data[] = {
840 {
841 .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
842 .mapbase = TEGRA_UARTD_BASE,
843 .irq = INT_UARTD,
844 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
845 .type = PORT_TEGRA,
846 .iotype = UPIO_MEM,
847 .regshift = 2,
848 },
849 {
850 .flags = 0,
851 },
852};
853
854#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
855static struct plat_serial8250_port debug_uarte_platform_data[] = {
856 {
857 .membase = IO_ADDRESS(TEGRA_UARTE_BASE),
858 .mapbase = TEGRA_UARTE_BASE,
859 .irq = INT_UARTE,
860 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
861 .type = PORT_TEGRA,
862 .iotype = UPIO_MEM,
863 .regshift = 2,
864 },
865 {
866 .flags = 0,
867 },
868};
869#endif
870
871struct platform_device debug_uarta_device = {
872 .name = "serial8250",
873 .id = PLAT8250_DEV_PLATFORM,
874 .dev = {
875 .platform_data = debug_uarta_platform_data,
876 },
877};
878
879struct platform_device debug_uartb_device = {
880 .name = "serial8250",
881 .id = PLAT8250_DEV_PLATFORM,
882 .dev = {
883 .platform_data = debug_uartb_platform_data,
884 },
885};
886
887struct platform_device debug_uartc_device = {
888 .name = "serial8250",
889 .id = PLAT8250_DEV_PLATFORM,
890 .dev = {
891 .platform_data = debug_uartc_platform_data,
892 },
893};
894
895struct platform_device debug_uartd_device = {
896 .name = "serial8250",
897 .id = PLAT8250_DEV_PLATFORM,
898 .dev = {
899 .platform_data = debug_uartd_platform_data,
900 },
901};
902
903#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
904struct platform_device debug_uarte_device = {
905 .name = "serial8250",
906 .id = PLAT8250_DEV_PLATFORM,
907 .dev = {
908 .platform_data = debug_uarte_platform_data,
909 },
910};
911#endif
912
913#ifdef CONFIG_ARCH_TEGRA_2x_SOC
914static struct resource i2s_resource1[] = {
915 [0] = {
916 .start = INT_I2S1,
917 .end = INT_I2S1,
918 .flags = IORESOURCE_IRQ
919 },
920 [1] = {
921 .start = TEGRA_DMA_REQ_SEL_I2S_1,
922 .end = TEGRA_DMA_REQ_SEL_I2S_1,
923 .flags = IORESOURCE_DMA
924 },
925 [2] = {
926 .start = TEGRA_I2S1_BASE,
927 .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
928 .flags = IORESOURCE_MEM
929 }
930};
931
932struct platform_device tegra_i2s_device1 = {
933 .name = "tegra20-i2s",
934 .id = 0,
935 .resource = i2s_resource1,
936 .num_resources = ARRAY_SIZE(i2s_resource1),
937};
938
939static struct resource i2s_resource2[] = {
940 [0] = {
941 .start = INT_I2S2,
942 .end = INT_I2S2,
943 .flags = IORESOURCE_IRQ
944 },
945 [1] = {
946 .start = TEGRA_DMA_REQ_SEL_I2S2_1,
947 .end = TEGRA_DMA_REQ_SEL_I2S2_1,
948 .flags = IORESOURCE_DMA
949 },
950 [2] = {
951 .start = TEGRA_I2S2_BASE,
952 .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
953 .flags = IORESOURCE_MEM
954 }
955};
956
957struct platform_device tegra_i2s_device2 = {
958 .name = "tegra20-i2s",
959 .id = 1,
960 .resource = i2s_resource2,
961 .num_resources = ARRAY_SIZE(i2s_resource2),
962};
963#else
964static struct resource i2s_resource0[] = {
965 [0] = {
966 .start = TEGRA_I2S0_BASE,
967 .end = TEGRA_I2S0_BASE + TEGRA_I2S0_SIZE - 1,
968 .flags = IORESOURCE_MEM
969 }
970};
971
972struct platform_device tegra_i2s_device0 = {
973 .name = "tegra30-i2s",
974 .id = 0,
975 .resource = i2s_resource0,
976 .num_resources = ARRAY_SIZE(i2s_resource0),
977};
978
979static struct resource i2s_resource1[] = {
980 [0] = {
981 .start = TEGRA_I2S1_BASE,
982 .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
983 .flags = IORESOURCE_MEM
984 }
985};
986
987struct platform_device tegra_i2s_device1 = {
988 .name = "tegra30-i2s",
989 .id = 1,
990 .resource = i2s_resource1,
991 .num_resources = ARRAY_SIZE(i2s_resource1),
992};
993
994static struct resource i2s_resource2[] = {
995 [0] = {
996 .start = TEGRA_I2S2_BASE,
997 .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
998 .flags = IORESOURCE_MEM
999 }
1000};
1001
1002struct platform_device tegra_i2s_device2 = {
1003 .name = "tegra30-i2s",
1004 .id = 2,
1005 .resource = i2s_resource2,
1006 .num_resources = ARRAY_SIZE(i2s_resource2),
1007};
1008
1009static struct resource i2s_resource3[] = {
1010 [0] = {
1011 .start = TEGRA_I2S3_BASE,
1012 .end = TEGRA_I2S3_BASE + TEGRA_I2S3_SIZE - 1,
1013 .flags = IORESOURCE_MEM
1014 }
1015};
1016
1017struct platform_device tegra_i2s_device3 = {
1018 .name = "tegra30-i2s",
1019 .id = 3,
1020 .resource = i2s_resource3,
1021 .num_resources = ARRAY_SIZE(i2s_resource3),
1022};
1023
1024static struct resource i2s_resource4[] = {
1025 [0] = {
1026 .start = TEGRA_I2S4_BASE,
1027 .end = TEGRA_I2S4_BASE + TEGRA_I2S4_SIZE - 1,
1028 .flags = IORESOURCE_MEM
1029 }
1030};
1031
1032struct platform_device tegra_i2s_device4 = {
1033 .name = "tegra30-i2s",
1034 .id = 4,
1035 .resource = i2s_resource4,
1036 .num_resources = ARRAY_SIZE(i2s_resource4),
1037};
1038#endif
1039
1040#ifdef CONFIG_ARCH_TEGRA_2x_SOC
1041static struct resource spdif_resource[] = {
1042 [0] = {
1043 .start = INT_SPDIF,
1044 .end = INT_SPDIF,
1045 .flags = IORESOURCE_IRQ
1046 },
1047 [1] = {
1048 .start = TEGRA_DMA_REQ_SEL_SPD_I,
1049 .end = TEGRA_DMA_REQ_SEL_SPD_I,
1050 .flags = IORESOURCE_DMA
1051 },
1052 [2] = {
1053 .start = TEGRA_SPDIF_BASE,
1054 .end = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1055 .flags = IORESOURCE_MEM
1056 }
1057};
1058
1059struct platform_device tegra_spdif_device = {
1060 .name = "tegra20-spdif",
1061 .id = -1,
1062 .resource = spdif_resource,
1063 .num_resources = ARRAY_SIZE(spdif_resource),
1064};
1065#else
1066static struct resource spdif_resource[] = {
1067 [0] = {
1068 .start = TEGRA_SPDIF_BASE,
1069 .end = TEGRA_SPDIF_BASE + TEGRA_SPDIF_SIZE - 1,
1070 .flags = IORESOURCE_MEM
1071 }
1072};
1073
1074struct platform_device tegra_spdif_device = {
1075 .name = "tegra30-spdif",
1076 .id = -1,
1077 .resource = spdif_resource,
1078 .num_resources = ARRAY_SIZE(spdif_resource),
1079};
1080#endif
1081
1082#ifndef CONFIG_ARCH_TEGRA_2x_SOC
1083static struct resource ahub_resource[] = {
1084 [0] = {
1085 .start = TEGRA_APBIF0_BASE,
1086 .end = TEGRA_APBIF3_BASE + TEGRA_APBIF3_SIZE - 1,
1087 .flags = IORESOURCE_MEM
1088 },
1089 [1] = {
1090 .start = TEGRA_AHUB_BASE,
1091 .end = TEGRA_AHUB_BASE + TEGRA_AHUB_SIZE - 1,
1092 .flags = IORESOURCE_MEM
1093 }
1094};
1095
1096struct platform_device tegra_ahub_device = {
1097 .name = "tegra30-ahub",
1098 .id = -1,
1099 .resource = ahub_resource,
1100 .num_resources = ARRAY_SIZE(ahub_resource),
1101};
1102
1103static struct resource dam_resource0[] = {
1104 [0] = {
1105 .start = TEGRA_DAM0_BASE,
1106 .end = TEGRA_DAM0_BASE + TEGRA_DAM0_SIZE - 1,
1107 .flags = IORESOURCE_MEM
1108 }
1109};
1110
1111struct platform_device tegra_dam_device0 = {
1112 .name = "tegra30-dam",
1113 .id = 0,
1114 .resource = dam_resource0,
1115 .num_resources = ARRAY_SIZE(dam_resource0),
1116};
1117
1118static struct resource dam_resource1[] = {
1119 [0] = {
1120 .start = TEGRA_DAM1_BASE,
1121 .end = TEGRA_DAM1_BASE + TEGRA_DAM1_SIZE - 1,
1122 .flags = IORESOURCE_MEM
1123 }
1124};
1125
1126struct platform_device tegra_dam_device1 = {
1127 .name = "tegra30-dam",
1128 .id = 1,
1129 .resource = dam_resource1,
1130 .num_resources = ARRAY_SIZE(dam_resource1),
1131};
1132
1133static struct resource dam_resource2[] = {
1134 [0] = {
1135 .start = TEGRA_DAM2_BASE,
1136 .end = TEGRA_DAM2_BASE + TEGRA_DAM2_SIZE - 1,
1137 .flags = IORESOURCE_MEM
1138 }
1139};
1140
1141struct platform_device tegra_dam_device2 = {
1142 .name = "tegra30-dam",
1143 .id = 2,
1144 .resource = dam_resource2,
1145 .num_resources = ARRAY_SIZE(dam_resource2),
1146};
1147
1148static u64 tegra_hda_dma_mask = DMA_BIT_MASK(32);
1149static struct resource hda_platform_resources[] = {
1150 [0] = {
1151 .start = TEGRA_HDA_BASE,
1152 .end = TEGRA_HDA_BASE + TEGRA_HDA_SIZE - 1,
1153 .flags = IORESOURCE_MEM
1154 },
1155 [1] = {
1156 .start = INT_HDA,
1157 .end = INT_HDA,
1158 .flags = IORESOURCE_IRQ
1159 },
1160};
1161
1162struct platform_device tegra_hda_device = {
1163 .name = "tegra30-hda",
1164 .id = -1,
1165 .dev = {
1166 .coherent_dma_mask = DMA_BIT_MASK(32),
1167 .dma_mask = &tegra_hda_dma_mask,
1168 },
1169 .resource = hda_platform_resources,
1170 .num_resources = ARRAY_SIZE(hda_platform_resources),
1171};
1172#endif
1173
1174struct platform_device spdif_dit_device = {
1175 .name = "spdif-dit",
1176 .id = 0,
1177};
1178
1179struct platform_device bluetooth_dit_device = {
1180 .name = "spdif-dit",
1181 .id = 1,
1182};
1183
1184struct platform_device baseband_dit_device = {
1185 .name = "spdif-dit",
1186 .id = 2,
1187};
1188
1189struct platform_device tegra_pcm_device = {
1190 .name = "tegra-pcm-audio",
1191 .id = -1,
1192};
1193
1194static struct resource w1_resources[] = {
1195 [0] = {
1196 .start = INT_OWR,
1197 .end = INT_OWR,
1198 .flags = IORESOURCE_IRQ
1199 },
1200 [1] = {
1201 .start = TEGRA_OWR_BASE,
1202 .end = TEGRA_OWR_BASE + TEGRA_OWR_SIZE - 1,
1203 .flags = IORESOURCE_MEM
1204 }
1205};
1206
1207struct platform_device tegra_w1_device = {
1208 .name = "tegra_w1",
1209 .id = -1,
1210 .resource = w1_resources,
1211 .num_resources = ARRAY_SIZE(w1_resources),
1212};
1213
1214static struct resource tegra_udc_resources[] = {
1215 [0] = {
1216 .start = TEGRA_USB_BASE,
1217 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1218 .flags = IORESOURCE_MEM,
1219 },
1220 [1] = {
1221 .start = INT_USB,
1222 .end = INT_USB,
1223 .flags = IORESOURCE_IRQ,
1224 },
1225};
1226
1227static u64 tegra_udc_dmamask = DMA_BIT_MASK(32);
1228
1229static struct fsl_usb2_platform_data tegra_udc_pdata = {
1230 .operating_mode = FSL_USB2_DR_DEVICE,
1231 .phy_mode = FSL_USB2_PHY_UTMI,
1232};
1233
1234struct platform_device tegra_udc_device = {
1235 .name = "fsl-tegra-udc",
1236 .id = -1,
1237 .dev = {
1238 .dma_mask = &tegra_udc_dmamask,
1239 .coherent_dma_mask = DMA_BIT_MASK(32),
1240 .platform_data = &tegra_udc_pdata,
1241 },
1242 .resource = tegra_udc_resources,
1243 .num_resources = ARRAY_SIZE(tegra_udc_resources),
1244};
1245
1246static struct resource tegra_otg_resources[] = {
1247 [0] = {
1248 .start = TEGRA_USB_BASE,
1249 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
1250 .flags = IORESOURCE_MEM,
1251 },
1252 [1] = {
1253 .start = INT_USB,
1254 .end = INT_USB,
1255 .flags = IORESOURCE_IRQ,
1256 },
1257};
1258
1259struct platform_device tegra_otg_device = {
1260 .name = "tegra-otg",
1261 .id = -1,
1262 .resource = tegra_otg_resources,
1263 .num_resources = ARRAY_SIZE(tegra_otg_resources),
1264};
1265
1266#ifdef CONFIG_SATA_AHCI_TEGRA
1267static u64 tegra_sata_dma_mask = DMA_BIT_MASK(32);
1268
1269static struct resource tegra_sata_resources[] = {
1270 [0] = {
1271 .start = TEGRA_SATA_BAR5_BASE,
1272 .end = TEGRA_SATA_BAR5_BASE + TEGRA_SATA_BAR5_SIZE - 1,
1273 .flags = IORESOURCE_MEM,
1274 },
1275 [1] = {
1276 .start = TEGRA_SATA_CONFIG_BASE,
1277 .end = TEGRA_SATA_CONFIG_BASE + TEGRA_SATA_CONFIG_SIZE - 1,
1278 .flags = IORESOURCE_MEM,
1279 },
1280 [2] = {
1281 .start = INT_SATA_CTL,
1282 .end = INT_SATA_CTL,
1283 .flags = IORESOURCE_IRQ,
1284 },
1285};
1286
1287struct platform_device tegra_sata_device = {
1288 .name = "tegra-sata",
1289 .id = 0,
1290 .dev = {
1291 .platform_data = 0,
1292 .coherent_dma_mask = DMA_BIT_MASK(32),
1293 .dma_mask = &tegra_sata_dma_mask,
1294 },
1295 .resource = tegra_sata_resources,
1296 .num_resources = ARRAY_SIZE(tegra_sata_resources),
1297};
1298#endif
1299
1300#ifdef CONFIG_ARCH_TEGRA_2x_SOC
1301static struct resource das_resource[] = {
1302 [0] = {
1303 .start = TEGRA_APB_MISC_DAS_BASE,
1304 .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
1305 .flags = IORESOURCE_MEM
1306 }
1307};
1308
1309struct platform_device tegra_das_device = {
1310 .name = "tegra20-das",
1311 .id = -1,
1312 .resource = das_resource,
1313 .num_resources = ARRAY_SIZE(das_resource),
1314};
1315#endif
1316
1317#if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
1318static struct resource tegra_gart_resources[] = {
1319 [0] = {
1320 .name = "mc",
1321 .flags = IORESOURCE_MEM,
1322 .start = TEGRA_MC_BASE,
1323 .end = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1324 },
1325 [1] = {
1326 .name = "gart",
1327 .flags = IORESOURCE_MEM,
1328 .start = TEGRA_GART_BASE,
1329 .end = TEGRA_GART_BASE + TEGRA_GART_SIZE - 1,
1330 }
1331};
1332
1333struct platform_device tegra_gart_device = {
1334 .name = "tegra_gart",
1335 .id = -1,
1336 .num_resources = ARRAY_SIZE(tegra_gart_resources),
1337 .resource = tegra_gart_resources
1338};
1339#endif
1340
1341#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
1342static struct resource tegra_smmu_resources[] = {
1343 [0] = {
1344 .name = "mc",
1345 .flags = IORESOURCE_MEM,
1346 .start = TEGRA_MC_BASE,
1347 .end = TEGRA_MC_BASE + TEGRA_MC_SIZE - 1,
1348 },
1349 [1] = {
1350 .name = "ahbarb",
1351 .flags = IORESOURCE_MEM,
1352 .start = TEGRA_AHB_ARB_BASE,
1353 .end = TEGRA_AHB_ARB_BASE + TEGRA_AHB_ARB_SIZE - 1,
1354 }
1355};
1356
1357struct platform_device tegra_smmu_device = {
1358 .name = "tegra_smmu",
1359 .id = -1,
1360 .num_resources = ARRAY_SIZE(tegra_smmu_resources),
1361 .resource = tegra_smmu_resources
1362};
1363
1364
1365static struct tegra_smmu_window tegra_smmu[] = {
1366 [0] = {
1367 .start = TEGRA_SMMU_BASE,
1368 .end = TEGRA_SMMU_BASE + TEGRA_SMMU_SIZE - 1,
1369 },
1370};
1371
1372struct tegra_smmu_window *tegra_smmu_window(int wnum)
1373{
1374 return &tegra_smmu[wnum];
1375}
1376
1377int tegra_smmu_window_count(void)
1378{
1379 return ARRAY_SIZE(tegra_smmu);
1380}
1381#endif
1382
1383#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
1384#define CLK_RESET_RST_SOURCE 0x0
1385static struct resource tegra_wdt_resources[] = {
1386 [0] = {
1387 .start = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE,
1388 .end = TEGRA_CLK_RESET_BASE + CLK_RESET_RST_SOURCE + 4 - 1,
1389 .flags = IORESOURCE_MEM,
1390 },
1391 [1] = {
1392 .start = TEGRA_TMR1_BASE,
1393 .end = TEGRA_TMR1_BASE + TEGRA_TMR1_SIZE - 1,
1394 .flags = IORESOURCE_MEM,
1395 },
1396 [2] = {
1397 .start = INT_TMR1,
1398 .end = INT_TMR1,
1399 .flags = IORESOURCE_IRQ,
1400 },
1401};
1402#else
1403static struct resource tegra_wdt_resources[] = {
1404 [0] = {
1405 .start = TEGRA_WDT0_BASE,
1406 .end = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
1407 .flags = IORESOURCE_MEM,
1408 },
1409 [1] = {
1410 .start = TEGRA_TMR10_BASE,
1411 .end = TEGRA_TMR10_BASE + TEGRA_TMR10_SIZE - 1,
1412 .flags = IORESOURCE_MEM,
1413 },
1414 [2] = {
1415 .start = INT_WDT_CPU,
1416 .end = INT_WDT_CPU,
1417 .flags = IORESOURCE_IRQ,
1418 },
1419};
1420#endif
1421
1422struct platform_device tegra_wdt_device = {
1423 .name = "tegra_wdt",
1424 .id = -1,
1425 .num_resources = ARRAY_SIZE(tegra_wdt_resources),
1426 .resource = tegra_wdt_resources,
1427};
1428
1429static struct resource tegra_pwfm0_resource = {
1430 .start = TEGRA_PWFM0_BASE,
1431 .end = TEGRA_PWFM0_BASE + TEGRA_PWFM0_SIZE - 1,
1432 .flags = IORESOURCE_MEM,
1433};
1434
1435static struct resource tegra_pwfm1_resource = {
1436 .start = TEGRA_PWFM1_BASE,
1437 .end = TEGRA_PWFM1_BASE + TEGRA_PWFM1_SIZE - 1,
1438 .flags = IORESOURCE_MEM,
1439};
1440
1441static struct resource tegra_pwfm2_resource = {
1442 .start = TEGRA_PWFM2_BASE,
1443 .end = TEGRA_PWFM2_BASE + TEGRA_PWFM2_SIZE - 1,
1444 .flags = IORESOURCE_MEM,
1445};
1446
1447static struct resource tegra_pwfm3_resource = {
1448 .start = TEGRA_PWFM3_BASE,
1449 .end = TEGRA_PWFM3_BASE + TEGRA_PWFM3_SIZE - 1,
1450 .flags = IORESOURCE_MEM,
1451};
1452
1453struct platform_device tegra_pwfm0_device = {
1454 .name = "tegra_pwm",
1455 .id = 0,
1456 .num_resources = 1,
1457 .resource = &tegra_pwfm0_resource,
1458};
1459
1460struct platform_device tegra_pwfm1_device = {
1461 .name = "tegra_pwm",
1462 .id = 1,
1463 .num_resources = 1,
1464 .resource = &tegra_pwfm1_resource,
1465};
1466
1467struct platform_device tegra_pwfm2_device = {
1468 .name = "tegra_pwm",
1469 .id = 2,
1470 .num_resources = 1,
1471 .resource = &tegra_pwfm2_resource,
1472};
1473
1474struct platform_device tegra_pwfm3_device = {
1475 .name = "tegra_pwm",
1476 .id = 3,
1477 .num_resources = 1,
1478 .resource = &tegra_pwfm3_resource,
1479};
1480
1481static struct tegra_avp_platform_data tegra_avp_pdata = {
1482#ifdef CONFIG_ARCH_TEGRA_2x_SOC
1483 .emc_clk_rate = ULONG_MAX,
1484#else
1485 .emc_clk_rate = 200000000,
1486#endif
1487};
1488
1489struct resource tegra_nvavp_resources[] = {
1490 [0] = {
1491 .start = INT_SHR_SEM_INBOX_IBF,
1492 .end = INT_SHR_SEM_INBOX_IBF,
1493 .flags = IORESOURCE_IRQ,
1494 .name = "mbox_from_nvavp_pending",
1495 },
1496};
1497
1498struct nvhost_device nvavp_device = {
1499 .name = "nvavp",
1500 .id = -1,
1501 .resource = tegra_nvavp_resources,
1502 .num_resources = ARRAY_SIZE(tegra_nvavp_resources),
1503};
1504
1505static struct resource tegra_avp_resources[] = {
1506 [0] = {
1507 .start = INT_SHR_SEM_INBOX_IBF,
1508 .end = INT_SHR_SEM_INBOX_IBF,
1509 .flags = IORESOURCE_IRQ,
1510 .name = "mbox_from_avp_pending",
1511 },
1512};
1513
1514struct platform_device tegra_avp_device = {
1515 .name = "tegra-avp",
1516 .id = -1,
1517 .num_resources = ARRAY_SIZE(tegra_avp_resources),
1518 .resource = tegra_avp_resources,
1519 .dev = {
1520 .coherent_dma_mask = 0xffffffffULL,
1521 .platform_data = &tegra_avp_pdata,
1522 },
1523};
1524
1525static struct resource tegra_aes_resources[] = {
1526 {
1527 .start = TEGRA_VDE_BASE,
1528 .end = TEGRA_VDE_BASE + TEGRA_VDE_SIZE - 1,
1529 .flags = IORESOURCE_MEM,
1530 },
1531 {
1532 .start = TEGRA_BSEA_BASE,
1533 .end = TEGRA_BSEA_BASE + TEGRA_BSEA_SIZE - 1,
1534 .flags = IORESOURCE_MEM,
1535 },
1536};
1537
1538static u64 tegra_aes_dma_mask = DMA_BIT_MASK(32);
1539
1540struct platform_device tegra_aes_device = {
1541 .name = "tegra-aes",
1542 .id = -1,
1543 .resource = tegra_aes_resources,
1544 .num_resources = ARRAY_SIZE(tegra_aes_resources),
1545 .dev = {
1546 .dma_mask = &tegra_aes_dma_mask,
1547 .coherent_dma_mask = DMA_BIT_MASK(32),
1548 },
1549};
1550
1551static struct resource tegra_kbc_resources[] = {
1552 [0] = {
1553 .start = TEGRA_KBC_BASE,
1554 .end = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
1555 .flags = IORESOURCE_MEM,
1556 },
1557 [1] = {
1558 .start = INT_KBC,
1559 .end = INT_KBC,
1560 .flags = IORESOURCE_IRQ,
1561 },
1562};
1563
1564struct platform_device tegra_kbc_device = {
1565 .name = "tegra-kbc",
1566 .id = -1,
1567 .resource = tegra_kbc_resources,
1568 .num_resources = ARRAY_SIZE(tegra_kbc_resources),
1569 .dev = {
1570 .platform_data = 0,
1571 },
1572};
1573
1574#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
1575static struct resource tegra_tsensor_resources[]= {
1576 {
1577 .start = TEGRA_TSENSOR_BASE,
1578 .end = TEGRA_TSENSOR_BASE + TEGRA_TSENSOR_SIZE - 1,
1579 .flags = IORESOURCE_MEM,
1580 },
1581 {
1582 .start = INT_TSENSOR,
1583 .end = INT_TSENSOR,
1584 .flags = IORESOURCE_IRQ,
1585 },
1586 {
1587 .start = TEGRA_PMC_BASE + 0x1B0,
1588 /* 2 pmc registers mapped */
1589 .end = TEGRA_PMC_BASE + 0x1B0 + (2 * 4),
1590 .flags = IORESOURCE_MEM,
1591 },
1592};
1593
1594struct platform_device tegra_tsensor_device = {
1595 .name = "tegra-tsensor",
1596 .id = -1,
1597 .num_resources = ARRAY_SIZE(tegra_tsensor_resources),
1598 .resource = tegra_tsensor_resources,
1599 .dev = {
1600 .platform_data = 0,
1601 },
1602};
1603#endif
1604
1605#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1606static u64 tegra_se_dma_mask = DMA_BIT_MASK(32);
1607
1608struct resource tegra_se_resources[] = {
1609 [0] = {
1610 .start = TEGRA_SE_BASE,
1611 .end = TEGRA_SE_BASE + TEGRA_SE_SIZE - 1,
1612 .flags = IORESOURCE_MEM,
1613 },
1614 [1] = {
1615 .start = TEGRA_PMC_BASE,
1616 .end = TEGRA_PMC_BASE + SZ_256 - 1,
1617 .flags = IORESOURCE_MEM,
1618 },
1619 [2] = {
1620 .start = INT_SE,
1621 .end = INT_SE,
1622 .flags = IORESOURCE_IRQ,
1623 },
1624};
1625
1626struct platform_device tegra_se_device = {
1627 .name = "tegra-se",
1628 .id = -1,
1629 .dev = {
1630 .coherent_dma_mask = DMA_BIT_MASK(32),
1631 .dma_mask = &tegra_se_dma_mask,
1632 },
1633 .resource = tegra_se_resources,
1634 .num_resources = ARRAY_SIZE(tegra_se_resources),
1635};
1636#endif
1637
1638static struct resource tegra_disp1_resources[] = {
1639 {
1640 .name = "irq",
1641 .start = INT_DISPLAY_GENERAL,
1642 .end = INT_DISPLAY_GENERAL,
1643 .flags = IORESOURCE_IRQ,
1644 },
1645 {
1646 .name = "regs",
1647 .start = TEGRA_DISPLAY_BASE,
1648 .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
1649 .flags = IORESOURCE_MEM,
1650 },
1651 {
1652 .name = "fbmem",
1653 .start = 0,
1654 .end = 0,
1655 .flags = IORESOURCE_MEM,
1656 },
1657 {
1658 .name = "dsi_regs",
1659 .start = TEGRA_DSI_BASE,
1660 .end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
1661 .flags = IORESOURCE_MEM,
1662 },
1663};
1664
1665struct nvhost_device tegra_disp1_device = {
1666 .name = "tegradc",
1667 .id = 0,
1668 .resource = tegra_disp1_resources,
1669 .num_resources = ARRAY_SIZE(tegra_disp1_resources),
1670};
1671
1672struct platform_device tegra_nvmap_device = {
1673 .name = "tegra-nvmap",
1674 .id = -1,
1675};
1676
1677void __init tegra_init_debug_uart_rate(void)
1678{
1679 unsigned int uartclk;
1680 struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
1681
1682 BUG_ON(IS_ERR(debug_uart_parent));
1683 uartclk = clk_get_rate(debug_uart_parent);
1684
1685 debug_uarta_platform_data[0].uartclk = uartclk;
1686 debug_uartb_platform_data[0].uartclk = uartclk;
1687 debug_uartc_platform_data[0].uartclk = uartclk;
1688 debug_uartd_platform_data[0].uartclk = uartclk;
1689#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1690 debug_uarte_platform_data[0].uartclk = uartclk;
1691#endif
1692}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 07:02:34 -0400