diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
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committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-tegra/board-cardhu.h | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'arch/arm/mach-tegra/board-cardhu.h')
-rw-r--r-- | arch/arm/mach-tegra/board-cardhu.h | 257 |
1 files changed, 257 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h new file mode 100644 index 00000000000..a0d0ebf3a77 --- /dev/null +++ b/arch/arm/mach-tegra/board-cardhu.h | |||
@@ -0,0 +1,257 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/board-cardhu.h | ||
3 | * | ||
4 | * Copyright (c) 2011, NVIDIA Corporation. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
14 | * more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
19 | */ | ||
20 | |||
21 | #ifndef _MACH_TEGRA_BOARD_CARDHU_H | ||
22 | #define _MACH_TEGRA_BOARD_CARDHU_H | ||
23 | |||
24 | #include <mach/gpio.h> | ||
25 | #include <mach/irqs.h> | ||
26 | #include <linux/mfd/tps6591x.h> | ||
27 | #include <linux/mfd/ricoh583.h> | ||
28 | |||
29 | /* Processor Board ID */ | ||
30 | #define BOARD_E1187 0x0B57 | ||
31 | #define BOARD_E1186 0x0B56 | ||
32 | #define BOARD_E1198 0x0B62 | ||
33 | #define BOARD_E1256 0x0C38 | ||
34 | #define BOARD_E1257 0x0C39 | ||
35 | #define BOARD_E1291 0x0C5B | ||
36 | #define BOARD_PM267 0x0243 | ||
37 | #define BOARD_PM269 0x0245 | ||
38 | #define BOARD_E1208 0x0C08 | ||
39 | #define BOARD_PM305 0x0305 | ||
40 | #define BOARD_PM311 0x030B | ||
41 | #define BOARD_PMU_PM298 0x0262 | ||
42 | #define BOARD_PMU_PM299 0x0263 | ||
43 | |||
44 | /* SKU Information */ | ||
45 | #define BOARD_SKU_B11 0xb11 | ||
46 | |||
47 | #define SKU_DCDC_TPS62361_SUPPORT 0x1 | ||
48 | #define SKU_SLT_ULPI_SUPPORT 0x2 | ||
49 | #define SKU_T30S_SUPPORT 0x4 | ||
50 | #define SKU_TOUCHSCREEN_MECH_FIX 0x0100 | ||
51 | |||
52 | #define SKU_TOUCH_MASK 0xFF00 | ||
53 | #define SKU_TOUCH_2000 0x0B00 | ||
54 | |||
55 | #define SKU_MEMORY_TYPE_BIT 0x3 | ||
56 | #define SKU_MEMORY_TYPE_MASK 0x7 | ||
57 | /* If BOARD_PM269 */ | ||
58 | #define SKU_MEMORY_SAMSUNG_EC 0x0 | ||
59 | #define SKU_MEMORY_ELPIDA 0x2 | ||
60 | #define SKU_MEMORY_SAMSUNG_EB 0x4 | ||
61 | /* If BOARD_PM272 */ | ||
62 | #define SKU_MEMORY_1GB_1R_HYNIX 0x0 | ||
63 | #define SKU_MEMORY_2GB_2R_HYH9 0x2 | ||
64 | /* If other BOARD_ variants */ | ||
65 | #define SKU_MEMORY_CARDHU_1GB_1R 0x0 | ||
66 | #define SKU_MEMORY_CARDHU_2GB_2R 0x2 | ||
67 | #define SKU_MEMORY_CARDHU_2GB_1R_HYK0 0x4 | ||
68 | #define SKU_MEMORY_CARDHU_2GB_1R_HYH9 0x6 | ||
69 | #define SKU_MEMORY_CARDHU_2GB_1R_HYNIX 0x1 | ||
70 | #define MEMORY_TYPE(sku) (((sku) >> SKU_MEMORY_TYPE_BIT) & SKU_MEMORY_TYPE_MASK) | ||
71 | |||
72 | /* Board Fab version */ | ||
73 | #define BOARD_FAB_A00 0x0 | ||
74 | #define BOARD_FAB_A01 0x1 | ||
75 | #define BOARD_FAB_A02 0x2 | ||
76 | #define BOARD_FAB_A03 0x3 | ||
77 | #define BOARD_FAB_A04 0x4 | ||
78 | #define BOARD_FAB_A05 0x5 | ||
79 | |||
80 | /* Display Board ID */ | ||
81 | #define BOARD_DISPLAY_PM313 0x030D | ||
82 | #define BOARD_DISPLAY_E1247 0x0C2F | ||
83 | |||
84 | /* External peripheral act as gpio */ | ||
85 | /* TPS6591x GPIOs */ | ||
86 | #define TPS6591X_GPIO_BASE TEGRA_NR_GPIOS | ||
87 | #define TPS6591X_GPIO_0 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP0) | ||
88 | #define TPS6591X_GPIO_1 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP1) | ||
89 | #define TPS6591X_GPIO_2 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP2) | ||
90 | #define TPS6591X_GPIO_3 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP3) | ||
91 | #define TPS6591X_GPIO_4 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP4) | ||
92 | #define TPS6591X_GPIO_5 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP5) | ||
93 | #define TPS6591X_GPIO_6 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP6) | ||
94 | #define TPS6591X_GPIO_7 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP7) | ||
95 | #define TPS6591X_GPIO_8 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP8) | ||
96 | #define TPS6591X_GPIO_END (TPS6591X_GPIO_BASE + TPS6591X_GPIO_NR) | ||
97 | |||
98 | /* RICOH583 GPIO */ | ||
99 | #define RICOH583_GPIO_BASE TEGRA_NR_GPIOS | ||
100 | #define RICOH583_GPIO_END (RICOH583_GPIO_BASE + 8) | ||
101 | |||
102 | /* MAX77663 GPIO */ | ||
103 | #define MAX77663_GPIO_BASE TEGRA_NR_GPIOS | ||
104 | #define MAX77663_GPIO_END (MAX77663_GPIO_BASE + MAX77663_GPIO_NR) | ||
105 | |||
106 | /* PMU_TCA6416 GPIOs */ | ||
107 | #define PMU_TCA6416_GPIO_BASE (TPS6591X_GPIO_END) | ||
108 | #define PMU_TCA6416_GPIO_PORT00 (PMU_TCA6416_GPIO_BASE + 0) | ||
109 | #define PMU_TCA6416_GPIO_PORT01 (PMU_TCA6416_GPIO_BASE + 1) | ||
110 | #define PMU_TCA6416_GPIO_PORT02 (PMU_TCA6416_GPIO_BASE + 2) | ||
111 | #define PMU_TCA6416_GPIO_PORT03 (PMU_TCA6416_GPIO_BASE + 3) | ||
112 | #define PMU_TCA6416_GPIO_PORT04 (PMU_TCA6416_GPIO_BASE + 4) | ||
113 | #define PMU_TCA6416_GPIO_PORT05 (PMU_TCA6416_GPIO_BASE + 5) | ||
114 | #define PMU_TCA6416_GPIO_PORT06 (PMU_TCA6416_GPIO_BASE + 6) | ||
115 | #define PMU_TCA6416_GPIO_PORT07 (PMU_TCA6416_GPIO_BASE + 7) | ||
116 | #define PMU_TCA6416_GPIO_PORT10 (PMU_TCA6416_GPIO_BASE + 8) | ||
117 | #define PMU_TCA6416_GPIO_PORT11 (PMU_TCA6416_GPIO_BASE + 9) | ||
118 | #define PMU_TCA6416_GPIO_PORT12 (PMU_TCA6416_GPIO_BASE + 10) | ||
119 | #define PMU_TCA6416_GPIO_PORT13 (PMU_TCA6416_GPIO_BASE + 11) | ||
120 | #define PMU_TCA6416_GPIO_PORT14 (PMU_TCA6416_GPIO_BASE + 12) | ||
121 | #define PMU_TCA6416_GPIO_PORT15 (PMU_TCA6416_GPIO_BASE + 13) | ||
122 | #define PMU_TCA6416_GPIO_PORT16 (PMU_TCA6416_GPIO_BASE + 14) | ||
123 | #define PMU_TCA6416_GPIO_PORT17 (PMU_TCA6416_GPIO_BASE + 15) | ||
124 | #define PMU_TCA6416_GPIO_END (PMU_TCA6416_GPIO_BASE + 16) | ||
125 | |||
126 | /* PMU_TCA6416 GPIO assignment */ | ||
127 | #define EN_HSIC_GPIO PMU_TCA6416_GPIO_PORT11 /* PMU_GPIO25 */ | ||
128 | #define PM267_SMSC4640_HSIC_HUB_RESET_GPIO PMU_TCA6416_GPIO_PORT17 /* PMU_GPIO31 */ | ||
129 | |||
130 | /* CAM_TCA6416 GPIOs */ | ||
131 | #define CAM_TCA6416_GPIO_BASE PMU_TCA6416_GPIO_END | ||
132 | #define CAM1_PWR_DN_GPIO CAM_TCA6416_GPIO_BASE + 0 | ||
133 | #define CAM1_RST_L_GPIO CAM_TCA6416_GPIO_BASE + 1 | ||
134 | #define CAM1_AF_PWR_DN_L_GPIO CAM_TCA6416_GPIO_BASE + 2 | ||
135 | #define CAM1_LDO_SHUTDN_L_GPIO CAM_TCA6416_GPIO_BASE + 3 | ||
136 | #define CAM2_PWR_DN_GPIO CAM_TCA6416_GPIO_BASE + 4 | ||
137 | #define CAM2_RST_L_GPIO CAM_TCA6416_GPIO_BASE + 5 | ||
138 | #define CAM2_AF_PWR_DN_L_GPIO CAM_TCA6416_GPIO_BASE + 6 | ||
139 | #define CAM2_LDO_SHUTDN_L_GPIO CAM_TCA6416_GPIO_BASE + 7 | ||
140 | #define CAM_FRONT_PWR_DN_GPIO CAM_TCA6416_GPIO_BASE + 8 | ||
141 | #define CAM_FRONT_RST_L_GPIO CAM_TCA6416_GPIO_BASE + 9 | ||
142 | #define CAM_FRONT_AF_PWR_DN_L_GPIO CAM_TCA6416_GPIO_BASE + 10 | ||
143 | #define CAM_FRONT_LDO_SHUTDN_L_GPIO CAM_TCA6416_GPIO_BASE + 11 | ||
144 | #define CAM_FRONT_LED_EXP CAM_TCA6416_GPIO_BASE + 12 | ||
145 | #define CAM_SNN_LED_REAR_EXP CAM_TCA6416_GPIO_BASE + 13 | ||
146 | /* PIN 19 NOT USED and is reserved */ | ||
147 | #define CAM_NOT_USED CAM_TCA6416_GPIO_BASE + 14 | ||
148 | #define CAM_I2C_MUX_RST_EXP CAM_TCA6416_GPIO_BASE + 15 | ||
149 | #define CAM_TCA6416_GPIO_END CAM_TCA6416_GPIO_BASE + 16 | ||
150 | |||
151 | /* WM8903 GPIOs */ | ||
152 | #define CARDHU_GPIO_WM8903(_x_) (CAM_TCA6416_GPIO_END + (_x_)) | ||
153 | #define CARDHU_GPIO_WM8903_END CARDHU_GPIO_WM8903(4) | ||
154 | |||
155 | /* Audio-related GPIOs */ | ||
156 | #define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW3 | ||
157 | #define TEGRA_GPIO_SPKR_EN CARDHU_GPIO_WM8903(2) | ||
158 | #define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW2 | ||
159 | |||
160 | /* CAMERA RELATED GPIOs on CARDHU */ | ||
161 | #define OV5650_RESETN_GPIO TEGRA_GPIO_PBB0 | ||
162 | #define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 | ||
163 | #define CAM2_POWER_DWN_GPIO TEGRA_GPIO_PBB6 | ||
164 | #define CAM3_POWER_DWN_GPIO TEGRA_GPIO_PBB7 | ||
165 | #define CAMERA_CSI_CAM_SEL_GPIO TEGRA_GPIO_PBB4 | ||
166 | #define CAMERA_CSI_MUX_SEL_GPIO TEGRA_GPIO_PCC1 | ||
167 | #define CAM1_LDO_EN_GPIO TEGRA_GPIO_PR6 | ||
168 | #define CAM2_LDO_EN_GPIO TEGRA_GPIO_PR7 | ||
169 | #define CAM3_LDO_EN_GPIO TEGRA_GPIO_PS0 | ||
170 | #define OV14810_RESETN_GPIO TEGRA_GPIO_PBB0 | ||
171 | |||
172 | #define CAMERA_FLASH_SYNC_GPIO TEGRA_GPIO_PBB3 | ||
173 | #define CAMERA_FLASH_MAX_TORCH_AMP 7 | ||
174 | #define CAMERA_FLASH_MAX_FLASH_AMP 7 | ||
175 | |||
176 | /* PCA954x I2C bus expander bus addresses */ | ||
177 | #define PCA954x_I2C_BUS_BASE 6 | ||
178 | #define PCA954x_I2C_BUS0 (PCA954x_I2C_BUS_BASE + 0) | ||
179 | #define PCA954x_I2C_BUS1 (PCA954x_I2C_BUS_BASE + 1) | ||
180 | #define PCA954x_I2C_BUS2 (PCA954x_I2C_BUS_BASE + 2) | ||
181 | #define PCA954x_I2C_BUS3 (PCA954x_I2C_BUS_BASE + 3) | ||
182 | |||
183 | #define AC_PRESENT_GPIO TPS6591X_GPIO_4 | ||
184 | |||
185 | /*****************Interrupt tables ******************/ | ||
186 | /* External peripheral act as interrupt controller */ | ||
187 | /* TPS6591x IRQs */ | ||
188 | #define TPS6591X_IRQ_BASE TEGRA_NR_IRQS | ||
189 | #define TPS6591X_IRQ_END (TPS6591X_IRQ_BASE + 18) | ||
190 | #define DOCK_DETECT_GPIO TEGRA_GPIO_PU4 | ||
191 | |||
192 | /* RICOH583 IRQs */ | ||
193 | #define RICOH583_IRQ_BASE TEGRA_NR_IRQS | ||
194 | #define RICOH583_IRQ_END (RICOH583_IRQ_BASE + RICOH583_NR_IRQS) | ||
195 | |||
196 | /* MAX77663 IRQs */ | ||
197 | #define MAX77663_IRQ_BASE TEGRA_NR_IRQS | ||
198 | #define MAX77663_IRQ_END (MAX77663_IRQ_BASE + MAX77663_IRQ_NR) | ||
199 | |||
200 | /* HDA AUDIO RESET */ | ||
201 | #define HDA_RESET TEGRA_GPIO_PEE2 | ||
202 | |||
203 | int cardhu_charge_init(void); | ||
204 | int cardhu_regulator_init(void); | ||
205 | int cardhu_suspend_init(void); | ||
206 | int cardhu_sdhci_init(void); | ||
207 | int cardhu_pinmux_init(void); | ||
208 | int cardhu_panel_init(void); | ||
209 | int cardhu_sensors_init(void); | ||
210 | int cardhu_kbc_init(void); | ||
211 | int cardhu_scroll_init(void); | ||
212 | int cardhu_keys_init(void); | ||
213 | int cardhu_pins_state_init(void); | ||
214 | int cardhu_emc_init(void); | ||
215 | int cardhu_edp_init(void); | ||
216 | int cardhu_pmon_init(void); | ||
217 | int cardhu_pm298_gpio_switch_regulator_init(void); | ||
218 | int cardhu_pm298_regulator_init(void); | ||
219 | int cardhu_pm299_gpio_switch_regulator_init(void); | ||
220 | int cardhu_pm299_regulator_init(void); | ||
221 | |||
222 | #define MPU_TYPE_MPU3050 1 | ||
223 | #define MPU_TYPE_MPU6050 2 | ||
224 | #define MPU_GYRO_TYPE MPU_TYPE_MPU3050 | ||
225 | #define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PX1 | ||
226 | #define MPU_GYRO_ADDR 0x68 | ||
227 | #define MPU_GYRO_BUS_NUM 2 | ||
228 | #define MPU_GYRO_ORIENTATION { 0, -1, 0, -1, 0, 0, 0, 0, -1 } | ||
229 | #define MPU_ACCEL_NAME "kxtf9" | ||
230 | #define MPU_ACCEL_IRQ_GPIO TEGRA_GPIO_PL1 | ||
231 | #define MPU_ACCEL_ADDR 0x0F | ||
232 | #define MPU_ACCEL_BUS_NUM 2 | ||
233 | #define MPU_ACCEL_ORIENTATION { 0, -1, 0, -1, 0, 0, 0, 0, -1 } | ||
234 | #define MPU_COMPASS_NAME "ak8975" | ||
235 | #define MPU_COMPASS_IRQ_GPIO 0 | ||
236 | #define MPU_COMPASS_ADDR 0x0C | ||
237 | #define MPU_COMPASS_BUS_NUM 2 | ||
238 | #define MPU_COMPASS_ORIENTATION { 1, 0, 0, 0, 1, 0, 0, 0, 1 } | ||
239 | |||
240 | /* Baseband GPIO addresses */ | ||
241 | #define BB_GPIO_BB_EN TEGRA_GPIO_PR5 | ||
242 | #define BB_GPIO_BB_RST TEGRA_GPIO_PS4 | ||
243 | #define BB_GPIO_SPI_INT TEGRA_GPIO_PS6 | ||
244 | #define BB_GPIO_SPI_SS TEGRA_GPIO_PV0 | ||
245 | #define BB_GPIO_AWR TEGRA_GPIO_PS7 | ||
246 | #define BB_GPIO_CWR TEGRA_GPIO_PU5 | ||
247 | |||
248 | #define XMM_GPIO_BB_ON BB_GPIO_BB_EN | ||
249 | #define XMM_GPIO_BB_RST BB_GPIO_BB_RST | ||
250 | #define XMM_GPIO_IPC_HSIC_ACTIVE BB_GPIO_SPI_INT | ||
251 | #define XMM_GPIO_IPC_HSIC_SUS_REQ BB_GPIO_SPI_SS | ||
252 | #define XMM_GPIO_IPC_BB_WAKE BB_GPIO_AWR | ||
253 | #define XMM_GPIO_IPC_AP_WAKE BB_GPIO_CWR | ||
254 | |||
255 | #define TDIODE_OFFSET (10000) /* in millicelsius */ | ||
256 | |||
257 | #endif | ||