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authordmitry pervushin <dpervushin@embeddedalley.com>2009-06-04 08:48:51 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-04 09:16:43 -0400
commitfc3fdfd632925990f14cffe314f5d90a2b0ae8f6 (patch)
treeaab621e4b865144292089fd02199834fffff1e1c /arch/arm/mach-stmp37xx
parent98f420b23a62e0c9df78c5851860d47bf1bc87dd (diff)
[ARM] 5537/1: Freescale STMP: 37nn registers definition
Add register definitions for Freescale STMP 37nn boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-stmp37xx')
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioin.h61
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioout.h111
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-digctl.h24
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h63
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h89
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lradc.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pwm.h51
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-rtc.h57
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ssp.h101
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h85
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h37
16 files changed, 1180 insertions, 0 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
new file mode 100644
index 00000000000..3b511f947a5
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
@@ -0,0 +1,61 @@
1/*
2 * stmp37xx: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22
23#define HW_AUDIOIN_CTRL 0x0
24#define BM_AUDIOIN_CTRL_RUN 0x00000001
25#define BP_AUDIOIN_CTRL_RUN 0
26#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
30#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOIN_STAT 0x10
34
35#define HW_AUDIOIN_ADCSRR 0x20
36
37#define HW_AUDIOIN_ADCVOLUME 0x30
38#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
39#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
42
43#define HW_AUDIOIN_ADCDEBUG 0x40
44
45#define HW_AUDIOIN_ADCVOL 0x50
46#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
47#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
48#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
49#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
50#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
51#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
52#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
53#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
54#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
55
56#define HW_AUDIOIN_MICLINE 0x60
57
58#define HW_AUDIOIN_ANACLKCTRL 0x70
59#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
60
61#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
new file mode 100644
index 00000000000..ca1942b8a3e
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
@@ -0,0 +1,111 @@
1/*
2 * stmp37xx: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22
23#define HW_AUDIOOUT_CTRL 0x0
24#define BM_AUDIOOUT_CTRL_RUN 0x00000001
25#define BP_AUDIOOUT_CTRL_RUN 0
26#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
30#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOOUT_STAT 0x10
34
35#define HW_AUDIOOUT_DACSRR 0x20
36#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
37#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
38#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
39#define BP_AUDIOOUT_DACSRR_SRC_INT 16
40#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
41#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
42#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
43#define BP_AUDIOOUT_DACSRR_BASEMULT 28
44
45#define HW_AUDIOOUT_DACVOLUME 0x30
46#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
47#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
48#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
49
50#define HW_AUDIOOUT_DACDEBUG 0x40
51
52#define HW_AUDIOOUT_HPVOL 0x50
53#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
54#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
55
56#define HW_AUDIOOUT_PWRDN 0x70
57#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
58#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
59#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
60#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
61#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
62#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
63#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
64
65#define HW_AUDIOOUT_REFCTRL 0x80
66#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
67#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
68#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
69#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
70#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
71#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
72#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
73#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
74#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
75#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
76#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
77#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
78#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
79
80#define HW_AUDIOOUT_ANACTRL 0x90
81#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
82#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
83
84#define HW_AUDIOOUT_TEST 0xA0
85#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
86#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
87
88#define HW_AUDIOOUT_BISTCTRL 0xB0
89
90#define HW_AUDIOOUT_BISTSTAT0 0xC0
91
92#define HW_AUDIOOUT_BISTSTAT1 0xD0
93
94#define HW_AUDIOOUT_ANACLKCTRL 0xE0
95#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
96
97#define HW_AUDIOOUT_DATA 0xF0
98
99#define HW_AUDIOOUT_LINEOUTCTRL 0x100
100#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
101#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
102#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
103#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
104#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
105#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
106#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
107#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
108#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
109#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
110
111#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
new file mode 100644
index 00000000000..ba1bbe265c2
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
@@ -0,0 +1,24 @@
1/*
2 * stmp37xx: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22
23#define HW_DIGCTL_CTRL 0x0
24#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
new file mode 100644
index 00000000000..3b6d990a3af
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
@@ -0,0 +1,37 @@
1/*
2 * stmp37xx: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22
23#define HW_ECC8_CTRL 0x0
24#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
25#define BP_ECC8_CTRL_COMPLETE_IRQ 0
26#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
27#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
28
29#define HW_ECC8_STATUS0 0x10
30#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
31#define BM_ECC8_STATUS0_CORRECTED 0x00000008
32#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
33#define BP_ECC8_STATUS0_STATUS_AUX 8
34#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
35#define BP_ECC8_STATUS0_COMPLETED_CE 16
36
37#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
new file mode 100644
index 00000000000..f2b304f5449
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
@@ -0,0 +1,63 @@
1/*
2 * stmp37xx: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
33#define BP_GPMI_CTRL0_COMMAND_MODE 24
34#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
35#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
36#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
37#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
38#define BM_GPMI_CTRL0_RUN 0x20000000
39#define BM_GPMI_CTRL0_CLKGATE 0x40000000
40#define BM_GPMI_CTRL0_SFTRST 0x80000000
41#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
42#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
43#define BP_GPMI_ECCCTRL_ECC_CMD 13
44
45#define HW_GPMI_CTRL1 0x60
46#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
47#define BP_GPMI_CTRL1_GPMI_MODE 0
48#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
49#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
50#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
51#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
52#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
53#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
54
55#define HW_GPMI_TIMING0 0x70
56#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
57#define BP_GPMI_TIMING0_DATA_SETUP 0
58#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
59#define BP_GPMI_TIMING0_DATA_HOLD 8
60
61#define HW_GPMI_TIMING1 0x80
62#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
63#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
new file mode 100644
index 00000000000..35882a9b8bc
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
@@ -0,0 +1,55 @@
1/*
2 * stmp37xx: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
new file mode 100644
index 00000000000..72514e8b073
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
@@ -0,0 +1,89 @@
1/*
2 * stmp37xx: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
27#define BP_LCDIF_CTRL_COUNT 0
28#define BM_LCDIF_CTRL_RUN 0x00010000
29#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
30#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
31#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
32#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
33#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
34#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
35#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
36#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
37#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
38#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
39#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
40#define BM_LCDIF_CTRL_CLKGATE 0x40000000
41#define BM_LCDIF_CTRL_SFTRST 0x80000000
42
43#define HW_LCDIF_CTRL1 0x10
44#define BM_LCDIF_CTRL1_RESET 0x00000001
45#define BP_LCDIF_CTRL1_RESET 0
46#define BM_LCDIF_CTRL1_MODE86 0x00000002
47#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
48#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
49#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
50#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
51#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
52#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
53#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
54#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
55
56#define HW_LCDIF_TIMING 0x20
57
58#define HW_LCDIF_VDCTRL0 0x30
59#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
60#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
61#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
62#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
63#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
64#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
65#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
66#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
67#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
68#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
69
70#define HW_LCDIF_VDCTRL1 0x40
71#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
72#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
73#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
74#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
75
76#define HW_LCDIF_VDCTRL2 0x50
77#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
78#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
79#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
80#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
81#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
82#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
83
84#define HW_LCDIF_VDCTRL3 0x60
85#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
86#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
87#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
88#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
89#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
new file mode 100644
index 00000000000..cc7b4702d1c
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
@@ -0,0 +1,97 @@
1/*
2 * stmp37xx: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22
23#define HW_LRADC_CTRL0 0x0
24#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
25#define BP_LRADC_CTRL0_SCHEDULE 0
26#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
27#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
28#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
29#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
30#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
31#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
32#define BM_LRADC_CTRL0_CLKGATE 0x40000000
33#define BM_LRADC_CTRL0_SFTRST 0x80000000
34
35#define HW_LRADC_CTRL1 0x10
36#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
37#define BP_LRADC_CTRL1_LRADC0_IRQ 0
38#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
39#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
40#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
41#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
42#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
43#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
44
45#define HW_LRADC_CTRL2 0x20
46#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
47#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
48#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
49#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
50#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
51#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
52
53#define HW_LRADC_CTRL3 0x30
54#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
55#define BP_LRADC_CTRL3_CYCLE_TIME 8
56
57#define HW_LRADC_STATUS 0x40
58#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
59#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
60
61#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
62#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
63#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
64#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
65#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
66#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
67#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
68#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
69
70#define HW_LRADC_CHn 0x50
71#define BM_LRADC_CHn_VALUE 0x0003FFFF
72#define BP_LRADC_CHn_VALUE 0
73#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
74#define BP_LRADC_CHn_NUM_SAMPLES 24
75#define BM_LRADC_CHn_ACCUMULATE 0x20000000
76
77#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
78#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
79#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
80#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
81
82#define HW_LRADC_DELAYn 0xD0
83#define BM_LRADC_DELAYn_DELAY 0x000007FF
84#define BP_LRADC_DELAYn_DELAY 0
85#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
86#define BP_LRADC_DELAYn_LOOP_COUNT 11
87#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
88#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
89#define BM_LRADC_DELAYn_KICK 0x00100000
90#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
91#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
92
93#define HW_LRADC_CTRL4 0x140
94#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
95#define BP_LRADC_CTRL4_LRADC6SELECT 24
96#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
97#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
new file mode 100644
index 00000000000..15966a1b62e
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
@@ -0,0 +1,51 @@
1/*
2 * stmp37xx: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22
23#define HW_PWM_CTRL 0x0
24#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
25#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
26
27#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
28#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
29#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
30#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
31
32#define HW_PWM_ACTIVEn 0x10
33#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
34#define BP_PWM_ACTIVEn_ACTIVE 0
35#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
36#define BP_PWM_ACTIVEn_INACTIVE 16
37
38#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
39#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
40#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
41#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
42
43#define HW_PWM_PERIODn 0x20
44#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
45#define BP_PWM_PERIODn_PERIOD 0
46#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
47#define BP_PWM_PERIODn_ACTIVE_STATE 16
48#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
49#define BP_PWM_PERIODn_INACTIVE_STATE 18
50#define BM_PWM_PERIODn_CDIV 0x00700000
51#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
new file mode 100644
index 00000000000..fac40edc38a
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
@@ -0,0 +1,57 @@
1/*
2 * stmp37xx: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56
57#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
new file mode 100644
index 00000000000..cbde891a06c
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
@@ -0,0 +1,101 @@
1/*
2 * stmp37xx: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_PHYS 0x80034000
24#define REGS_SSP_SIZE 0x2000
25
26#define HW_SSP_CTRL0 0x0
27#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
28#define BP_SSP_CTRL0_XFER_COUNT 0
29#define BM_SSP_CTRL0_ENABLE 0x00010000
30#define BM_SSP_CTRL0_GET_RESP 0x00020000
31#define BM_SSP_CTRL0_LONG_RESP 0x00080000
32#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
33#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
34#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
35#define BP_SSP_CTRL0_BUS_WIDTH 22
36#define BM_SSP_CTRL0_DATA_XFER 0x01000000
37#define BM_SSP_CTRL0_READ 0x02000000
38#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
39#define BM_SSP_CTRL0_LOCK_CS 0x08000000
40#define BM_SSP_CTRL0_RUN 0x20000000
41#define BM_SSP_CTRL0_CLKGATE 0x40000000
42#define BM_SSP_CTRL0_SFTRST 0x80000000
43
44#define HW_SSP_CMD0 0x10
45#define BM_SSP_CMD0_CMD 0x000000FF
46#define BP_SSP_CMD0_CMD 0
47#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
48#define BP_SSP_CMD0_BLOCK_COUNT 8
49#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
50#define BP_SSP_CMD0_BLOCK_SIZE 16
51#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
52#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
53#define BP_SSP_CMD1_CMD_ARG 0
54
55#define HW_SSP_TIMING 0x50
56#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
57#define BP_SSP_TIMING_CLOCK_RATE 0
58#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
59#define BP_SSP_TIMING_CLOCK_DIVIDE 8
60#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
61#define BP_SSP_TIMING_TIMEOUT 16
62
63#define HW_SSP_CTRL1 0x60
64#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
65#define BP_SSP_CTRL1_SSP_MODE 0
66#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
67#define BP_SSP_CTRL1_WORD_LENGTH 4
68#define BM_SSP_CTRL1_POLARITY 0x00000200
69#define BM_SSP_CTRL1_PHASE 0x00000400
70#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
71#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
72#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
74#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
75#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
77#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
79#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
81#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
83#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
84
85#define HW_SSP_DATA 0x70
86
87#define HW_SSP_SDRESP0 0x80
88
89#define HW_SSP_SDRESP1 0x90
90
91#define HW_SSP_SDRESP2 0xA0
92
93#define HW_SSP_SDRESP3 0xB0
94
95#define HW_SSP_STATUS 0xC0
96#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
97#define BM_SSP_STATUS_TIMEOUT 0x00001000
98#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
99#define BM_SSP_STATUS_RESP_ERR 0x00008000
100#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
101#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
new file mode 100644
index 00000000000..0594275d860
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
@@ -0,0 +1,85 @@
1/*
2 * stmp37xx: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP_SIZE 0x2000
24
25#define HW_UARTAPP_CTRL0 0x0
26#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_UARTAPP_CTRL0_XFER_COUNT 0
28#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
29#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
30#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
31#define BM_UARTAPP_CTRL0_RUN 0x20000000
32#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
33#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
34#define BP_UARTAPP_CTRL1_XFER_COUNT 0
35#define BM_UARTAPP_CTRL1_RUN 0x10000000
36
37#define HW_UARTAPP_CTRL2 0x20
38#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
39#define BP_UARTAPP_CTRL2_UARTEN 0
40#define BM_UARTAPP_CTRL2_TXE 0x00000100
41#define BM_UARTAPP_CTRL2_RXE 0x00000200
42#define BM_UARTAPP_CTRL2_RTS 0x00000800
43#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
44#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
45#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
46#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
47#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
48
49#define HW_UARTAPP_LINECTRL 0x30
50#define BM_UARTAPP_LINECTRL_BRK 0x00000001
51#define BP_UARTAPP_LINECTRL_BRK 0
52#define BM_UARTAPP_LINECTRL_PEN 0x00000002
53#define BM_UARTAPP_LINECTRL_EPS 0x00000004
54#define BM_UARTAPP_LINECTRL_STP2 0x00000008
55#define BM_UARTAPP_LINECTRL_FEN 0x00000010
56#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
57#define BP_UARTAPP_LINECTRL_WLEN 5
58#define BM_UARTAPP_LINECTRL_SPS 0x00000080
59#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
60#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
61#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
62#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
63
64#define HW_UARTAPP_INTR 0x50
65#define BM_UARTAPP_INTR_CTSMIS 0x00000002
66#define BM_UARTAPP_INTR_RTIS 0x00000040
67#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
68#define BM_UARTAPP_INTR_RXIEN 0x00100000
69#define BM_UARTAPP_INTR_RTIEN 0x00400000
70
71#define HW_UARTAPP_DATA 0x60
72
73#define HW_UARTAPP_STAT 0x70
74#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
75#define BP_UARTAPP_STAT_RXCOUNT 0
76#define BM_UARTAPP_STAT_FERR 0x00010000
77#define BM_UARTAPP_STAT_PERR 0x00020000
78#define BM_UARTAPP_STAT_BERR 0x00040000
79#define BM_UARTAPP_STAT_OERR 0x00080000
80#define BM_UARTAPP_STAT_RXFE 0x01000000
81#define BM_UARTAPP_STAT_TXFF 0x02000000
82#define BM_UARTAPP_STAT_TXFE 0x08000000
83#define BM_UARTAPP_STAT_CTS 0x10000000
84
85#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
new file mode 100644
index 00000000000..b810deb552a
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
@@ -0,0 +1,268 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
new file mode 100644
index 00000000000..9145e22df32
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
@@ -0,0 +1,22 @@
1/*
2 * stmp37xx: USBCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTL_PHYS 0x80000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
new file mode 100644
index 00000000000..1a2ae9cbdfe
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
@@ -0,0 +1,22 @@
1/*
2 * stmp37xx: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
new file mode 100644
index 00000000000..b7fce0fbc56
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
@@ -0,0 +1,37 @@
1/*
2 * stmp37xx: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22
23#define HW_USBPHY_PWD 0x0
24
25#define HW_USBPHY_CTRL 0x30
26#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
27#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 17:56:38 -0400