[ARM] 5468/1: Freescale STMP platform support [3/10]

Minimal definition of register set for 37xx boards

Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 102 insertions, 0 deletions

diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
new file mode 100644
index 00000000000..3044c20ad90
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
@@ -0,0 +1,102 @@
+/*
+ * STMP APBH Register Definitions
+ *
+ * Copyright (c) 2008 Freescale Semiconductor
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H
+#define _INCLUDE_ASM_ARCH_REGS_APBH_H
+
+#include <mach/stmp3xxx_regs.h>
+
+#ifndef REGS_APBH_BASE
+#define REGS_APBH_BASE (REGS_BASE + 0x00004000)
+#endif
+
+HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)
+#define BP_APBH_CTRL0_SFTRST      31
+#define BM_APBH_CTRL0_SFTRST      0x80000000
+#define BP_APBH_CTRL0_CLKGATE      30
+#define BM_APBH_CTRL0_CLKGATE      0x40000000
+#define BP_APBH_CTRL0_RESET_CHANNEL      16
+#define BM_APBH_CTRL0_RESET_CHANNEL      0x00FF0000
+#define BF_APBH_CTRL0_RESET_CHANNEL(v)   \
+        (((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
+HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
+#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN      9
+#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN      0x00000200
+#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN      8
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN      0x00000100
+#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ      7
+#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ      0x00000080
+#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ      1
+#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ      0x00000002
+#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ      0
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ      0x00000001
+#define BP_APBH_CTRL1_CH1_ERR_IRQ           17
+#define BM_APBH_CTRL1_CH1_ERR_IRQ          0x00020000
+HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
+HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
+HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR      0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR      0xFFFFFFFF
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   ((u32) v)
+HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
+#define BM_APBH_CHn_CMD_XFER_COUNT              0xFFFF0000
+#define BP_APBH_CHn_CMD_XFER_COUNT              16
+#define BF_APBH_CHn_CMD_XFER_COUNT(v)           \
+        (((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
+#define BM_APBH_CHn_CMD_CMDWORDS                0x0000F000
+#define BP_APBH_CHn_CMD_CMDWORDS                12
+#define BF_APBH_CHn_CMD_CMDWORDS(v)             \
+        (((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x00000080
+#define BM_APBH_CHn_CMD_SEMAPHORE               0x00000040
+#define BP_APBH_CHn_CMD_SEMAPHORE               6
+#define BF_APBH_CHn_CMD_SEMAPHORE(v)            \
+        (((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
+#define BM_APBH_CHn_CMD_NANDWAIT4READY   0x00000020
+#define BP_APBH_CHn_CMD_NANDLOCK                4
+#define BM_APBH_CHn_CMD_NANDLOCK                0x00000010
+#define BF_APBH_CHn_CMD_NANDLOCK(v)             \
+        (((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
+#define BM_APBH_CHn_CMD_IRQONCMPLT              0x00000008
+#define BM_APBH_CHn_CMD_CHAIN           0x00000004
+#define BM_APBH_CHn_CMD_DMA_READ                0x00000003
+#define BP_APBH_CHn_CMD_DMA_READ                0
+#define BF_APBH_CHn_CMD_DMA_READ(v)             \
+        (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
+#define BF_APBH_CHn_CMD_COMMAND(v)              \
+        (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER  0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE    0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ     0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE    0x3
+HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)
+HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA      0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA      0x000000FF
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)   \
+        (((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \
+        BM_APBH_CHn_SEMA_INCREMENT_SEMA)
+#define BP_APBH_CHn_SEMA_PHORE      16
+#define BM_APBH_CHn_SEMA_PHORE      0x00FF0000
+HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)
+HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)
+HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)
+
+#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */