diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-05-16 07:20:55 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-07-01 09:15:48 -0400 |
commit | dc8d5f8de12146c8732d926a30e5f064d76061e0 (patch) | |
tree | a44e7117da81c14d86fda0aefca77c8b9a7537d7 /arch/arm/mach-spear3xx | |
parent | 800d683e6b8f0ba630470a56b61ff6742ad129ad (diff) |
dmaengine: PL08x: get rid of unnecessary checks in dma_slave_config
Get rid of the unnecessary checks in dma_slave_config utilizing
the DMA direction. This allows us to move the computation of
cctl to the prepare function.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r-- | arch/arm/mach-spear3xx/spear300.c | 26 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear310.c | 26 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear320.c | 26 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear3xx.c | 3 |
4 files changed, 2 insertions, 79 deletions
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index 0f882ecb7d8..6ec30054996 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c | |||
@@ -120,182 +120,156 @@ struct pl08x_channel_data spear300_dma_info[] = { | |||
120 | .min_signal = 2, | 120 | .min_signal = 2, |
121 | .max_signal = 2, | 121 | .max_signal = 2, |
122 | .muxval = 0, | 122 | .muxval = 0, |
123 | .cctl = 0, | ||
124 | .periph_buses = PL08X_AHB1, | 123 | .periph_buses = PL08X_AHB1, |
125 | }, { | 124 | }, { |
126 | .bus_id = "uart0_tx", | 125 | .bus_id = "uart0_tx", |
127 | .min_signal = 3, | 126 | .min_signal = 3, |
128 | .max_signal = 3, | 127 | .max_signal = 3, |
129 | .muxval = 0, | 128 | .muxval = 0, |
130 | .cctl = 0, | ||
131 | .periph_buses = PL08X_AHB1, | 129 | .periph_buses = PL08X_AHB1, |
132 | }, { | 130 | }, { |
133 | .bus_id = "ssp0_rx", | 131 | .bus_id = "ssp0_rx", |
134 | .min_signal = 8, | 132 | .min_signal = 8, |
135 | .max_signal = 8, | 133 | .max_signal = 8, |
136 | .muxval = 0, | 134 | .muxval = 0, |
137 | .cctl = 0, | ||
138 | .periph_buses = PL08X_AHB1, | 135 | .periph_buses = PL08X_AHB1, |
139 | }, { | 136 | }, { |
140 | .bus_id = "ssp0_tx", | 137 | .bus_id = "ssp0_tx", |
141 | .min_signal = 9, | 138 | .min_signal = 9, |
142 | .max_signal = 9, | 139 | .max_signal = 9, |
143 | .muxval = 0, | 140 | .muxval = 0, |
144 | .cctl = 0, | ||
145 | .periph_buses = PL08X_AHB1, | 141 | .periph_buses = PL08X_AHB1, |
146 | }, { | 142 | }, { |
147 | .bus_id = "i2c_rx", | 143 | .bus_id = "i2c_rx", |
148 | .min_signal = 10, | 144 | .min_signal = 10, |
149 | .max_signal = 10, | 145 | .max_signal = 10, |
150 | .muxval = 0, | 146 | .muxval = 0, |
151 | .cctl = 0, | ||
152 | .periph_buses = PL08X_AHB1, | 147 | .periph_buses = PL08X_AHB1, |
153 | }, { | 148 | }, { |
154 | .bus_id = "i2c_tx", | 149 | .bus_id = "i2c_tx", |
155 | .min_signal = 11, | 150 | .min_signal = 11, |
156 | .max_signal = 11, | 151 | .max_signal = 11, |
157 | .muxval = 0, | 152 | .muxval = 0, |
158 | .cctl = 0, | ||
159 | .periph_buses = PL08X_AHB1, | 153 | .periph_buses = PL08X_AHB1, |
160 | }, { | 154 | }, { |
161 | .bus_id = "irda", | 155 | .bus_id = "irda", |
162 | .min_signal = 12, | 156 | .min_signal = 12, |
163 | .max_signal = 12, | 157 | .max_signal = 12, |
164 | .muxval = 0, | 158 | .muxval = 0, |
165 | .cctl = 0, | ||
166 | .periph_buses = PL08X_AHB1, | 159 | .periph_buses = PL08X_AHB1, |
167 | }, { | 160 | }, { |
168 | .bus_id = "adc", | 161 | .bus_id = "adc", |
169 | .min_signal = 13, | 162 | .min_signal = 13, |
170 | .max_signal = 13, | 163 | .max_signal = 13, |
171 | .muxval = 0, | 164 | .muxval = 0, |
172 | .cctl = 0, | ||
173 | .periph_buses = PL08X_AHB1, | 165 | .periph_buses = PL08X_AHB1, |
174 | }, { | 166 | }, { |
175 | .bus_id = "to_jpeg", | 167 | .bus_id = "to_jpeg", |
176 | .min_signal = 14, | 168 | .min_signal = 14, |
177 | .max_signal = 14, | 169 | .max_signal = 14, |
178 | .muxval = 0, | 170 | .muxval = 0, |
179 | .cctl = 0, | ||
180 | .periph_buses = PL08X_AHB1, | 171 | .periph_buses = PL08X_AHB1, |
181 | }, { | 172 | }, { |
182 | .bus_id = "from_jpeg", | 173 | .bus_id = "from_jpeg", |
183 | .min_signal = 15, | 174 | .min_signal = 15, |
184 | .max_signal = 15, | 175 | .max_signal = 15, |
185 | .muxval = 0, | 176 | .muxval = 0, |
186 | .cctl = 0, | ||
187 | .periph_buses = PL08X_AHB1, | 177 | .periph_buses = PL08X_AHB1, |
188 | }, { | 178 | }, { |
189 | .bus_id = "ras0_rx", | 179 | .bus_id = "ras0_rx", |
190 | .min_signal = 0, | 180 | .min_signal = 0, |
191 | .max_signal = 0, | 181 | .max_signal = 0, |
192 | .muxval = 1, | 182 | .muxval = 1, |
193 | .cctl = 0, | ||
194 | .periph_buses = PL08X_AHB1, | 183 | .periph_buses = PL08X_AHB1, |
195 | }, { | 184 | }, { |
196 | .bus_id = "ras0_tx", | 185 | .bus_id = "ras0_tx", |
197 | .min_signal = 1, | 186 | .min_signal = 1, |
198 | .max_signal = 1, | 187 | .max_signal = 1, |
199 | .muxval = 1, | 188 | .muxval = 1, |
200 | .cctl = 0, | ||
201 | .periph_buses = PL08X_AHB1, | 189 | .periph_buses = PL08X_AHB1, |
202 | }, { | 190 | }, { |
203 | .bus_id = "ras1_rx", | 191 | .bus_id = "ras1_rx", |
204 | .min_signal = 2, | 192 | .min_signal = 2, |
205 | .max_signal = 2, | 193 | .max_signal = 2, |
206 | .muxval = 1, | 194 | .muxval = 1, |
207 | .cctl = 0, | ||
208 | .periph_buses = PL08X_AHB1, | 195 | .periph_buses = PL08X_AHB1, |
209 | }, { | 196 | }, { |
210 | .bus_id = "ras1_tx", | 197 | .bus_id = "ras1_tx", |
211 | .min_signal = 3, | 198 | .min_signal = 3, |
212 | .max_signal = 3, | 199 | .max_signal = 3, |
213 | .muxval = 1, | 200 | .muxval = 1, |
214 | .cctl = 0, | ||
215 | .periph_buses = PL08X_AHB1, | 201 | .periph_buses = PL08X_AHB1, |
216 | }, { | 202 | }, { |
217 | .bus_id = "ras2_rx", | 203 | .bus_id = "ras2_rx", |
218 | .min_signal = 4, | 204 | .min_signal = 4, |
219 | .max_signal = 4, | 205 | .max_signal = 4, |
220 | .muxval = 1, | 206 | .muxval = 1, |
221 | .cctl = 0, | ||
222 | .periph_buses = PL08X_AHB1, | 207 | .periph_buses = PL08X_AHB1, |
223 | }, { | 208 | }, { |
224 | .bus_id = "ras2_tx", | 209 | .bus_id = "ras2_tx", |
225 | .min_signal = 5, | 210 | .min_signal = 5, |
226 | .max_signal = 5, | 211 | .max_signal = 5, |
227 | .muxval = 1, | 212 | .muxval = 1, |
228 | .cctl = 0, | ||
229 | .periph_buses = PL08X_AHB1, | 213 | .periph_buses = PL08X_AHB1, |
230 | }, { | 214 | }, { |
231 | .bus_id = "ras3_rx", | 215 | .bus_id = "ras3_rx", |
232 | .min_signal = 6, | 216 | .min_signal = 6, |
233 | .max_signal = 6, | 217 | .max_signal = 6, |
234 | .muxval = 1, | 218 | .muxval = 1, |
235 | .cctl = 0, | ||
236 | .periph_buses = PL08X_AHB1, | 219 | .periph_buses = PL08X_AHB1, |
237 | }, { | 220 | }, { |
238 | .bus_id = "ras3_tx", | 221 | .bus_id = "ras3_tx", |
239 | .min_signal = 7, | 222 | .min_signal = 7, |
240 | .max_signal = 7, | 223 | .max_signal = 7, |
241 | .muxval = 1, | 224 | .muxval = 1, |
242 | .cctl = 0, | ||
243 | .periph_buses = PL08X_AHB1, | 225 | .periph_buses = PL08X_AHB1, |
244 | }, { | 226 | }, { |
245 | .bus_id = "ras4_rx", | 227 | .bus_id = "ras4_rx", |
246 | .min_signal = 8, | 228 | .min_signal = 8, |
247 | .max_signal = 8, | 229 | .max_signal = 8, |
248 | .muxval = 1, | 230 | .muxval = 1, |
249 | .cctl = 0, | ||
250 | .periph_buses = PL08X_AHB1, | 231 | .periph_buses = PL08X_AHB1, |
251 | }, { | 232 | }, { |
252 | .bus_id = "ras4_tx", | 233 | .bus_id = "ras4_tx", |
253 | .min_signal = 9, | 234 | .min_signal = 9, |
254 | .max_signal = 9, | 235 | .max_signal = 9, |
255 | .muxval = 1, | 236 | .muxval = 1, |
256 | .cctl = 0, | ||
257 | .periph_buses = PL08X_AHB1, | 237 | .periph_buses = PL08X_AHB1, |
258 | }, { | 238 | }, { |
259 | .bus_id = "ras5_rx", | 239 | .bus_id = "ras5_rx", |
260 | .min_signal = 10, | 240 | .min_signal = 10, |
261 | .max_signal = 10, | 241 | .max_signal = 10, |
262 | .muxval = 1, | 242 | .muxval = 1, |
263 | .cctl = 0, | ||
264 | .periph_buses = PL08X_AHB1, | 243 | .periph_buses = PL08X_AHB1, |
265 | }, { | 244 | }, { |
266 | .bus_id = "ras5_tx", | 245 | .bus_id = "ras5_tx", |
267 | .min_signal = 11, | 246 | .min_signal = 11, |
268 | .max_signal = 11, | 247 | .max_signal = 11, |
269 | .muxval = 1, | 248 | .muxval = 1, |
270 | .cctl = 0, | ||
271 | .periph_buses = PL08X_AHB1, | 249 | .periph_buses = PL08X_AHB1, |
272 | }, { | 250 | }, { |
273 | .bus_id = "ras6_rx", | 251 | .bus_id = "ras6_rx", |
274 | .min_signal = 12, | 252 | .min_signal = 12, |
275 | .max_signal = 12, | 253 | .max_signal = 12, |
276 | .muxval = 1, | 254 | .muxval = 1, |
277 | .cctl = 0, | ||
278 | .periph_buses = PL08X_AHB1, | 255 | .periph_buses = PL08X_AHB1, |
279 | }, { | 256 | }, { |
280 | .bus_id = "ras6_tx", | 257 | .bus_id = "ras6_tx", |
281 | .min_signal = 13, | 258 | .min_signal = 13, |
282 | .max_signal = 13, | 259 | .max_signal = 13, |
283 | .muxval = 1, | 260 | .muxval = 1, |
284 | .cctl = 0, | ||
285 | .periph_buses = PL08X_AHB1, | 261 | .periph_buses = PL08X_AHB1, |
286 | }, { | 262 | }, { |
287 | .bus_id = "ras7_rx", | 263 | .bus_id = "ras7_rx", |
288 | .min_signal = 14, | 264 | .min_signal = 14, |
289 | .max_signal = 14, | 265 | .max_signal = 14, |
290 | .muxval = 1, | 266 | .muxval = 1, |
291 | .cctl = 0, | ||
292 | .periph_buses = PL08X_AHB1, | 267 | .periph_buses = PL08X_AHB1, |
293 | }, { | 268 | }, { |
294 | .bus_id = "ras7_tx", | 269 | .bus_id = "ras7_tx", |
295 | .min_signal = 15, | 270 | .min_signal = 15, |
296 | .max_signal = 15, | 271 | .max_signal = 15, |
297 | .muxval = 1, | 272 | .muxval = 1, |
298 | .cctl = 0, | ||
299 | .periph_buses = PL08X_AHB1, | 273 | .periph_buses = PL08X_AHB1, |
300 | }, | 274 | }, |
301 | }; | 275 | }; |
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index bbcf4571d36..1d0e435b904 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c | |||
@@ -205,182 +205,156 @@ struct pl08x_channel_data spear310_dma_info[] = { | |||
205 | .min_signal = 2, | 205 | .min_signal = 2, |
206 | .max_signal = 2, | 206 | .max_signal = 2, |
207 | .muxval = 0, | 207 | .muxval = 0, |
208 | .cctl = 0, | ||
209 | .periph_buses = PL08X_AHB1, | 208 | .periph_buses = PL08X_AHB1, |
210 | }, { | 209 | }, { |
211 | .bus_id = "uart0_tx", | 210 | .bus_id = "uart0_tx", |
212 | .min_signal = 3, | 211 | .min_signal = 3, |
213 | .max_signal = 3, | 212 | .max_signal = 3, |
214 | .muxval = 0, | 213 | .muxval = 0, |
215 | .cctl = 0, | ||
216 | .periph_buses = PL08X_AHB1, | 214 | .periph_buses = PL08X_AHB1, |
217 | }, { | 215 | }, { |
218 | .bus_id = "ssp0_rx", | 216 | .bus_id = "ssp0_rx", |
219 | .min_signal = 8, | 217 | .min_signal = 8, |
220 | .max_signal = 8, | 218 | .max_signal = 8, |
221 | .muxval = 0, | 219 | .muxval = 0, |
222 | .cctl = 0, | ||
223 | .periph_buses = PL08X_AHB1, | 220 | .periph_buses = PL08X_AHB1, |
224 | }, { | 221 | }, { |
225 | .bus_id = "ssp0_tx", | 222 | .bus_id = "ssp0_tx", |
226 | .min_signal = 9, | 223 | .min_signal = 9, |
227 | .max_signal = 9, | 224 | .max_signal = 9, |
228 | .muxval = 0, | 225 | .muxval = 0, |
229 | .cctl = 0, | ||
230 | .periph_buses = PL08X_AHB1, | 226 | .periph_buses = PL08X_AHB1, |
231 | }, { | 227 | }, { |
232 | .bus_id = "i2c_rx", | 228 | .bus_id = "i2c_rx", |
233 | .min_signal = 10, | 229 | .min_signal = 10, |
234 | .max_signal = 10, | 230 | .max_signal = 10, |
235 | .muxval = 0, | 231 | .muxval = 0, |
236 | .cctl = 0, | ||
237 | .periph_buses = PL08X_AHB1, | 232 | .periph_buses = PL08X_AHB1, |
238 | }, { | 233 | }, { |
239 | .bus_id = "i2c_tx", | 234 | .bus_id = "i2c_tx", |
240 | .min_signal = 11, | 235 | .min_signal = 11, |
241 | .max_signal = 11, | 236 | .max_signal = 11, |
242 | .muxval = 0, | 237 | .muxval = 0, |
243 | .cctl = 0, | ||
244 | .periph_buses = PL08X_AHB1, | 238 | .periph_buses = PL08X_AHB1, |
245 | }, { | 239 | }, { |
246 | .bus_id = "irda", | 240 | .bus_id = "irda", |
247 | .min_signal = 12, | 241 | .min_signal = 12, |
248 | .max_signal = 12, | 242 | .max_signal = 12, |
249 | .muxval = 0, | 243 | .muxval = 0, |
250 | .cctl = 0, | ||
251 | .periph_buses = PL08X_AHB1, | 244 | .periph_buses = PL08X_AHB1, |
252 | }, { | 245 | }, { |
253 | .bus_id = "adc", | 246 | .bus_id = "adc", |
254 | .min_signal = 13, | 247 | .min_signal = 13, |
255 | .max_signal = 13, | 248 | .max_signal = 13, |
256 | .muxval = 0, | 249 | .muxval = 0, |
257 | .cctl = 0, | ||
258 | .periph_buses = PL08X_AHB1, | 250 | .periph_buses = PL08X_AHB1, |
259 | }, { | 251 | }, { |
260 | .bus_id = "to_jpeg", | 252 | .bus_id = "to_jpeg", |
261 | .min_signal = 14, | 253 | .min_signal = 14, |
262 | .max_signal = 14, | 254 | .max_signal = 14, |
263 | .muxval = 0, | 255 | .muxval = 0, |
264 | .cctl = 0, | ||
265 | .periph_buses = PL08X_AHB1, | 256 | .periph_buses = PL08X_AHB1, |
266 | }, { | 257 | }, { |
267 | .bus_id = "from_jpeg", | 258 | .bus_id = "from_jpeg", |
268 | .min_signal = 15, | 259 | .min_signal = 15, |
269 | .max_signal = 15, | 260 | .max_signal = 15, |
270 | .muxval = 0, | 261 | .muxval = 0, |
271 | .cctl = 0, | ||
272 | .periph_buses = PL08X_AHB1, | 262 | .periph_buses = PL08X_AHB1, |
273 | }, { | 263 | }, { |
274 | .bus_id = "uart1_rx", | 264 | .bus_id = "uart1_rx", |
275 | .min_signal = 0, | 265 | .min_signal = 0, |
276 | .max_signal = 0, | 266 | .max_signal = 0, |
277 | .muxval = 1, | 267 | .muxval = 1, |
278 | .cctl = 0, | ||
279 | .periph_buses = PL08X_AHB1, | 268 | .periph_buses = PL08X_AHB1, |
280 | }, { | 269 | }, { |
281 | .bus_id = "uart1_tx", | 270 | .bus_id = "uart1_tx", |
282 | .min_signal = 1, | 271 | .min_signal = 1, |
283 | .max_signal = 1, | 272 | .max_signal = 1, |
284 | .muxval = 1, | 273 | .muxval = 1, |
285 | .cctl = 0, | ||
286 | .periph_buses = PL08X_AHB1, | 274 | .periph_buses = PL08X_AHB1, |
287 | }, { | 275 | }, { |
288 | .bus_id = "uart2_rx", | 276 | .bus_id = "uart2_rx", |
289 | .min_signal = 2, | 277 | .min_signal = 2, |
290 | .max_signal = 2, | 278 | .max_signal = 2, |
291 | .muxval = 1, | 279 | .muxval = 1, |
292 | .cctl = 0, | ||
293 | .periph_buses = PL08X_AHB1, | 280 | .periph_buses = PL08X_AHB1, |
294 | }, { | 281 | }, { |
295 | .bus_id = "uart2_tx", | 282 | .bus_id = "uart2_tx", |
296 | .min_signal = 3, | 283 | .min_signal = 3, |
297 | .max_signal = 3, | 284 | .max_signal = 3, |
298 | .muxval = 1, | 285 | .muxval = 1, |
299 | .cctl = 0, | ||
300 | .periph_buses = PL08X_AHB1, | 286 | .periph_buses = PL08X_AHB1, |
301 | }, { | 287 | }, { |
302 | .bus_id = "uart3_rx", | 288 | .bus_id = "uart3_rx", |
303 | .min_signal = 4, | 289 | .min_signal = 4, |
304 | .max_signal = 4, | 290 | .max_signal = 4, |
305 | .muxval = 1, | 291 | .muxval = 1, |
306 | .cctl = 0, | ||
307 | .periph_buses = PL08X_AHB1, | 292 | .periph_buses = PL08X_AHB1, |
308 | }, { | 293 | }, { |
309 | .bus_id = "uart3_tx", | 294 | .bus_id = "uart3_tx", |
310 | .min_signal = 5, | 295 | .min_signal = 5, |
311 | .max_signal = 5, | 296 | .max_signal = 5, |
312 | .muxval = 1, | 297 | .muxval = 1, |
313 | .cctl = 0, | ||
314 | .periph_buses = PL08X_AHB1, | 298 | .periph_buses = PL08X_AHB1, |
315 | }, { | 299 | }, { |
316 | .bus_id = "uart4_rx", | 300 | .bus_id = "uart4_rx", |
317 | .min_signal = 6, | 301 | .min_signal = 6, |
318 | .max_signal = 6, | 302 | .max_signal = 6, |
319 | .muxval = 1, | 303 | .muxval = 1, |
320 | .cctl = 0, | ||
321 | .periph_buses = PL08X_AHB1, | 304 | .periph_buses = PL08X_AHB1, |
322 | }, { | 305 | }, { |
323 | .bus_id = "uart4_tx", | 306 | .bus_id = "uart4_tx", |
324 | .min_signal = 7, | 307 | .min_signal = 7, |
325 | .max_signal = 7, | 308 | .max_signal = 7, |
326 | .muxval = 1, | 309 | .muxval = 1, |
327 | .cctl = 0, | ||
328 | .periph_buses = PL08X_AHB1, | 310 | .periph_buses = PL08X_AHB1, |
329 | }, { | 311 | }, { |
330 | .bus_id = "uart5_rx", | 312 | .bus_id = "uart5_rx", |
331 | .min_signal = 8, | 313 | .min_signal = 8, |
332 | .max_signal = 8, | 314 | .max_signal = 8, |
333 | .muxval = 1, | 315 | .muxval = 1, |
334 | .cctl = 0, | ||
335 | .periph_buses = PL08X_AHB1, | 316 | .periph_buses = PL08X_AHB1, |
336 | }, { | 317 | }, { |
337 | .bus_id = "uart5_tx", | 318 | .bus_id = "uart5_tx", |
338 | .min_signal = 9, | 319 | .min_signal = 9, |
339 | .max_signal = 9, | 320 | .max_signal = 9, |
340 | .muxval = 1, | 321 | .muxval = 1, |
341 | .cctl = 0, | ||
342 | .periph_buses = PL08X_AHB1, | 322 | .periph_buses = PL08X_AHB1, |
343 | }, { | 323 | }, { |
344 | .bus_id = "ras5_rx", | 324 | .bus_id = "ras5_rx", |
345 | .min_signal = 10, | 325 | .min_signal = 10, |
346 | .max_signal = 10, | 326 | .max_signal = 10, |
347 | .muxval = 1, | 327 | .muxval = 1, |
348 | .cctl = 0, | ||
349 | .periph_buses = PL08X_AHB1, | 328 | .periph_buses = PL08X_AHB1, |
350 | }, { | 329 | }, { |
351 | .bus_id = "ras5_tx", | 330 | .bus_id = "ras5_tx", |
352 | .min_signal = 11, | 331 | .min_signal = 11, |
353 | .max_signal = 11, | 332 | .max_signal = 11, |
354 | .muxval = 1, | 333 | .muxval = 1, |
355 | .cctl = 0, | ||
356 | .periph_buses = PL08X_AHB1, | 334 | .periph_buses = PL08X_AHB1, |
357 | }, { | 335 | }, { |
358 | .bus_id = "ras6_rx", | 336 | .bus_id = "ras6_rx", |
359 | .min_signal = 12, | 337 | .min_signal = 12, |
360 | .max_signal = 12, | 338 | .max_signal = 12, |
361 | .muxval = 1, | 339 | .muxval = 1, |
362 | .cctl = 0, | ||
363 | .periph_buses = PL08X_AHB1, | 340 | .periph_buses = PL08X_AHB1, |
364 | }, { | 341 | }, { |
365 | .bus_id = "ras6_tx", | 342 | .bus_id = "ras6_tx", |
366 | .min_signal = 13, | 343 | .min_signal = 13, |
367 | .max_signal = 13, | 344 | .max_signal = 13, |
368 | .muxval = 1, | 345 | .muxval = 1, |
369 | .cctl = 0, | ||
370 | .periph_buses = PL08X_AHB1, | 346 | .periph_buses = PL08X_AHB1, |
371 | }, { | 347 | }, { |
372 | .bus_id = "ras7_rx", | 348 | .bus_id = "ras7_rx", |
373 | .min_signal = 14, | 349 | .min_signal = 14, |
374 | .max_signal = 14, | 350 | .max_signal = 14, |
375 | .muxval = 1, | 351 | .muxval = 1, |
376 | .cctl = 0, | ||
377 | .periph_buses = PL08X_AHB1, | 352 | .periph_buses = PL08X_AHB1, |
378 | }, { | 353 | }, { |
379 | .bus_id = "ras7_tx", | 354 | .bus_id = "ras7_tx", |
380 | .min_signal = 15, | 355 | .min_signal = 15, |
381 | .max_signal = 15, | 356 | .max_signal = 15, |
382 | .muxval = 1, | 357 | .muxval = 1, |
383 | .cctl = 0, | ||
384 | .periph_buses = PL08X_AHB1, | 358 | .periph_buses = PL08X_AHB1, |
385 | }, | 359 | }, |
386 | }; | 360 | }; |
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index 88d483bcd66..fd823c62457 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c | |||
@@ -213,182 +213,156 @@ struct pl08x_channel_data spear320_dma_info[] = { | |||
213 | .min_signal = 2, | 213 | .min_signal = 2, |
214 | .max_signal = 2, | 214 | .max_signal = 2, |
215 | .muxval = 0, | 215 | .muxval = 0, |
216 | .cctl = 0, | ||
217 | .periph_buses = PL08X_AHB1, | 216 | .periph_buses = PL08X_AHB1, |
218 | }, { | 217 | }, { |
219 | .bus_id = "uart0_tx", | 218 | .bus_id = "uart0_tx", |
220 | .min_signal = 3, | 219 | .min_signal = 3, |
221 | .max_signal = 3, | 220 | .max_signal = 3, |
222 | .muxval = 0, | 221 | .muxval = 0, |
223 | .cctl = 0, | ||
224 | .periph_buses = PL08X_AHB1, | 222 | .periph_buses = PL08X_AHB1, |
225 | }, { | 223 | }, { |
226 | .bus_id = "ssp0_rx", | 224 | .bus_id = "ssp0_rx", |
227 | .min_signal = 8, | 225 | .min_signal = 8, |
228 | .max_signal = 8, | 226 | .max_signal = 8, |
229 | .muxval = 0, | 227 | .muxval = 0, |
230 | .cctl = 0, | ||
231 | .periph_buses = PL08X_AHB1, | 228 | .periph_buses = PL08X_AHB1, |
232 | }, { | 229 | }, { |
233 | .bus_id = "ssp0_tx", | 230 | .bus_id = "ssp0_tx", |
234 | .min_signal = 9, | 231 | .min_signal = 9, |
235 | .max_signal = 9, | 232 | .max_signal = 9, |
236 | .muxval = 0, | 233 | .muxval = 0, |
237 | .cctl = 0, | ||
238 | .periph_buses = PL08X_AHB1, | 234 | .periph_buses = PL08X_AHB1, |
239 | }, { | 235 | }, { |
240 | .bus_id = "i2c0_rx", | 236 | .bus_id = "i2c0_rx", |
241 | .min_signal = 10, | 237 | .min_signal = 10, |
242 | .max_signal = 10, | 238 | .max_signal = 10, |
243 | .muxval = 0, | 239 | .muxval = 0, |
244 | .cctl = 0, | ||
245 | .periph_buses = PL08X_AHB1, | 240 | .periph_buses = PL08X_AHB1, |
246 | }, { | 241 | }, { |
247 | .bus_id = "i2c0_tx", | 242 | .bus_id = "i2c0_tx", |
248 | .min_signal = 11, | 243 | .min_signal = 11, |
249 | .max_signal = 11, | 244 | .max_signal = 11, |
250 | .muxval = 0, | 245 | .muxval = 0, |
251 | .cctl = 0, | ||
252 | .periph_buses = PL08X_AHB1, | 246 | .periph_buses = PL08X_AHB1, |
253 | }, { | 247 | }, { |
254 | .bus_id = "irda", | 248 | .bus_id = "irda", |
255 | .min_signal = 12, | 249 | .min_signal = 12, |
256 | .max_signal = 12, | 250 | .max_signal = 12, |
257 | .muxval = 0, | 251 | .muxval = 0, |
258 | .cctl = 0, | ||
259 | .periph_buses = PL08X_AHB1, | 252 | .periph_buses = PL08X_AHB1, |
260 | }, { | 253 | }, { |
261 | .bus_id = "adc", | 254 | .bus_id = "adc", |
262 | .min_signal = 13, | 255 | .min_signal = 13, |
263 | .max_signal = 13, | 256 | .max_signal = 13, |
264 | .muxval = 0, | 257 | .muxval = 0, |
265 | .cctl = 0, | ||
266 | .periph_buses = PL08X_AHB1, | 258 | .periph_buses = PL08X_AHB1, |
267 | }, { | 259 | }, { |
268 | .bus_id = "to_jpeg", | 260 | .bus_id = "to_jpeg", |
269 | .min_signal = 14, | 261 | .min_signal = 14, |
270 | .max_signal = 14, | 262 | .max_signal = 14, |
271 | .muxval = 0, | 263 | .muxval = 0, |
272 | .cctl = 0, | ||
273 | .periph_buses = PL08X_AHB1, | 264 | .periph_buses = PL08X_AHB1, |
274 | }, { | 265 | }, { |
275 | .bus_id = "from_jpeg", | 266 | .bus_id = "from_jpeg", |
276 | .min_signal = 15, | 267 | .min_signal = 15, |
277 | .max_signal = 15, | 268 | .max_signal = 15, |
278 | .muxval = 0, | 269 | .muxval = 0, |
279 | .cctl = 0, | ||
280 | .periph_buses = PL08X_AHB1, | 270 | .periph_buses = PL08X_AHB1, |
281 | }, { | 271 | }, { |
282 | .bus_id = "ssp1_rx", | 272 | .bus_id = "ssp1_rx", |
283 | .min_signal = 0, | 273 | .min_signal = 0, |
284 | .max_signal = 0, | 274 | .max_signal = 0, |
285 | .muxval = 1, | 275 | .muxval = 1, |
286 | .cctl = 0, | ||
287 | .periph_buses = PL08X_AHB2, | 276 | .periph_buses = PL08X_AHB2, |
288 | }, { | 277 | }, { |
289 | .bus_id = "ssp1_tx", | 278 | .bus_id = "ssp1_tx", |
290 | .min_signal = 1, | 279 | .min_signal = 1, |
291 | .max_signal = 1, | 280 | .max_signal = 1, |
292 | .muxval = 1, | 281 | .muxval = 1, |
293 | .cctl = 0, | ||
294 | .periph_buses = PL08X_AHB2, | 282 | .periph_buses = PL08X_AHB2, |
295 | }, { | 283 | }, { |
296 | .bus_id = "ssp2_rx", | 284 | .bus_id = "ssp2_rx", |
297 | .min_signal = 2, | 285 | .min_signal = 2, |
298 | .max_signal = 2, | 286 | .max_signal = 2, |
299 | .muxval = 1, | 287 | .muxval = 1, |
300 | .cctl = 0, | ||
301 | .periph_buses = PL08X_AHB2, | 288 | .periph_buses = PL08X_AHB2, |
302 | }, { | 289 | }, { |
303 | .bus_id = "ssp2_tx", | 290 | .bus_id = "ssp2_tx", |
304 | .min_signal = 3, | 291 | .min_signal = 3, |
305 | .max_signal = 3, | 292 | .max_signal = 3, |
306 | .muxval = 1, | 293 | .muxval = 1, |
307 | .cctl = 0, | ||
308 | .periph_buses = PL08X_AHB2, | 294 | .periph_buses = PL08X_AHB2, |
309 | }, { | 295 | }, { |
310 | .bus_id = "uart1_rx", | 296 | .bus_id = "uart1_rx", |
311 | .min_signal = 4, | 297 | .min_signal = 4, |
312 | .max_signal = 4, | 298 | .max_signal = 4, |
313 | .muxval = 1, | 299 | .muxval = 1, |
314 | .cctl = 0, | ||
315 | .periph_buses = PL08X_AHB2, | 300 | .periph_buses = PL08X_AHB2, |
316 | }, { | 301 | }, { |
317 | .bus_id = "uart1_tx", | 302 | .bus_id = "uart1_tx", |
318 | .min_signal = 5, | 303 | .min_signal = 5, |
319 | .max_signal = 5, | 304 | .max_signal = 5, |
320 | .muxval = 1, | 305 | .muxval = 1, |
321 | .cctl = 0, | ||
322 | .periph_buses = PL08X_AHB2, | 306 | .periph_buses = PL08X_AHB2, |
323 | }, { | 307 | }, { |
324 | .bus_id = "uart2_rx", | 308 | .bus_id = "uart2_rx", |
325 | .min_signal = 6, | 309 | .min_signal = 6, |
326 | .max_signal = 6, | 310 | .max_signal = 6, |
327 | .muxval = 1, | 311 | .muxval = 1, |
328 | .cctl = 0, | ||
329 | .periph_buses = PL08X_AHB2, | 312 | .periph_buses = PL08X_AHB2, |
330 | }, { | 313 | }, { |
331 | .bus_id = "uart2_tx", | 314 | .bus_id = "uart2_tx", |
332 | .min_signal = 7, | 315 | .min_signal = 7, |
333 | .max_signal = 7, | 316 | .max_signal = 7, |
334 | .muxval = 1, | 317 | .muxval = 1, |
335 | .cctl = 0, | ||
336 | .periph_buses = PL08X_AHB2, | 318 | .periph_buses = PL08X_AHB2, |
337 | }, { | 319 | }, { |
338 | .bus_id = "i2c1_rx", | 320 | .bus_id = "i2c1_rx", |
339 | .min_signal = 8, | 321 | .min_signal = 8, |
340 | .max_signal = 8, | 322 | .max_signal = 8, |
341 | .muxval = 1, | 323 | .muxval = 1, |
342 | .cctl = 0, | ||
343 | .periph_buses = PL08X_AHB2, | 324 | .periph_buses = PL08X_AHB2, |
344 | }, { | 325 | }, { |
345 | .bus_id = "i2c1_tx", | 326 | .bus_id = "i2c1_tx", |
346 | .min_signal = 9, | 327 | .min_signal = 9, |
347 | .max_signal = 9, | 328 | .max_signal = 9, |
348 | .muxval = 1, | 329 | .muxval = 1, |
349 | .cctl = 0, | ||
350 | .periph_buses = PL08X_AHB2, | 330 | .periph_buses = PL08X_AHB2, |
351 | }, { | 331 | }, { |
352 | .bus_id = "i2c2_rx", | 332 | .bus_id = "i2c2_rx", |
353 | .min_signal = 10, | 333 | .min_signal = 10, |
354 | .max_signal = 10, | 334 | .max_signal = 10, |
355 | .muxval = 1, | 335 | .muxval = 1, |
356 | .cctl = 0, | ||
357 | .periph_buses = PL08X_AHB2, | 336 | .periph_buses = PL08X_AHB2, |
358 | }, { | 337 | }, { |
359 | .bus_id = "i2c2_tx", | 338 | .bus_id = "i2c2_tx", |
360 | .min_signal = 11, | 339 | .min_signal = 11, |
361 | .max_signal = 11, | 340 | .max_signal = 11, |
362 | .muxval = 1, | 341 | .muxval = 1, |
363 | .cctl = 0, | ||
364 | .periph_buses = PL08X_AHB2, | 342 | .periph_buses = PL08X_AHB2, |
365 | }, { | 343 | }, { |
366 | .bus_id = "i2s_rx", | 344 | .bus_id = "i2s_rx", |
367 | .min_signal = 12, | 345 | .min_signal = 12, |
368 | .max_signal = 12, | 346 | .max_signal = 12, |
369 | .muxval = 1, | 347 | .muxval = 1, |
370 | .cctl = 0, | ||
371 | .periph_buses = PL08X_AHB2, | 348 | .periph_buses = PL08X_AHB2, |
372 | }, { | 349 | }, { |
373 | .bus_id = "i2s_tx", | 350 | .bus_id = "i2s_tx", |
374 | .min_signal = 13, | 351 | .min_signal = 13, |
375 | .max_signal = 13, | 352 | .max_signal = 13, |
376 | .muxval = 1, | 353 | .muxval = 1, |
377 | .cctl = 0, | ||
378 | .periph_buses = PL08X_AHB2, | 354 | .periph_buses = PL08X_AHB2, |
379 | }, { | 355 | }, { |
380 | .bus_id = "rs485_rx", | 356 | .bus_id = "rs485_rx", |
381 | .min_signal = 14, | 357 | .min_signal = 14, |
382 | .max_signal = 14, | 358 | .max_signal = 14, |
383 | .muxval = 1, | 359 | .muxval = 1, |
384 | .cctl = 0, | ||
385 | .periph_buses = PL08X_AHB2, | 360 | .periph_buses = PL08X_AHB2, |
386 | }, { | 361 | }, { |
387 | .bus_id = "rs485_tx", | 362 | .bus_id = "rs485_tx", |
388 | .min_signal = 15, | 363 | .min_signal = 15, |
389 | .max_signal = 15, | 364 | .max_signal = 15, |
390 | .muxval = 1, | 365 | .muxval = 1, |
391 | .cctl = 0, | ||
392 | .periph_buses = PL08X_AHB2, | 366 | .periph_buses = PL08X_AHB2, |
393 | }, | 367 | }, |
394 | }; | 368 | }; |
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 0f41bd1c47c..d6cd8403fe6 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c | |||
@@ -46,7 +46,8 @@ struct pl022_ssp_controller pl022_plat_data = { | |||
46 | struct pl08x_platform_data pl080_plat_data = { | 46 | struct pl08x_platform_data pl080_plat_data = { |
47 | .memcpy_channel = { | 47 | .memcpy_channel = { |
48 | .bus_id = "memcpy", | 48 | .bus_id = "memcpy", |
49 | .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ | 49 | .cctl_memcpy = |
50 | (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \ | ||
50 | PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ | 51 | PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \ |
51 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ | 52 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \ |
52 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ | 53 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \ |