Added missing tegra files.HEADmaster

13 files changed, 1304 insertions, 0 deletions

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
new file mode 100644
index 00000000000..f67860cd649
--- /dev/null
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -0,0 +1,759 @@
+/*
+ * arch/arm/mach-spear3xx/clock.c
+ *
+ * SPEAr3xx machines clock framework source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/mach-types.h>
+#include <plat/clock.h>
+#include <mach/misc_regs.h>
+
+/* root clks */
+/* 32 KHz oscillator clock */
+static struct clk osc_32k_clk = {
+        .flags = ALWAYS_ENABLED,
+        .rate = 32000,
+};
+
+/* 24 MHz oscillator clock */
+static struct clk osc_24m_clk = {
+        .flags = ALWAYS_ENABLED,
+        .rate = 24000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+        .pclk = &osc_32k_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = RTC_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* clock derived from 24 MHz osc clk */
+/* pll masks structure */
+static struct pll_clk_masks pll1_masks = {
+        .mode_mask = PLL_MODE_MASK,
+        .mode_shift = PLL_MODE_SHIFT,
+        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+        .div_p_mask = PLL_DIV_P_MASK,
+        .div_p_shift = PLL_DIV_P_SHIFT,
+        .div_n_mask = PLL_DIV_N_MASK,
+        .div_n_shift = PLL_DIV_N_SHIFT,
+};
+
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+        .mode_reg = PLL1_CTR,
+        .cfg_reg = PLL1_FRQ,
+        .masks = &pll1_masks,
+};
+
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
+};
+
+/* PLL1 clock */
+static struct clk pll1_clk = {
+        .flags = ENABLED_ON_INIT,
+        .pclk = &osc_24m_clk,
+        .en_reg = PLL1_CTR,
+        .en_reg_bit = PLL_ENABLE,
+        .calc_rate = &pll_calc_rate,
+        .recalc = &pll_clk_recalc,
+        .set_rate = &pll_clk_set_rate,
+        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
+        .private_data = &pll1_config,
+};
+
+/* PLL3 48 MHz clock */
+static struct clk pll3_48m_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &osc_24m_clk,
+        .rate = 48000000,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &osc_24m_clk,
+        .recalc = &follow_parent,
+};
+
+/* clock derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .recalc = &follow_parent,
+};
+
+/* ahb masks structure */
+static struct bus_clk_masks ahb_masks = {
+        .mask = PLL_HCLK_RATIO_MASK,
+        .shift = PLL_HCLK_RATIO_SHIFT,
+};
+
+/* ahb configuration structure */
+static struct bus_clk_config ahb_config = {
+        .reg = CORE_CLK_CFG,
+        .masks = &ahb_masks,
+};
+
+/* ahb rate configuration table, in ascending order of rates */
+struct bus_rate_tbl bus_rtbl[] = {
+        {.div = 3}, /* == parent divided by 4 */
+        {.div = 2}, /* == parent divided by 3 */
+        {.div = 1}, /* == parent divided by 2 */
+        {.div = 0}, /* == parent divided by 1 */
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &bus_calc_rate,
+        .recalc = &bus_clk_recalc,
+        .set_rate = &bus_clk_set_rate,
+        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
+        .private_data = &ahb_config,
+};
+
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = AUX_XSCALE_MASK,
+        .xscale_sel_shift = AUX_XSCALE_SHIFT,
+        .yscale_sel_mask = AUX_YSCALE_MASK,
+        .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
+/* uart synth configurations */
+static struct aux_clk_config uart_synth_config = {
+        .synth_reg = UART_CLK_SYNT,
+        .masks = &aux_masks,
+};
+
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+        /* For PLL1 = 332 MHz */
+        {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
+        {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+        .en_reg = UART_CLK_SYNT,
+        .en_reg_bit = AUX_SYNT_ENB,
+        .pclk = &pll1_clk,
+        .calc_rate = &aux_calc_rate,
+        .recalc = &aux_clk_recalc,
+        .set_rate = &aux_clk_set_rate,
+        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+        .private_data = &uart_synth_config,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+        {
+                .pclk = &uart_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+        .pclk_info = uart_pclk_info,
+        .pclk_count = ARRAY_SIZE(uart_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart clock */
+static struct clk uart_clk = {
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = UART_CLK_ENB,
+        .pclk_sel = &uart_pclk_sel,
+        .pclk_sel_shift = UART_CLK_SHIFT,
+        .recalc = &follow_parent,
+};
+
+/* firda configurations */
+static struct aux_clk_config firda_synth_config = {
+        .synth_reg = FIRDA_CLK_SYNT,
+        .masks = &aux_masks,
+};
+
+/* firda synth clock */
+static struct clk firda_synth_clk = {
+        .en_reg = FIRDA_CLK_SYNT,
+        .en_reg_bit = AUX_SYNT_ENB,
+        .pclk = &pll1_clk,
+        .calc_rate = &aux_calc_rate,
+        .recalc = &aux_clk_recalc,
+        .set_rate = &aux_clk_set_rate,
+        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+        .private_data = &firda_synth_config,
+};
+
+/* firda parents */
+static struct pclk_info firda_pclk_info[] = {
+        {
+                .pclk = &firda_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* firda parent select structure */
+static struct pclk_sel firda_pclk_sel = {
+        .pclk_info = firda_pclk_info,
+        .pclk_count = ARRAY_SIZE(firda_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = FIRDA_CLK_MASK,
+};
+
+/* firda clock */
+static struct clk firda_clk = {
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = FIRDA_CLK_ENB,
+        .pclk_sel = &firda_pclk_sel,
+        .pclk_sel_shift = FIRDA_CLK_SHIFT,
+        .recalc = &follow_parent,
+};
+
+/* gpt synthesizer masks */
+static struct gpt_clk_masks gpt_masks = {
+        .mscale_sel_mask = GPT_MSCALE_MASK,
+        .mscale_sel_shift = GPT_MSCALE_SHIFT,
+        .nscale_sel_mask = GPT_NSCALE_MASK,
+        .nscale_sel_shift = GPT_NSCALE_SHIFT,
+};
+
+/* gpt rate configuration table, in ascending order of rates */
+struct gpt_rate_tbl gpt_rtbl[] = {
+        /* For pll1 = 332 MHz */
+        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+        {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+/* gpt0 synth clk config*/
+static struct gpt_clk_config gpt0_synth_config = {
+        .synth_reg = PRSC1_CLK_CFG,
+        .masks = &gpt_masks,
+};
+
+/* gpt synth clock */
+static struct clk gpt0_synth_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &gpt_calc_rate,
+        .recalc = &gpt_clk_recalc,
+        .set_rate = &gpt_clk_set_rate,
+        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+        .private_data = &gpt0_synth_config,
+};
+
+/* gpt parents */
+static struct pclk_info gpt0_pclk_info[] = {
+        {
+                .pclk = &gpt0_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt0_pclk_sel = {
+        .pclk_info = gpt0_pclk_info,
+        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk_sel = &gpt0_pclk_sel,
+        .pclk_sel_shift = GPT0_CLK_SHIFT,
+        .recalc = &follow_parent,
+};
+
+/* gpt1 synth clk configurations */
+static struct gpt_clk_config gpt1_synth_config = {
+        .synth_reg = PRSC2_CLK_CFG,
+        .masks = &gpt_masks,
+};
+
+/* gpt1 synth clock */
+static struct clk gpt1_synth_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &gpt_calc_rate,
+        .recalc = &gpt_clk_recalc,
+        .set_rate = &gpt_clk_set_rate,
+        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+        .private_data = &gpt1_synth_config,
+};
+
+static struct pclk_info gpt1_pclk_info[] = {
+        {
+                .pclk = &gpt1_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt1_pclk_sel = {
+        .pclk_info = gpt1_pclk_info,
+        .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = GPT1_CLK_ENB,
+        .pclk_sel = &gpt1_pclk_sel,
+        .pclk_sel_shift = GPT1_CLK_SHIFT,
+        .recalc = &follow_parent,
+};
+
+/* gpt2 synth clk configurations */
+static struct gpt_clk_config gpt2_synth_config = {
+        .synth_reg = PRSC3_CLK_CFG,
+        .masks = &gpt_masks,
+};
+
+/* gpt1 synth clock */
+static struct clk gpt2_synth_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &gpt_calc_rate,
+        .recalc = &gpt_clk_recalc,
+        .set_rate = &gpt_clk_set_rate,
+        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+        .private_data = &gpt2_synth_config,
+};
+
+static struct pclk_info gpt2_pclk_info[] = {
+        {
+                .pclk = &gpt2_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt2_pclk_sel = {
+        .pclk_info = gpt2_pclk_info,
+        .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = GPT2_CLK_ENB,
+        .pclk_sel = &gpt2_pclk_sel,
+        .pclk_sel_shift = GPT2_CLK_SHIFT,
+        .recalc = &follow_parent,
+};
+
+/* clock derived from pll3 clk */
+/* usbh clock */
+static struct clk usbh_clk = {
+        .pclk = &pll3_48m_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = USBH_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+        .pclk = &pll3_48m_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = USBD_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+/* apb masks structure */
+static struct bus_clk_masks apb_masks = {
+        .mask = HCLK_PCLK_RATIO_MASK,
+        .shift = HCLK_PCLK_RATIO_SHIFT,
+};
+
+/* apb configuration structure */
+static struct bus_clk_config apb_config = {
+        .reg = CORE_CLK_CFG,
+        .masks = &apb_masks,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .calc_rate = &bus_calc_rate,
+        .recalc = &bus_clk_recalc,
+        .set_rate = &bus_clk_set_rate,
+        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
+        .private_data = &apb_config,
+};
+
+/* i2c clock */
+static struct clk i2c_clk = {
+        .pclk = &ahb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = I2C_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma_clk = {
+        .pclk = &ahb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = DMA_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+        .pclk = &ahb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = JPEG_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* gmac clock */
+static struct clk gmac_clk = {
+        .pclk = &ahb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = GMAC_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+        .pclk = &ahb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = SMI_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* c3 clock */
+static struct clk c3_clk = {
+        .pclk = &ahb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = C3_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+        .pclk = &apb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = ADC_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* emi clock */
+static struct clk emi_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
+/* ssp clock */
+static struct clk ssp0_clk = {
+        .pclk = &apb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = SSP_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio_clk = {
+        .pclk = &apb_clk,
+        .en_reg = PERIP1_CLK_ENB,
+        .en_reg_bit = GPIO_CLK_ENB,
+        .recalc = &follow_parent,
+};
+
+static struct clk dummy_apb_pclk;
+
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
+        defined(CONFIG_MACH_SPEAR320)
+/* fsmc clock */
+static struct clk fsmc_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
+/* common clocks to spear310 and spear320 */
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* uart1 clock */
+static struct clk uart1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* uart2 clock */
+static struct clk uart2_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+
+/* common clocks to spear300 and spear320 */
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+/* clcd clock */
+static struct clk clcd_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll3_48m_clk,
+        .recalc = &follow_parent,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+
+/* spear300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR300
+/* gpio1 clock */
+static struct clk gpio1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+#endif
+
+/* spear310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR310
+/* uart3 clock */
+static struct clk uart3_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* uart4 clock */
+static struct clk uart4_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* uart5 clock */
+static struct clk uart5_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
+/* spear320 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR320
+/* can0 clock */
+static struct clk can0_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* can1 clock */
+static struct clk can1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* i2c1 clock */
+static struct clk i2c1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+
+/* ssp1 clock */
+static struct clk ssp1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* ssp2 clock */
+static struct clk ssp2_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* pwm clock */
+static struct clk pwm_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
+/* array of all spear 3xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        /* root clks */
+        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
+        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
+        /* clock derived from 32 KHz osc clk */
+        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        /* clock derived from 24 MHz osc clk */
+        { .con_id = "pll1_clk",         .clk = &pll1_clk},
+        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
+        { .dev_id = "wdt",              .clk = &wdt_clk},
+        /* clock derived from pll1 clk */
+        { .con_id = "cpu_clk",          .clk = &cpu_clk},
+        { .con_id = "ahb_clk",          .clk = &ahb_clk},
+        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
+        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
+        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
+        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
+        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
+        { .dev_id = "uart",             .clk = &uart_clk},
+        { .dev_id = "firda",            .clk = &firda_clk},
+        { .dev_id = "gpt0",             .clk = &gpt0_clk},
+        { .dev_id = "gpt1",             .clk = &gpt1_clk},
+        { .dev_id = "gpt2",             .clk = &gpt2_clk},
+        /* clock derived from pll3 clk */
+        { .dev_id = "designware_udc",   .clk = &usbd_clk},
+        { .con_id = "usbh_clk",         .clk = &usbh_clk},
+        /* clock derived from ahb clk */
+        { .con_id = "apb_clk",          .clk = &apb_clk},
+        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
+        { .dev_id = "dma",              .clk = &dma_clk},
+        { .dev_id = "jpeg",             .clk = &jpeg_clk},
+        { .dev_id = "gmac",             .clk = &gmac_clk},
+        { .dev_id = "smi",              .clk = &smi_clk},
+        { .dev_id = "c3",               .clk = &c3_clk},
+        /* clock derived from apb clk */
+        { .dev_id = "adc",              .clk = &adc_clk},
+        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
+        { .dev_id = "gpio",             .clk = &gpio_clk},
+};
+
+/* array of all spear 300 clock lookups */
+#ifdef CONFIG_MACH_SPEAR300
+static struct clk_lookup spear300_clk_lookups[] = {
+        { .dev_id = "clcd",             .clk = &clcd_clk},
+        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        { .dev_id = "gpio1",            .clk = &gpio1_clk},
+        { .dev_id = "keyboard",         .clk = &kbd_clk},
+        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+};
+#endif
+
+/* array of all spear 310 clock lookups */
+#ifdef CONFIG_MACH_SPEAR310
+static struct clk_lookup spear310_clk_lookups[] = {
+        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        { .con_id = "emi",              .clk = &emi_clk},
+        { .dev_id = "uart1",            .clk = &uart1_clk},
+        { .dev_id = "uart2",            .clk = &uart2_clk},
+        { .dev_id = "uart3",            .clk = &uart3_clk},
+        { .dev_id = "uart4",            .clk = &uart4_clk},
+        { .dev_id = "uart5",            .clk = &uart5_clk},
+};
+#endif
+
+/* array of all spear 320 clock lookups */
+#ifdef CONFIG_MACH_SPEAR320
+static struct clk_lookup spear320_clk_lookups[] = {
+        { .dev_id = "clcd",             .clk = &clcd_clk},
+        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
+        { .con_id = "emi",              .clk = &emi_clk},
+        { .dev_id = "pwm",              .clk = &pwm_clk},
+        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
+        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
+        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
+        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
+        { .dev_id = "uart1",            .clk = &uart1_clk},
+        { .dev_id = "uart2",            .clk = &uart2_clk},
+};
+#endif
+
+void __init spear3xx_clk_init(void)
+{
+        int i, cnt;
+        struct clk_lookup *lookups;
+
+        if (machine_is_spear300()) {
+                cnt = ARRAY_SIZE(spear300_clk_lookups);
+                lookups = spear300_clk_lookups;
+        } else if (machine_is_spear310()) {
+                cnt = ARRAY_SIZE(spear310_clk_lookups);
+                lookups = spear310_clk_lookups;
+        } else {
+                cnt = ARRAY_SIZE(spear320_clk_lookups);
+                lookups = spear320_clk_lookups;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+
+        for (i = 0; i < cnt; i++)
+                clk_register(&lookups[i]);
+
+        clk_init();
+}
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
new file mode 100644
index 00000000000..53da4224ba3
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/vic.h>
+#include <mach/hardware.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =VA_SPEAR3XX_ML1_VIC_BASE
+                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get status
+                teq     \irqstat, #0
+                beq     1001f                           @ this will set/reset
+                                                        @ zero register
+                /*
+                 * Following code will find bit position of least significang
+                 * bit set in irqstat, using following equation
+                 * least significant bit set in n = (n & ~(n-1))
+                 */
+                sub     \tmp, \irqstat, #1              @ tmp = irqstat - 1
+                mvn     \tmp, \tmp                      @ tmp = ~tmp
+                and     \irqstat, \irqstat, \tmp        @ irqstat &= tmp
+                /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
+                clz     \tmp, \irqstat                  @ tmp = leading zeros
+                rsb     \irqnr, \tmp, #0x1F             @ irqnr = 32 - tmp - 1
+
+1001:           /* EQ will be set if no irqs pending */
+                .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
new file mode 100644
index 00000000000..451b2081bfc
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/gpio.h
+ *
+ * GPIO macros for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h
new file mode 100644
index 00000000000..30cff8a1f6b
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/io.h
+ *
+ * IO definitions for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h
new file mode 100644
index 00000000000..51735221ea1
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/memory.h
+ *
+ * Memory map for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
new file mode 100644
index 00000000000..3b6ea072904
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear300.h
+ *
+ * SPEAr300 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef  CONFIG_MACH_SPEAR300
+
+#ifndef __MACH_SPEAR300_H
+#define __MACH_SPEAR300_H
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG       0x54
+#define SPEAR300_INT_STS_MASK_REG       0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
+
+#define SPEAR300_CLCD_BASE              UL(0x60000000)
+#define SPEAR300_SDHCI_BASE             UL(0x70000000)
+#define SPEAR300_NAND_0_BASE            UL(0x80000000)
+#define SPEAR300_NAND_1_BASE            UL(0x84000000)
+#define SPEAR300_NAND_2_BASE            UL(0x88000000)
+#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
+#define SPEAR300_NOR_0_BASE             UL(0x90000000)
+#define SPEAR300_NOR_1_BASE             UL(0x91000000)
+#define SPEAR300_NOR_2_BASE             UL(0x92000000)
+#define SPEAR300_NOR_3_BASE             UL(0x93000000)
+#define SPEAR300_FSMC_BASE              UL(0x94000000)
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
+#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
+#define SPEAR300_GPIO_BASE              UL(0xA9000000)
+
+#endif /* __MACH_SPEAR300_H */
+
+#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
new file mode 100644
index 00000000000..1567d0da725
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -0,0 +1,58 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear310.h
+ *
+ * SPEAr310 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef  CONFIG_MACH_SPEAR310
+
+#ifndef __MACH_SPEAR310_H
+#define __MACH_SPEAR310_H
+
+#define SPEAR310_NAND_BASE              UL(0x40000000)
+#define SPEAR310_FSMC_BASE              UL(0x44000000)
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
+#define SPEAR310_HDLC_BASE              UL(0xB2800000)
+#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
+#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG       0x04
+#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
+
+#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
+
+#endif /* __MACH_SPEAR310_H */
+
+#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
new file mode 100644
index 00000000000..8cfa83fa129
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -0,0 +1,67 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear320.h
+ *
+ * SPEAr320 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef  CONFIG_MACH_SPEAR320
+
+#ifndef __MACH_SPEAR320_H
+#define __MACH_SPEAR320_H
+
+#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
+#define SPEAR320_FSMC_BASE              UL(0x4C000000)
+#define SPEAR320_NAND_BASE              UL(0x50000000)
+#define SPEAR320_I2S_BASE               UL(0x60000000)
+#define SPEAR320_SDHCI_BASE             UL(0x70000000)
+#define SPEAR320_CLCD_BASE              UL(0x90000000)
+#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
+#define SPEAR320_CAN0_BASE              UL(0xA1000000)
+#define SPEAR320_CAN1_BASE              UL(0xA2000000)
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
+#define SPEAR320_I2C_BASE               UL(0xA7000000)
+#define SPEAR320_PWM_BASE               UL(0xA8000000)
+#define SPEAR320_SMII0_BASE             UL(0xAA000000)
+#define SPEAR320_SMII1_BASE             UL(0xAB000000)
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG               0x04
+#define SPEAR320_INT_CLR_MASK_REG               0x04
+#define SPEAR320_INT_ENB_MASK_REG               0x08
+#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
+
+#endif /* __MACH_SPEAR320_H */
+
+#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
new file mode 100644
index 00000000000..92cee6335c9
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/system.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/system.h
+ *
+ * SPEAr3xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <plat/system.h>
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
new file mode 100644
index 00000000000..df977b3c9a6
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#include <plat/vmalloc.h>
+
+#endif /* __MACH_VMALLOC_H */
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
new file mode 100644
index 00000000000..69006f69422
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -0,0 +1,72 @@
+/*
+ * arch/arm/mach-spear3xx/spear300_evb.c
+ *
+ * SPEAr300 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+        /* spear3xx specific devices */
+        &spear3xx_pmx_i2c,
+        &spear3xx_pmx_ssp_cs,
+        &spear3xx_pmx_ssp,
+        &spear3xx_pmx_mii,
+        &spear3xx_pmx_uart0,
+
+        /* spear300 specific devices */
+        &spear300_pmx_fsmc_2_chips,
+        &spear300_pmx_clcd,
+        &spear300_pmx_telecom_sdhci_4bit,
+        &spear300_pmx_gpio1,
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        /* spear3xx specific devices */
+        &spear3xx_gpio_device,
+        &spear3xx_uart_device,
+
+        /* spear300 specific devices */
+        &spear300_gpio1_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+        /* spear3xx specific devices */
+
+        /* spear300 specific devices */
+};
+
+static void __init spear300_evb_init(void)
+{
+        unsigned int i;
+
+        /* call spear300 machine init function */
+        spear300_init(&spear300_photo_frame_mode, pmx_devs,
+                        ARRAY_SIZE(pmx_devs));
+
+        /* Add Platform Devices */
+        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+        /* Add Amba Devices */
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+                amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
+        .boot_params    =       0x00000100,
+        .map_io         =       spear3xx_map_io,
+        .init_irq       =       spear3xx_init_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear300_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
new file mode 100644
index 00000000000..c8684ce1f9b
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-spear3xx/spear310_evb.c
+ *
+ * SPEAr310 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+        /* spear3xx specific devices */
+        &spear3xx_pmx_i2c,
+        &spear3xx_pmx_ssp,
+        &spear3xx_pmx_gpio_pin0,
+        &spear3xx_pmx_gpio_pin1,
+        &spear3xx_pmx_gpio_pin2,
+        &spear3xx_pmx_gpio_pin3,
+        &spear3xx_pmx_gpio_pin4,
+        &spear3xx_pmx_gpio_pin5,
+        &spear3xx_pmx_uart0,
+
+        /* spear310 specific devices */
+        &spear310_pmx_emi_cs_0_1_4_5,
+        &spear310_pmx_emi_cs_2_3,
+        &spear310_pmx_uart1,
+        &spear310_pmx_uart2,
+        &spear310_pmx_uart3_4_5,
+        &spear310_pmx_fsmc,
+        &spear310_pmx_rs485_0_1,
+        &spear310_pmx_tdm0,
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        /* spear3xx specific devices */
+        &spear3xx_gpio_device,
+        &spear3xx_uart_device,
+
+        /* spear310 specific devices */
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+        /* spear3xx specific devices */
+
+        /* spear310 specific devices */
+};
+
+static void __init spear310_evb_init(void)
+{
+        unsigned int i;
+
+        /* call spear310 machine init function */
+        spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
+
+        /* Add Platform Devices */
+        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+        /* Add Amba Devices */
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+                amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
+        .boot_params    =       0x00000100,
+        .map_io         =       spear3xx_map_io,
+        .init_irq       =       spear3xx_init_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear310_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
new file mode 100644
index 00000000000..a12b353940d
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/mach-spear3xx/spear320_evb.c
+ *
+ * SPEAr320 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+        /* spear3xx specific devices */
+        &spear3xx_pmx_i2c,
+        &spear3xx_pmx_ssp,
+        &spear3xx_pmx_mii,
+        &spear3xx_pmx_uart0,
+
+        /* spear320 specific devices */
+        &spear320_pmx_fsmc,
+        &spear320_pmx_sdhci,
+        &spear320_pmx_i2s,
+        &spear320_pmx_uart1,
+        &spear320_pmx_uart2,
+        &spear320_pmx_can,
+        &spear320_pmx_pwm0,
+        &spear320_pmx_pwm1,
+        &spear320_pmx_pwm2,
+        &spear320_pmx_mii1,
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        /* spear3xx specific devices */
+        &spear3xx_gpio_device,
+        &spear3xx_uart_device,
+
+        /* spear320 specific devices */
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+        /* spear3xx specific devices */
+
+        /* spear320 specific devices */
+};
+
+static void __init spear320_evb_init(void)
+{
+        unsigned int i;
+
+        /* call spear320 machine init function */
+        spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
+                        ARRAY_SIZE(pmx_devs));
+
+        /* Add Platform Devices */
+        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+        /* Add Amba Devices */
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+                amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
+        .boot_params    =       0x00000100,
+        .map_io         =       spear3xx_map_io,
+        .init_irq       =       spear3xx_init_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear320_evb_init,
+MACHINE_END