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authorKukjin Kim <kgene.kim@samsung.com>2011-01-04 19:39:23 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-01-04 19:39:23 -0500
commitab10f1dd914ad87e0370bd8b82f77dcd32b6d941 (patch)
tree3879eaf6d7ede69d2757a5db2bf0de5e6bd3c367 /arch/arm/mach-s5pc100
parentf56d463423b825ff5bf4b63e0dc443557934165c (diff)
parent957c461e82f7a8ddcd7fb25c01c43917f64fde33 (diff)
Merge branch 'dev/cleanup-clocks' into for-next
Diffstat (limited to 'arch/arm/mach-s5pc100')
-rw-r--r--arch/arm/mach-s5pc100/clock.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 2d4a761a516..0305e9b8282 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -396,7 +396,7 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
396 * recommended to keep the following clocks disabled until the driver requests 396 * recommended to keep the following clocks disabled until the driver requests
397 * for enabling the clock. 397 * for enabling the clock.
398 */ 398 */
399static struct clk init_clocks_disable[] = { 399static struct clk init_clocks_off[] = {
400 { 400 {
401 .name = "cssys", 401 .name = "cssys",
402 .id = -1, 402 .id = -1,
@@ -1381,8 +1381,6 @@ static struct clk *clks[] __initdata = {
1381 1381
1382void __init s5pc100_register_clocks(void) 1382void __init s5pc100_register_clocks(void)
1383{ 1383{
1384 struct clk *clkp;
1385 int ret;
1386 int ptr; 1384 int ptr;
1387 1385
1388 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); 1386 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
@@ -1393,16 +1391,8 @@ void __init s5pc100_register_clocks(void)
1393 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1391 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1394 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1392 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1395 1393
1396 clkp = init_clocks_disable; 1394 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1397 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 1395 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1398
1399 ret = s3c24xx_register_clock(clkp);
1400 if (ret < 0) {
1401 printk(KERN_ERR "Failed to register clock %s (%d)\n",
1402 clkp->name, ret);
1403 }
1404 (clkp->enable)(clkp, 0);
1405 }
1406 1396
1407 s3c_pwmclk_init(); 1397 s3c_pwmclk_init();
1408} 1398}