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authorLinus Torvalds <torvalds@linux-foundation.org>2012-01-09 17:28:38 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-01-09 17:28:38 -0500
commitdfc1ebe76663d582a01c9dc572395cf8086d01de (patch)
tree54a5ac91214a90f82c27b6e38099a4470837729e /arch/arm/mach-s5p64x0
parentacc952c1f373bf3f66cc7a10680eee1762bed40b (diff)
parentb001befe58691ef3627458cd814e8cee7f845c5f (diff)
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Device tree conversions for samsung and tegra Both platforms had some initial device tree support, but this adds much more to actually make it usable. * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits) ARM: dts: Add intial dts file for EXYNOS4210 SoC, SMDKV310 and ORIGEN ARM: EXYNOS: Add Exynos4 device tree enabled board file rtc: rtc-s3c: Add device tree support input: samsung-keypad: Add device tree support ARM: S5PV210: Modify platform data for pl330 driver ARM: S5PC100: Modify platform data for pl330 driver ARM: S5P64x0: Modify platform data for pl330 driver ARM: EXYNOS: Add a alias for pdma clocks ARM: EXYNOS: Limit usage of pl330 device instance to non-dt build ARM: SAMSUNG: Add device tree support for pl330 dma engine wrappers DMA: PL330: Add device tree support ARM: EXYNOS: Modify platform data for pl330 driver DMA: PL330: Infer transfer direction from transfer request instead of platform data DMA: PL330: move filter function into driver serial: samsung: Fix build for non-Exynos4210 devices serial: samsung: add device tree support serial: samsung: merge probe() function from all SoC specific extensions serial: samsung: merge all SoC specific port reset functions ARM: SAMSUNG: register uart clocks to clock lookup list serial: samsung: remove all uses of get_clksrc and set_clksrc ... Fix up fairly trivial conflicts in arch/arm/mach-s3c2440/clock.c and drivers/tty/serial/Kconfig both due to just adding code close to changes.
Diffstat (limited to 'arch/arm/mach-s5p64x0')
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c32
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c32
-rw-r--r--arch/arm/mach-s5p64x0/common.c31
-rw-r--r--arch/arm/mach-s5p64x0/dma.c227
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h2
5 files changed, 113 insertions, 211 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index eb4ffe331e1..4c797ab3b3f 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -422,15 +422,6 @@ static struct clksrc_clk clksrcs[] = {
422 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 422 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
423 }, { 423 }, {
424 .clk = { 424 .clk = {
425 .name = "uclk1",
426 .ctrlbit = (1 << 5),
427 .enable = s5p64x0_sclk_ctrl,
428 },
429 .sources = &clkset_uart,
430 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
432 }, {
433 .clk = {
434 .name = "sclk_spi", 425 .name = "sclk_spi",
435 .devname = "s3c64xx-spi.0", 426 .devname = "s3c64xx-spi.0",
436 .ctrlbit = (1 << 20), 427 .ctrlbit = (1 << 20),
@@ -488,6 +479,17 @@ static struct clksrc_clk clksrcs[] = {
488 }, 479 },
489}; 480};
490 481
482static struct clksrc_clk clk_sclk_uclk = {
483 .clk = {
484 .name = "uclk1",
485 .ctrlbit = (1 << 5),
486 .enable = s5p64x0_sclk_ctrl,
487 },
488 .sources = &clkset_uart,
489 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
490 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
491};
492
491/* Clock initialization code */ 493/* Clock initialization code */
492static struct clksrc_clk *sysclks[] = { 494static struct clksrc_clk *sysclks[] = {
493 &clk_mout_apll, 495 &clk_mout_apll,
@@ -506,6 +508,15 @@ static struct clk dummy_apb_pclk = {
506 .id = -1, 508 .id = -1,
507}; 509};
508 510
511static struct clksrc_clk *clksrc_cdev[] = {
512 &clk_sclk_uclk,
513};
514
515static struct clk_lookup s5p6440_clk_lookup[] = {
516 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
517 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
518};
519
509void __init_or_cpufreq s5p6440_setup_clocks(void) 520void __init_or_cpufreq s5p6440_setup_clocks(void)
510{ 521{
511 struct clk *xtal_clk; 522 struct clk *xtal_clk;
@@ -584,9 +595,12 @@ void __init s5p6440_register_clocks(void)
584 595
585 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 596 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
586 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 597 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
598 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
599 s3c_register_clksrc(clksrc_cdev[ptr], 1);
587 600
588 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 601 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
589 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 602 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
603 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
590 604
591 s3c24xx_register_clock(&dummy_apb_pclk); 605 s3c24xx_register_clock(&dummy_apb_pclk);
592 606
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index bb7ee912090..26aa63402d6 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -444,15 +444,6 @@ static struct clksrc_clk clksrcs[] = {
444 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 444 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
445 }, { 445 }, {
446 .clk = { 446 .clk = {
447 .name = "uclk1",
448 .ctrlbit = (1 << 5),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_uart,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi", 447 .name = "sclk_spi",
457 .devname = "s3c64xx-spi.0", 448 .devname = "s3c64xx-spi.0",
458 .ctrlbit = (1 << 20), 449 .ctrlbit = (1 << 20),
@@ -537,6 +528,26 @@ static struct clksrc_clk clksrcs[] = {
537 }, 528 },
538}; 529};
539 530
531static struct clksrc_clk clk_sclk_uclk = {
532 .clk = {
533 .name = "uclk1",
534 .ctrlbit = (1 << 5),
535 .enable = s5p64x0_sclk_ctrl,
536 },
537 .sources = &clkset_uart,
538 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
539 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
540};
541
542static struct clksrc_clk *clksrc_cdev[] = {
543 &clk_sclk_uclk,
544};
545
546static struct clk_lookup s5p6450_clk_lookup[] = {
547 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
548 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
549};
550
540/* Clock initialization code */ 551/* Clock initialization code */
541static struct clksrc_clk *sysclks[] = { 552static struct clksrc_clk *sysclks[] = {
542 &clk_mout_apll, 553 &clk_mout_apll,
@@ -635,9 +646,12 @@ void __init s5p6450_register_clocks(void)
635 646
636 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 647 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
637 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 648 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
649 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
650 s3c_register_clksrc(clksrc_cdev[ptr], 1);
638 651
639 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 652 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
640 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 653 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
654 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
641 655
642 s3c24xx_register_clock(&dummy_apb_pclk); 656 s3c24xx_register_clock(&dummy_apb_pclk);
643 657
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 28d0b918cd4..0d50e79fb9f 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -282,36 +282,7 @@ int __init s5p64x0_init(void)
282 return device_register(&s5p64x0_dev); 282 return device_register(&s5p64x0_dev);
283} 283}
284 284
285static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
286 [0] = {
287 .name = "pclk_low",
288 .divisor = 1,
289 .min_baud = 0,
290 .max_baud = 0,
291 },
292 [1] = {
293 .name = "uclk1",
294 .divisor = 1,
295 .min_baud = 0,
296 .max_baud = 0,
297 },
298};
299
300/* uart registration process */ 285/* uart registration process */
301
302void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
303{
304 struct s3c2410_uartcfg *tcfg = cfg;
305 u32 ucnt;
306
307 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
308 if (!tcfg->clocks) {
309 tcfg->clocks = s5p64x0_serial_clocks;
310 tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
311 }
312 }
313}
314
315void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) 286void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
316{ 287{
317 int uart; 288 int uart;
@@ -321,13 +292,11 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
321 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART; 292 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
322 } 293 }
323 294
324 s5p64x0_common_init_uarts(cfg, no);
325 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); 295 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
326} 296}
327 297
328void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no) 298void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
329{ 299{
330 s5p64x0_common_init_uarts(cfg, no);
331 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); 300 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
332} 301}
333 302
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 442dd4ad12d..f820c074440 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,176 +38,74 @@
38 38
39static u64 dma_dmamask = DMA_BIT_MASK(32); 39static u64 dma_dmamask = DMA_BIT_MASK(32);
40 40
41struct dma_pl330_peri s5p6440_pdma_peri[22] = { 41u8 s5p6440_pdma_peri[] = {
42 { 42 DMACH_UART0_RX,
43 .peri_id = (u8)DMACH_UART0_RX, 43 DMACH_UART0_TX,
44 .rqtype = DEVTOMEM, 44 DMACH_UART1_RX,
45 }, { 45 DMACH_UART1_TX,
46 .peri_id = (u8)DMACH_UART0_TX, 46 DMACH_UART2_RX,
47 .rqtype = MEMTODEV, 47 DMACH_UART2_TX,
48 }, { 48 DMACH_UART3_RX,
49 .peri_id = (u8)DMACH_UART1_RX, 49 DMACH_UART3_TX,
50 .rqtype = DEVTOMEM, 50 DMACH_MAX,
51 }, { 51 DMACH_MAX,
52 .peri_id = (u8)DMACH_UART1_TX, 52 DMACH_PCM0_TX,
53 .rqtype = MEMTODEV, 53 DMACH_PCM0_RX,
54 }, { 54 DMACH_I2S0_TX,
55 .peri_id = (u8)DMACH_UART2_RX, 55 DMACH_I2S0_RX,
56 .rqtype = DEVTOMEM, 56 DMACH_SPI0_TX,
57 }, { 57 DMACH_SPI0_RX,
58 .peri_id = (u8)DMACH_UART2_TX, 58 DMACH_MAX,
59 .rqtype = MEMTODEV, 59 DMACH_MAX,
60 }, { 60 DMACH_MAX,
61 .peri_id = (u8)DMACH_UART3_RX, 61 DMACH_MAX,
62 .rqtype = DEVTOMEM, 62 DMACH_SPI1_TX,
63 }, { 63 DMACH_SPI1_RX,
64 .peri_id = (u8)DMACH_UART3_TX,
65 .rqtype = MEMTODEV,
66 }, {
67 .peri_id = DMACH_MAX,
68 }, {
69 .peri_id = DMACH_MAX,
70 }, {
71 .peri_id = (u8)DMACH_PCM0_TX,
72 .rqtype = MEMTODEV,
73 }, {
74 .peri_id = (u8)DMACH_PCM0_RX,
75 .rqtype = DEVTOMEM,
76 }, {
77 .peri_id = (u8)DMACH_I2S0_TX,
78 .rqtype = MEMTODEV,
79 }, {
80 .peri_id = (u8)DMACH_I2S0_RX,
81 .rqtype = DEVTOMEM,
82 }, {
83 .peri_id = (u8)DMACH_SPI0_TX,
84 .rqtype = MEMTODEV,
85 }, {
86 .peri_id = (u8)DMACH_SPI0_RX,
87 .rqtype = DEVTOMEM,
88 }, {
89 .peri_id = (u8)DMACH_MAX,
90 }, {
91 .peri_id = (u8)DMACH_MAX,
92 }, {
93 .peri_id = (u8)DMACH_MAX,
94 }, {
95 .peri_id = (u8)DMACH_MAX,
96 }, {
97 .peri_id = (u8)DMACH_SPI1_TX,
98 .rqtype = MEMTODEV,
99 }, {
100 .peri_id = (u8)DMACH_SPI1_RX,
101 .rqtype = DEVTOMEM,
102 },
103}; 64};
104 65
105struct dma_pl330_platdata s5p6440_pdma_pdata = { 66struct dma_pl330_platdata s5p6440_pdma_pdata = {
106 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), 67 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
107 .peri = s5p6440_pdma_peri, 68 .peri_id = s5p6440_pdma_peri,
108}; 69};
109 70
110struct dma_pl330_peri s5p6450_pdma_peri[32] = { 71u8 s5p6450_pdma_peri[] = {
111 { 72 DMACH_UART0_RX,
112 .peri_id = (u8)DMACH_UART0_RX, 73 DMACH_UART0_TX,
113 .rqtype = DEVTOMEM, 74 DMACH_UART1_RX,
114 }, { 75 DMACH_UART1_TX,
115 .peri_id = (u8)DMACH_UART0_TX, 76 DMACH_UART2_RX,
116 .rqtype = MEMTODEV, 77 DMACH_UART2_TX,
117 }, { 78 DMACH_UART3_RX,
118 .peri_id = (u8)DMACH_UART1_RX, 79 DMACH_UART3_TX,
119 .rqtype = DEVTOMEM, 80 DMACH_UART4_RX,
120 }, { 81 DMACH_UART4_TX,
121 .peri_id = (u8)DMACH_UART1_TX, 82 DMACH_PCM0_TX,
122 .rqtype = MEMTODEV, 83 DMACH_PCM0_RX,
123 }, { 84 DMACH_I2S0_TX,
124 .peri_id = (u8)DMACH_UART2_RX, 85 DMACH_I2S0_RX,
125 .rqtype = DEVTOMEM, 86 DMACH_SPI0_TX,
126 }, { 87 DMACH_SPI0_RX,
127 .peri_id = (u8)DMACH_UART2_TX, 88 DMACH_PCM1_TX,
128 .rqtype = MEMTODEV, 89 DMACH_PCM1_RX,
129 }, { 90 DMACH_PCM2_TX,
130 .peri_id = (u8)DMACH_UART3_RX, 91 DMACH_PCM2_RX,
131 .rqtype = DEVTOMEM, 92 DMACH_SPI1_TX,
132 }, { 93 DMACH_SPI1_RX,
133 .peri_id = (u8)DMACH_UART3_TX, 94 DMACH_USI_TX,
134 .rqtype = MEMTODEV, 95 DMACH_USI_RX,
135 }, { 96 DMACH_MAX,
136 .peri_id = (u8)DMACH_UART4_RX, 97 DMACH_I2S1_TX,
137 .rqtype = DEVTOMEM, 98 DMACH_I2S1_RX,
138 }, { 99 DMACH_I2S2_TX,
139 .peri_id = (u8)DMACH_UART4_TX, 100 DMACH_I2S2_RX,
140 .rqtype = MEMTODEV, 101 DMACH_PWM,
141 }, { 102 DMACH_UART5_RX,
142 .peri_id = (u8)DMACH_PCM0_TX, 103 DMACH_UART5_TX,
143 .rqtype = MEMTODEV,
144 }, {
145 .peri_id = (u8)DMACH_PCM0_RX,
146 .rqtype = DEVTOMEM,
147 }, {
148 .peri_id = (u8)DMACH_I2S0_TX,
149 .rqtype = MEMTODEV,
150 }, {
151 .peri_id = (u8)DMACH_I2S0_RX,
152 .rqtype = DEVTOMEM,
153 }, {
154 .peri_id = (u8)DMACH_SPI0_TX,
155 .rqtype = MEMTODEV,
156 }, {
157 .peri_id = (u8)DMACH_SPI0_RX,
158 .rqtype = DEVTOMEM,
159 }, {
160 .peri_id = (u8)DMACH_PCM1_TX,
161 .rqtype = MEMTODEV,
162 }, {
163 .peri_id = (u8)DMACH_PCM1_RX,
164 .rqtype = DEVTOMEM,
165 }, {
166 .peri_id = (u8)DMACH_PCM2_TX,
167 .rqtype = MEMTODEV,
168 }, {
169 .peri_id = (u8)DMACH_PCM2_RX,
170 .rqtype = DEVTOMEM,
171 }, {
172 .peri_id = (u8)DMACH_SPI1_TX,
173 .rqtype = MEMTODEV,
174 }, {
175 .peri_id = (u8)DMACH_SPI1_RX,
176 .rqtype = DEVTOMEM,
177 }, {
178 .peri_id = (u8)DMACH_USI_TX,
179 .rqtype = MEMTODEV,
180 }, {
181 .peri_id = (u8)DMACH_USI_RX,
182 .rqtype = DEVTOMEM,
183 }, {
184 .peri_id = (u8)DMACH_MAX,
185 }, {
186 .peri_id = (u8)DMACH_I2S1_TX,
187 .rqtype = MEMTODEV,
188 }, {
189 .peri_id = (u8)DMACH_I2S1_RX,
190 .rqtype = DEVTOMEM,
191 }, {
192 .peri_id = (u8)DMACH_I2S2_TX,
193 .rqtype = MEMTODEV,
194 }, {
195 .peri_id = (u8)DMACH_I2S2_RX,
196 .rqtype = DEVTOMEM,
197 }, {
198 .peri_id = (u8)DMACH_PWM,
199 }, {
200 .peri_id = (u8)DMACH_UART5_RX,
201 .rqtype = DEVTOMEM,
202 }, {
203 .peri_id = (u8)DMACH_UART5_TX,
204 .rqtype = MEMTODEV,
205 },
206}; 104};
207 105
208struct dma_pl330_platdata s5p6450_pdma_pdata = { 106struct dma_pl330_platdata s5p6450_pdma_pdata = {
209 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), 107 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
210 .peri = s5p6450_pdma_peri, 108 .peri_id = s5p6450_pdma_peri,
211}; 109};
212 110
213struct amba_device s5p64x0_device_pdma = { 111struct amba_device s5p64x0_device_pdma = {
@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = {
227 125
228static int __init s5p64x0_dma_init(void) 126static int __init s5p64x0_dma_init(void)
229{ 127{
230 if (soc_is_s5p6450()) 128 if (soc_is_s5p6450()) {
129 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
130 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
231 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 131 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
232 else 132 } else {
133 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
134 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
233 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 135 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
136 }
234 137
235 amba_device_register(&s5p64x0_device_pdma, &iomem_resource); 138 amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
236 139
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 53982db9d25..5b845e849b3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,6 +141,8 @@
141 141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) 142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143 143
144#define IRQ_TIMER_BASE (11)
145
144/* Set the default NR_IRQS */ 146/* Set the default NR_IRQS */
145 147
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) 148#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 09:56:50 -0500