Merge branch 'omap4-i2c-init' into omap-for-linus

12 files changed, 569 insertions, 111 deletions

diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
index 4c29ff8b07d..77aeffd1733 100644
--- a/arch/arm/mach-s5p6440/Kconfig
+++ b/arch/arm/mach-s5p6440/Kconfig
@@ -9,6 +9,7 @@ if ARCH_S5P6440
 
 config CPU_S5P6440
         bool
+        select S3C_PL330_DMA
         help
           Enable S5P6440 CPU support
 
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
index 1ad894b1d3a..44facf43d59 100644
--- a/arch/arm/mach-s5p6440/Makefile
+++ b/arch/arm/mach-s5p6440/Makefile
@@ -12,8 +12,12 @@ obj-				:=
 
 # Core support for S5P6440 system
 
-obj-$(CONFIG_CPU_S5P6440)       += cpu.o init.o clock.o gpio.o
+obj-$(CONFIG_CPU_S5P6440)       += cpu.o init.o clock.o gpio.o dma.o
+obj-$(CONFIG_CPU_S5P6440)       += setup-i2c0.o
 
 # machine support
 
 obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
+
+# device support
+obj-y                           += dev-audio.o
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
index b2672e16e7a..ca6e48dce77 100644
--- a/arch/arm/mach-s5p6440/clock.c
+++ b/arch/arm/mach-s5p6440/clock.c
@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
 };
 
-static struct clk clk_h_low = {
-        .name           = "hclk_low",
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
-static struct clk clk_p_low = {
-        .name           = "pclk_low",
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .ops            = &clk_ops_def_setrate,
-};
-
 enum perf_level {
         L0 = 532*1000,
         L1 = 266*1000,
@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
         .round_rate     = s5p6440_armclk_round_rate,
 };
 
-static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
+static struct clksrc_clk clk_armclk = {
+        .clk    = {
+                .name   = "armclk",
+                .id     = 1,
+                .parent = &clk_mout_apll.clk,
+                .ops    = &s5p6440_clkarm_ops,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
+};
 
-        if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK)
-                rate /= 2;
+static struct clksrc_clk clk_dout_mpll = {
+        .clk    = {
+                .name   = "dout_mpll",
+                .id     = -1,
+                .parent = &clk_mout_mpll.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
+};
 
-        return rate;
-}
+static struct clksrc_clk clk_hclk = {
+        .clk    = {
+                .name   = "clk_hclk",
+                .id     = -1,
+                .parent = &clk_armclk.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
+};
 
-static struct clk clk_dout_mpll = {
-        .name           = "dout_mpll",
-        .id             = -1,
-        .parent         = &clk_mout_mpll.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s5p6440_clk_doutmpll_get_rate,
+static struct clksrc_clk clk_pclk = {
+        .clk    = {
+                .name   = "clk_pclk",
+                .id     = -1,
+                .parent = &clk_hclk.clk,
         },
+        .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
+};
+
+static struct clk *clkset_hclklow_list[] = {
+        &clk_mout_apll.clk,
+        &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_hclklow = {
+        .sources        = clkset_hclklow_list,
+        .nr_sources     = ARRAY_SIZE(clkset_hclklow_list),
+};
+
+static struct clksrc_clk clk_hclk_low = {
+        .clk = {
+                .name   = "hclk_low",
+                .id     = -1,
+        },
+        .sources        = &clkset_hclklow,
+        .reg_src        = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
+        .reg_div        = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_pclk_low = {
+        .clk    = {
+                .name   = "pclk_low",
+                .id     = -1,
+                .parent = &clk_hclk_low.clk,
+        },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 };
 
 int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
 }
 
+static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
+}
+
 static int s5p6440_mem_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
         {
                 .name           = "nand",
                 .id             = -1,
-                .parent         = &clk_h,
+                .parent         = &clk_hclk.clk,
                 .enable         = s5p6440_mem_ctrl,
                 .ctrlbit        = S5P_CLKCON_MEM0_HCLK_NFCON,
         }, {
                 .name           = "adc",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_TSADC,
         }, {
                 .name           = "i2c",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_IIC0,
         }, {
                 .name           = "i2s_v40",
                 .id             = 0,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_IIS2,
         }, {
                 .name           = "spi",
                 .id             = 0,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_SPI0,
         }, {
                 .name           = "spi",
                 .id             = 1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_SPI1,
         }, {
@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
         }, {
                 .name           = "otg",
                 .id             = -1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_USB
         }, {
                 .name           = "post",
                 .id             = -1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_POST0
         }, {
                 .name           = "lcd",
                 .id             = -1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk1_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK1_DISPCON,
         }, {
                 .name           = "hsmmc",
                 .id             = 0,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC0,
         }, {
                 .name           = "hsmmc",
                 .id             = 1,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC1,
         }, {
                 .name           = "hsmmc",
                 .id             = 2,
-                .parent         = &clk_h_low,
+                .parent         = &clk_hclk_low.clk,
                 .enable         = s5p6440_hclk0_ctrl,
                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC2,
         }, {
                 .name           = "rtc",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_RTC,
         }, {
                 .name           = "watchdog",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_WDT,
         }, {
                 .name           = "timers",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_PWM,
-        }
+        }, {
+                .name           = "hclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk1_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "tsi",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p6440_hclk1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "pclk_fimgvg",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 31),
+        }, {
+                .name           = "dmc0",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 30),
+        }, {
+                .name           = "etm",
+                .id             = -1,
+                .parent         = &clk_pclk.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 29),
+        }, {
+                .name           = "dsim",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
+                .name           = "gps",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "pcm",
+                .id             = -1,
+                .parent         = &clk_pclk_low.clk,
+                .enable         = s5p6440_pclk_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "irom",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "dma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "2d",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
 };
 
 /*
@@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
         {
                 .name           = "gpio",
                 .id             = -1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_GPIO,
         }, {
                 .name           = "uart",
                 .id             = 0,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART0,
         }, {
                 .name           = "uart",
                 .id             = 1,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART1,
         }, {
                 .name           = "uart",
                 .id             = 2,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART2,
         }, {
                 .name           = "uart",
                 .id             = 3,
-                .parent         = &clk_p_low,
+                .parent         = &clk_pclk_low.clk,
                 .enable         = s5p6440_pclk_ctrl,
                 .ctrlbit        = S5P_CLKCON_PCLK_UART3,
-        }
+        }, {
+                .name           = "mem",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hclk.clk,
+                .enable         = s5p6440_hclk0_ctrl,
+                .ctrlbit        = (1 << 1),
+        },
 };
 
 static struct clk clk_iis_cd_v40 = {
@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
         .id             = -1,
 };
 
-static struct clk *clkset_spi_mmc_list[] = {
+static struct clk *clkset_group1_list[] = {
         &clk_mout_epll.clk,
-        &clk_dout_mpll,
+        &clk_dout_mpll.clk,
         &clk_fin_epll,
 };
 
-static struct clksrc_sources clkset_spi_mmc = {
-        .sources        = clkset_spi_mmc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
+static struct clksrc_sources clkset_group1 = {
+        .sources        = clkset_group1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 };
 
 static struct clk *clkset_uart_list[] = {
         &clk_mout_epll.clk,
-        &clk_dout_mpll
+        &clk_dout_mpll.clk,
 };
 
 static struct clksrc_sources clkset_uart = {
@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 };
 
+static struct clk *clkset_audio_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll.clk,
+        &clk_fin_epll,
+        &clk_iis_cd_v40,
+        &clk_pcm_cd,
+};
+
+static struct clksrc_sources clkset_audio = {
+        .sources        = clkset_audio_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio_list),
+};
+
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC0,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
         }, {
@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC1,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
         }, {
@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC2,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
         }, {
@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_SPI0,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
         }, {
@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
                         .ctrlbit        = S5P_CLKCON_SCLK0_SPI1,
                         .enable         = s5p6440_sclk_ctrl,
                 },
-                .sources = &clkset_spi_mmc,
+                .sources = &clkset_group1,
                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }
+        }, {
+                .clk    = {
+                        .name           = "sclk_post",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 10),
+                        .enable         = s5p6440_sclk_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dispcon",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 1),
+                        .enable         = s5p6440_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimgvg",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 2),
+                        .enable         = s5p6440_sclk1_ctrl,
+                },
+                .sources = &clkset_group1,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_audio2",
+                        .id             = -1,
+                        .ctrlbit        = (1 << 11),
+                        .enable         = s5p6440_sclk_ctrl,
+                },
+                .sources = &clkset_audio,
+                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
+                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
+        },
 };
 
 /* Clock initialisation code */
-static struct clksrc_clk *init_parents[] = {
+static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
         &clk_mout_epll,
         &clk_mout_mpll,
+        &clk_dout_mpll,
+        &clk_armclk,
+        &clk_hclk,
+        &clk_pclk,
+        &clk_hclk_low,
+        &clk_pclk_low,
 };
 
 void __init_or_cpufreq s5p6440_setup_clocks(void)
@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
         unsigned long apll;
         unsigned long mpll;
         unsigned int ptr;
-        u32 clkdiv0;
-        u32 clkdiv3;
 
         /* Set S5P6440 functions for clk_fout_epll */
         clk_fout_epll.enable = s5p6440_epll_enable;
         clk_fout_epll.ops = &s5p6440_epll_ops;
 
-        /* Set S5P6440 functions for arm clock */
-        clk_arm.parent = &clk_mout_apll.clk;
-        clk_arm.ops = &s5p6440_clkarm_ops;
         clk_48m.enable = s5p6440_clk48m_ctrl;
 
-        clkdiv0 = __raw_readl(S5P_CLK_DIV0);
-        clkdiv3 = __raw_readl(S5P_CLK_DIV3);
-
         xtal_clk = clk_get(NULL, "ext_xtal");
         BUG_ON(IS_ERR(xtal_clk));
 
@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
 
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_apll.rate = apll;
+
         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
                         " E=%ld.%ldMHz\n",
                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 
-        fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM);
-        hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK);
-        pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
-
-        if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
-                /* Asynchronous mode */
-                hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
-        } else {
-                /* Synchronous mode */
-                hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
-        }
-
-        pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
+        fclk = clk_get_rate(&clk_armclk.clk);
+        hclk = clk_get_rate(&clk_hclk.clk);
+        pclk = clk_get_rate(&clk_pclk.clk);
+        hclk_low = clk_get_rate(&clk_hclk_low.clk);
+        pclk_low = clk_get_rate(&clk_pclk_low.clk);
 
         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
                         print_mhz(hclk), print_mhz(hclk_low),
                         print_mhz(pclk), print_mhz(pclk_low));
 
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
-
         clk_f.rate = fclk;
         clk_h.rate = hclk;
         clk_p.rate = pclk;
-        clk_h_low.rate = hclk_low;
-        clk_p_low.rate = pclk_low;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s3c_set_clksrc(init_parents[ptr], true);
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_set_clksrc(&clksrcs[ptr], true);
@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
 
 static struct clk *clks[] __initdata = {
         &clk_ext,
-        &clk_mout_epll.clk,
-        &clk_mout_mpll.clk,
-        &clk_dout_mpll,
         &clk_iis_cd_v40,
         &clk_pcm_cd,
-        &clk_p_low,
-        &clk_h_low,
 };
 
 void __init s5p6440_register_clocks(void)
@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
         if (ret > 0)
                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
index 1794131aeac..ca3b3206e6f 100644
--- a/arch/arm/mach-s5p6440/cpu.c
+++ b/arch/arm/mach-s5p6440/cpu.c
@@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void)
         s5p_init_irq(vic, ARRAY_SIZE(vic));
 }
 
-static struct sysdev_class s5p6440_sysclass = {
+struct sysdev_class s5p6440_sysclass = {
         .name   = "s5p6440-core",
 };
 
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c
new file mode 100644
index 00000000000..0c536796283
--- /dev/null
+++ b/arch/arm/mach-s5p6440/dev-audio.c
@@ -0,0 +1,127 @@
+/* linux/arch/arm/mach-s5p6440/dev-audio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co. Ltd
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/audio.h>
+
+#include <mach/gpio.h>
+#include <mach/map.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+
+static int s5p6440_cfg_i2s(struct platform_device *pdev)
+{
+        /* configure GPIO for i2s port */
+        switch (pdev->id) {
+        case -1:
+                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
+                break;
+
+        default:
+                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s3c_i2s_pdata = {
+        .cfg_gpio = s5p6440_cfg_i2s,
+};
+
+static struct resource s5p6440_iis0_resource[] = {
+        [0] = {
+                .start = S5P6440_PA_I2S,
+                .end   = S5P6440_PA_I2S + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_I2S0_TX,
+                .end   = DMACH_I2S0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_I2S0_RX,
+                .end   = DMACH_I2S0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_iis = {
+        .name             = "s3c64xx-iis-v4",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s5p6440_iis0_resource),
+        .resource         = s5p6440_iis0_resource,
+        .dev = {
+                .platform_data = &s3c_i2s_pdata,
+        },
+};
+
+/* PCM Controller platform_devices */
+
+static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
+{
+        switch (pdev->id) {
+        case 0:
+                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
+                break;
+
+        default:
+                printk(KERN_DEBUG "Invalid PCM Controller number!");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct s3c_audio_pdata s3c_pcm_pdata = {
+        .cfg_gpio = s5p6440_pcm_cfg_gpio,
+};
+
+static struct resource s5p6440_pcm0_resource[] = {
+        [0] = {
+                .start = S5P6440_PA_PCM,
+                .end   = S5P6440_PA_PCM + 0x100 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DMACH_PCM0_TX,
+                .end   = DMACH_PCM0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = DMACH_PCM0_RX,
+                .end   = DMACH_PCM0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+struct platform_device s5p6440_device_pcm = {
+        .name             = "samsung-pcm",
+        .id               = 0,
+        .num_resources    = ARRAY_SIZE(s5p6440_pcm0_resource),
+        .resource         = s5p6440_pcm0_resource,
+        .dev = {
+                .platform_data = &s3c_pcm_pdata,
+        },
+};
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p6440/dma.c
new file mode 100644
index 00000000000..07606ad5751
--- /dev/null
+++ b/arch/arm/mach-s5p6440/dma.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/devs.h>
+#include <plat/irqs.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#include <plat/s3c-pl330-pdata.h>
+
+static u64 dma_dmamask = DMA_BIT_MASK(32);
+
+static struct resource s5p6440_pdma_resource[] = {
+        [0] = {
+                .start  = S5P6440_PA_PDMA,
+                .end    = S5P6440_PA_PDMA + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_DMA0,
+                .end    = IRQ_DMA0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
+        .peri = {
+                [0] = DMACH_UART0_RX,
+                [1] = DMACH_UART0_TX,
+                [2] = DMACH_UART1_RX,
+                [3] = DMACH_UART1_TX,
+                [4] = DMACH_UART2_RX,
+                [5] = DMACH_UART2_TX,
+                [6] = DMACH_UART3_RX,
+                [7] = DMACH_UART3_TX,
+                [8] = DMACH_MAX,
+                [9] = DMACH_MAX,
+                [10] = DMACH_PCM0_TX,
+                [11] = DMACH_PCM0_RX,
+                [12] = DMACH_I2S0_TX,
+                [13] = DMACH_I2S0_RX,
+                [14] = DMACH_SPI0_TX,
+                [15] = DMACH_SPI0_RX,
+                [16] = DMACH_MAX,
+                [17] = DMACH_MAX,
+                [18] = DMACH_MAX,
+                [19] = DMACH_MAX,
+                [20] = DMACH_SPI1_TX,
+                [21] = DMACH_SPI1_RX,
+                [22] = DMACH_MAX,
+                [23] = DMACH_MAX,
+                [24] = DMACH_MAX,
+                [25] = DMACH_MAX,
+                [26] = DMACH_MAX,
+                [27] = DMACH_MAX,
+                [28] = DMACH_MAX,
+                [29] = DMACH_PWM,
+                [30] = DMACH_MAX,
+                [31] = DMACH_MAX,
+        },
+};
+
+static struct platform_device s5p6440_device_pdma = {
+        .name           = "s3c-pl330",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(s5p6440_pdma_resource),
+        .resource       = s5p6440_pdma_resource,
+        .dev            = {
+                .dma_mask = &dma_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &s5p6440_pdma_pdata,
+        },
+};
+
+static struct platform_device *s5p6440_dmacs[] __initdata = {
+        &s5p6440_device_pdma,
+};
+
+static int __init s5p6440_dma_init(void)
+{
+        platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
+
+        return 0;
+}
+arch_initcall(s5p6440_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c
index b0ea741177a..262dc75d5be 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p6440/gpio.c
@@ -161,12 +161,15 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
         }, {
                 .cfg_eint       = 0,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         }, {
                 .cfg_eint       = 2,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         }, {
                 .cfg_eint       = 3,
                 .set_config     = s3c_gpio_setcfg_s3c24xx,
+                .get_config     = s3c_gpio_getcfg_s3c24xx,
         },
 };
 
@@ -279,6 +282,8 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
         for (; nr_chips > 0; nr_chips--, chipcfg++) {
                 if (!chipcfg->set_config)
                         chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
+                if (!chipcfg->get_config)
+                        chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
                 if (!chipcfg->set_pull)
                         chipcfg->set_pull       = s3c_gpio_setpull_updown;
                 if (!chipcfg->get_pull)
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p6440/include/mach/dma.h
new file mode 100644
index 00000000000..81209eb1409
--- /dev/null
+++ b/arch/arm/mach-s5p6440/include/mach/dma.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics Co. Ltd.
+ *      Jaswinder Singh <jassi.brar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* This platform uses the common S3C DMA API driver for PL330 */
+#include <plat/s3c-dma-pl330.h>
+
+#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
index 8924e5a4d6a..72aedadd412 100644
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ b/arch/arm/mach-s5p6440/include/mach/map.h
@@ -29,6 +29,8 @@
 #define S5P6440_PA_VIC0         (0xE4000000)
 #define S5P_PA_VIC0             S5P6440_PA_VIC0
 
+#define S5P6440_PA_PDMA         0xE9000000
+
 #define S5P6440_PA_VIC1         (0xE4100000)
 #define S5P_PA_VIC1             S5P6440_PA_VIC1
 
@@ -61,6 +63,12 @@
 #define S5P6440_PA_SDRAM        (0x20000000)
 #define S5P_PA_SDRAM            S5P6440_PA_SDRAM
 
+/* I2S */
+#define S5P6440_PA_I2S          0xF2000000
+
+/* PCM */
+#define S5P6440_PA_PCM          0xF2100000
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART             S5P6440_PA_UART
 #define S3C_PA_IIC              S5P6440_PA_IIC0
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
index c4bb7c55547..6a2a02fdf12 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
@@ -1,11 +1,14 @@
 /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
  *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Copyright 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
  *
  * S5P6440 - pwm clock and timer support
  *
@@ -14,16 +17,19 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __ASM_ARCH_PWMCLK_H
+#define __ASM_ARCH_PWMCLK_H __FILE__
+
 /**
  * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @cfg: The timer TCFG1 register bits shifted down to 0.
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
  *
  * Return true if the given configuration from TCFG1 is a TCLK instead
  * any of the TDIV clocks.
  */
 static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
 {
-        return tcfg == S3C2410_TCFG1_MUX_TCLK;
+        return 0;
 }
 
 /**
@@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
  */
 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
 {
-        return 1 << (1 + tcfg1);
+        return 1 << tcfg1;
 }
 
 /**
@@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
  */
 static inline unsigned int pwm_tdiv_has_div1(void)
 {
-        return 0;
+        return 1;
 }
 
 /**
@@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
  */
 static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
 {
-        return ilog2(div) - 1;
+        return ilog2(div);
 }
 
-#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
+#define S3C_TCFG1_MUX_TCLK 0
+
+#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c
index 3ae88f2c7c7..d7fede971ca 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p6440/mach-smdk6440.c
@@ -84,6 +84,7 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
 };
 
 static struct platform_device *smdk6440_devices[] __initdata = {
+        &s5p6440_device_iis,
 };
 
 static void __init smdk6440_map_io(void)
diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p6440/setup-i2c0.c
new file mode 100644
index 00000000000..69e8a664aed
--- /dev/null
+++ b/arch/arm/mach-s5p6440/setup-i2c0.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5p6440/setup-i2c0.c
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * I2C0 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <plat/iic.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        /* Will be populated later */
+}