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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-s3c64xx
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/cpu.c167
-rw-r--r--arch/arm/mach-s3c64xx/dev-onenand1.c53
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c179
-rw-r--r--arch/arm/mach-s3c64xx/gpiolib.c290
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/entry-macro.S18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/io.h18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/memory.h20
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pll.h45
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pwm-clock.h56
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/s3c6400.h36
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/s3c6410.h29
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/spi-clocks.h18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/system.h30
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/vmalloc.h20
-rw-r--r--arch/arm/mach-s3c64xx/irq-eint.c213
-rw-r--r--arch/arm/mach-s3c64xx/irq.c72
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci.c72
18 files changed, 1343 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
new file mode 100644
index 00000000000..374e45e566b
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -0,0 +1,167 @@
1/* linux/arch/arm/plat-s3c64xx/cpu.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU Support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23
24#include <mach/hardware.h>
25#include <mach/map.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <plat/regs-serial.h>
31
32#include <plat/cpu.h>
33#include <plat/devs.h>
34#include <plat/clock.h>
35
36#include <mach/s3c6400.h>
37#include <mach/s3c6410.h>
38
39/* table of supported CPUs */
40
41static const char name_s3c6400[] = "S3C6400";
42static const char name_s3c6410[] = "S3C6410";
43
44static struct cpu_table cpu_ids[] __initdata = {
45 {
46 .idcode = 0x36400000,
47 .idmask = 0xfffff000,
48 .map_io = s3c6400_map_io,
49 .init_clocks = s3c6400_init_clocks,
50 .init_uarts = s3c6400_init_uarts,
51 .init = s3c6400_init,
52 .name = name_s3c6400,
53 }, {
54 .idcode = 0x36410100,
55 .idmask = 0xffffff00,
56 .map_io = s3c6410_map_io,
57 .init_clocks = s3c6410_init_clocks,
58 .init_uarts = s3c6410_init_uarts,
59 .init = s3c6410_init,
60 .name = name_s3c6410,
61 },
62};
63
64/* minimal IO mapping */
65
66/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
67#define UART_OFFS (S3C_PA_UART & 0xfffff)
68
69static struct map_desc s3c_iodesc[] __initdata = {
70 {
71 .virtual = (unsigned long)S3C_VA_SYS,
72 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
76 .virtual = (unsigned long)S3C_VA_MEM,
77 .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
78 .length = SZ_4K,
79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
82 .pfn = __phys_to_pfn(S3C_PA_UART),
83 .length = SZ_4K,
84 .type = MT_DEVICE,
85 }, {
86 .virtual = (unsigned long)VA_VIC0,
87 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
88 .length = SZ_16K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (unsigned long)VA_VIC1,
92 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
93 .length = SZ_16K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = (unsigned long)S3C_VA_TIMER,
97 .pfn = __phys_to_pfn(S3C_PA_TIMER),
98 .length = SZ_16K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = (unsigned long)S3C64XX_VA_GPIO,
102 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
103 .length = SZ_4K,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (unsigned long)S3C64XX_VA_MODEM,
107 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
108 .length = SZ_4K,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (unsigned long)S3C_VA_WATCHDOG,
112 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
113 .length = SZ_4K,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
117 .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
118 .length = SZ_1K,
119 .type = MT_DEVICE,
120 },
121};
122
123
124struct sysdev_class s3c64xx_sysclass = {
125 .name = "s3c64xx-core",
126};
127
128static struct sys_device s3c64xx_sysdev = {
129 .cls = &s3c64xx_sysclass,
130};
131
132/* uart registration process */
133
134void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
135{
136 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
137}
138
139/* read cpu identification code */
140
141void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
142{
143 unsigned long idcode;
144
145 /* initialise the io descriptors we need for initialisation */
146 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
147 iotable_init(mach_desc, size);
148
149 idcode = __raw_readl(S3C_VA_SYS + 0x118);
150 if (!idcode) {
151 /* S3C6400 has the ID register in a different place,
152 * and needs a write before it can be read. */
153
154 __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
155 idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
156 }
157
158 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
159}
160
161static __init int s3c64xx_sysdev_init(void)
162{
163 sysdev_class_register(&s3c64xx_sysclass);
164 return sysdev_register(&s3c64xx_sysdev);
165}
166
167core_initcall(s3c64xx_sysdev_init);
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c
new file mode 100644
index 00000000000..999f9e17a1e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/dev-onenand1.c
@@ -0,0 +1,53 @@
1/*
2 * linux/arch/arm/mach-s3c64xx/dev-onenand1.c
3 *
4 * Copyright (c) 2008-2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * S3C64XX series device definition for OneNAND devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/onenand.h>
18
19#include <mach/irqs.h>
20#include <mach/map.h>
21
22#include <plat/devs.h>
23
24static struct resource s3c64xx_onenand1_resources[] = {
25 [0] = {
26 .start = S3C64XX_PA_ONENAND1,
27 .end = S3C64XX_PA_ONENAND1 + 0x400 - 1,
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .start = S3C64XX_PA_ONENAND1_BUF,
32 .end = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 [2] = {
36 .start = IRQ_ONENAND1,
37 .end = IRQ_ONENAND1,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42struct platform_device s3c64xx_device_onenand1 = {
43 .name = "samsung-onenand",
44 .id = 1,
45 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
46 .resource = s3c64xx_onenand1_resources,
47};
48
49void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
50{
51 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
52 &s3c64xx_device_onenand1);
53}
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
new file mode 100644
index 00000000000..5e6b42089eb
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -0,0 +1,179 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/gpio.h>
16
17#include <mach/dma.h>
18#include <mach/map.h>
19#include <mach/spi-clocks.h>
20#include <mach/irqs.h>
21
22#include <plat/s3c64xx-spi.h>
23#include <plat/gpio-cfg.h>
24#include <plat/devs.h>
25
26static char *spi_src_clks[] = {
27 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
28 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
29 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
30};
31
32/* SPI Controller platform_devices */
33
34/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
35 * The emulated CS is toggled by board specific mechanism, as it can
36 * be either some immediate GPIO or some signal out of some other
37 * chip in between ... or some yet another way.
38 * We simply do not assume anything about CS.
39 */
40static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
41{
42 unsigned int base;
43
44 switch (pdev->id) {
45 case 0:
46 base = S3C64XX_GPC(0);
47 break;
48
49 case 1:
50 base = S3C64XX_GPC(4);
51 break;
52
53 default:
54 dev_err(&pdev->dev, "Invalid SPI Controller number!");
55 return -EINVAL;
56 }
57
58 s3c_gpio_cfgall_range(base, 3,
59 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
60
61 return 0;
62}
63
64static struct resource s3c64xx_spi0_resource[] = {
65 [0] = {
66 .start = S3C64XX_PA_SPI0,
67 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = DMACH_SPI0_TX,
72 .end = DMACH_SPI0_TX,
73 .flags = IORESOURCE_DMA,
74 },
75 [2] = {
76 .start = DMACH_SPI0_RX,
77 .end = DMACH_SPI0_RX,
78 .flags = IORESOURCE_DMA,
79 },
80 [3] = {
81 .start = IRQ_SPI0,
82 .end = IRQ_SPI0,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
88 .cfg_gpio = s3c64xx_spi_cfg_gpio,
89 .fifo_lvl_mask = 0x7f,
90 .rx_lvl_offset = 13,
91 .tx_st_done = 21,
92};
93
94static u64 spi_dmamask = DMA_BIT_MASK(32);
95
96struct platform_device s3c64xx_device_spi0 = {
97 .name = "s3c64xx-spi",
98 .id = 0,
99 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
100 .resource = s3c64xx_spi0_resource,
101 .dev = {
102 .dma_mask = &spi_dmamask,
103 .coherent_dma_mask = DMA_BIT_MASK(32),
104 .platform_data = &s3c64xx_spi0_pdata,
105 },
106};
107EXPORT_SYMBOL(s3c64xx_device_spi0);
108
109static struct resource s3c64xx_spi1_resource[] = {
110 [0] = {
111 .start = S3C64XX_PA_SPI1,
112 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
113 .flags = IORESOURCE_MEM,
114 },
115 [1] = {
116 .start = DMACH_SPI1_TX,
117 .end = DMACH_SPI1_TX,
118 .flags = IORESOURCE_DMA,
119 },
120 [2] = {
121 .start = DMACH_SPI1_RX,
122 .end = DMACH_SPI1_RX,
123 .flags = IORESOURCE_DMA,
124 },
125 [3] = {
126 .start = IRQ_SPI1,
127 .end = IRQ_SPI1,
128 .flags = IORESOURCE_IRQ,
129 },
130};
131
132static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
133 .cfg_gpio = s3c64xx_spi_cfg_gpio,
134 .fifo_lvl_mask = 0x7f,
135 .rx_lvl_offset = 13,
136 .tx_st_done = 21,
137};
138
139struct platform_device s3c64xx_device_spi1 = {
140 .name = "s3c64xx-spi",
141 .id = 1,
142 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
143 .resource = s3c64xx_spi1_resource,
144 .dev = {
145 .dma_mask = &spi_dmamask,
146 .coherent_dma_mask = DMA_BIT_MASK(32),
147 .platform_data = &s3c64xx_spi1_pdata,
148 },
149};
150EXPORT_SYMBOL(s3c64xx_device_spi1);
151
152void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
153{
154 struct s3c64xx_spi_info *pd;
155
156 /* Reject invalid configuration */
157 if (!num_cs || src_clk_nr < 0
158 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
159 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
160 return;
161 }
162
163 switch (cntrlr) {
164 case 0:
165 pd = &s3c64xx_spi0_pdata;
166 break;
167 case 1:
168 pd = &s3c64xx_spi1_pdata;
169 break;
170 default:
171 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
172 __func__, cntrlr);
173 return;
174 }
175
176 pd->num_cs = num_cs;
177 pd->src_clk_nr = src_clk_nr;
178 pd->src_clk_name = spi_src_clks[src_clk_nr];
179}
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
new file mode 100644
index 00000000000..92b09085caa
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -0,0 +1,290 @@
1/* arch/arm/plat-s3c64xx/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIOlib support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19
20#include <mach/map.h>
21
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25#include <mach/regs-gpio.h>
26
27/* GPIO bank summary:
28 *
29 * Bank GPIOs Style SlpCon ExtInt Group
30 * A 8 4Bit Yes 1
31 * B 7 4Bit Yes 1
32 * C 8 4Bit Yes 2
33 * D 5 4Bit Yes 3
34 * E 5 4Bit Yes None
35 * F 16 2Bit Yes 4 [1]
36 * G 7 4Bit Yes 5
37 * H 10 4Bit[2] Yes 6
38 * I 16 2Bit Yes None
39 * J 12 2Bit Yes None
40 * K 16 4Bit[2] No None
41 * L 15 4Bit[2] No None
42 * M 6 4Bit No IRQ_EINT
43 * N 16 2Bit No IRQ_EINT
44 * O 16 2Bit Yes 7
45 * P 15 2Bit Yes 8
46 * Q 9 2Bit Yes 9
47 *
48 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
49 * [2] BANK has two control registers, GPxCON0 and GPxCON1
50 */
51
52static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
53 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
54 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
55 .set_pull = s3c_gpio_setpull_updown,
56 .get_pull = s3c_gpio_getpull_updown,
57};
58
59static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
60 .cfg_eint = 7,
61 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
62 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
63 .set_pull = s3c_gpio_setpull_updown,
64 .get_pull = s3c_gpio_getpull_updown,
65};
66
67static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
68 .cfg_eint = 3,
69 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
70 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
71 .set_pull = s3c_gpio_setpull_updown,
72 .get_pull = s3c_gpio_getpull_updown,
73};
74
75static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
76{
77 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
78}
79
80static struct s3c_gpio_chip gpio_4bit[] = {
81 {
82 .base = S3C64XX_GPA_BASE,
83 .config = &gpio_4bit_cfg_eint0111,
84 .chip = {
85 .base = S3C64XX_GPA(0),
86 .ngpio = S3C64XX_GPIO_A_NR,
87 .label = "GPA",
88 },
89 }, {
90 .base = S3C64XX_GPB_BASE,
91 .config = &gpio_4bit_cfg_eint0111,
92 .chip = {
93 .base = S3C64XX_GPB(0),
94 .ngpio = S3C64XX_GPIO_B_NR,
95 .label = "GPB",
96 },
97 }, {
98 .base = S3C64XX_GPC_BASE,
99 .config = &gpio_4bit_cfg_eint0111,
100 .chip = {
101 .base = S3C64XX_GPC(0),
102 .ngpio = S3C64XX_GPIO_C_NR,
103 .label = "GPC",
104 },
105 }, {
106 .base = S3C64XX_GPD_BASE,
107 .config = &gpio_4bit_cfg_eint0111,
108 .chip = {
109 .base = S3C64XX_GPD(0),
110 .ngpio = S3C64XX_GPIO_D_NR,
111 .label = "GPD",
112 },
113 }, {
114 .base = S3C64XX_GPE_BASE,
115 .config = &gpio_4bit_cfg_noint,
116 .chip = {
117 .base = S3C64XX_GPE(0),
118 .ngpio = S3C64XX_GPIO_E_NR,
119 .label = "GPE",
120 },
121 }, {
122 .base = S3C64XX_GPG_BASE,
123 .config = &gpio_4bit_cfg_eint0111,
124 .chip = {
125 .base = S3C64XX_GPG(0),
126 .ngpio = S3C64XX_GPIO_G_NR,
127 .label = "GPG",
128 },
129 }, {
130 .base = S3C64XX_GPM_BASE,
131 .config = &gpio_4bit_cfg_eint0011,
132 .chip = {
133 .base = S3C64XX_GPM(0),
134 .ngpio = S3C64XX_GPIO_M_NR,
135 .label = "GPM",
136 .to_irq = s3c64xx_gpio2int_gpm,
137 },
138 },
139};
140
141static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
142{
143 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
144}
145
146static struct s3c_gpio_chip gpio_4bit2[] = {
147 {
148 .base = S3C64XX_GPH_BASE + 0x4,
149 .config = &gpio_4bit_cfg_eint0111,
150 .chip = {
151 .base = S3C64XX_GPH(0),
152 .ngpio = S3C64XX_GPIO_H_NR,
153 .label = "GPH",
154 },
155 }, {
156 .base = S3C64XX_GPK_BASE + 0x4,
157 .config = &gpio_4bit_cfg_noint,
158 .chip = {
159 .base = S3C64XX_GPK(0),
160 .ngpio = S3C64XX_GPIO_K_NR,
161 .label = "GPK",
162 },
163 }, {
164 .base = S3C64XX_GPL_BASE + 0x4,
165 .config = &gpio_4bit_cfg_eint0011,
166 .chip = {
167 .base = S3C64XX_GPL(0),
168 .ngpio = S3C64XX_GPIO_L_NR,
169 .label = "GPL",
170 .to_irq = s3c64xx_gpio2int_gpl,
171 },
172 },
173};
174
175static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
176 .set_config = s3c_gpio_setcfg_s3c24xx,
177 .get_config = s3c_gpio_getcfg_s3c24xx,
178 .set_pull = s3c_gpio_setpull_updown,
179 .get_pull = s3c_gpio_getpull_updown,
180};
181
182static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
183 .cfg_eint = 2,
184 .set_config = s3c_gpio_setcfg_s3c24xx,
185 .get_config = s3c_gpio_getcfg_s3c24xx,
186 .set_pull = s3c_gpio_setpull_updown,
187 .get_pull = s3c_gpio_getpull_updown,
188};
189
190static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
191 .cfg_eint = 3,
192 .set_config = s3c_gpio_setcfg_s3c24xx,
193 .get_config = s3c_gpio_getcfg_s3c24xx,
194 .set_pull = s3c_gpio_setpull_updown,
195 .get_pull = s3c_gpio_getpull_updown,
196};
197
198static struct s3c_gpio_chip gpio_2bit[] = {
199 {
200 .base = S3C64XX_GPF_BASE,
201 .config = &gpio_2bit_cfg_eint11,
202 .chip = {
203 .base = S3C64XX_GPF(0),
204 .ngpio = S3C64XX_GPIO_F_NR,
205 .label = "GPF",
206 },
207 }, {
208 .base = S3C64XX_GPI_BASE,
209 .config = &gpio_2bit_cfg_noint,
210 .chip = {
211 .base = S3C64XX_GPI(0),
212 .ngpio = S3C64XX_GPIO_I_NR,
213 .label = "GPI",
214 },
215 }, {
216 .base = S3C64XX_GPJ_BASE,
217 .config = &gpio_2bit_cfg_noint,
218 .chip = {
219 .base = S3C64XX_GPJ(0),
220 .ngpio = S3C64XX_GPIO_J_NR,
221 .label = "GPJ",
222 },
223 }, {
224 .base = S3C64XX_GPN_BASE,
225 .irq_base = IRQ_EINT(0),
226 .config = &gpio_2bit_cfg_eint10,
227 .chip = {
228 .base = S3C64XX_GPN(0),
229 .ngpio = S3C64XX_GPIO_N_NR,
230 .label = "GPN",
231 .to_irq = samsung_gpiolib_to_irq,
232 },
233 }, {
234 .base = S3C64XX_GPO_BASE,
235 .config = &gpio_2bit_cfg_eint11,
236 .chip = {
237 .base = S3C64XX_GPO(0),
238 .ngpio = S3C64XX_GPIO_O_NR,
239 .label = "GPO",
240 },
241 }, {
242 .base = S3C64XX_GPP_BASE,
243 .config = &gpio_2bit_cfg_eint11,
244 .chip = {
245 .base = S3C64XX_GPP(0),
246 .ngpio = S3C64XX_GPIO_P_NR,
247 .label = "GPP",
248 },
249 }, {
250 .base = S3C64XX_GPQ_BASE,
251 .config = &gpio_2bit_cfg_eint11,
252 .chip = {
253 .base = S3C64XX_GPQ(0),
254 .ngpio = S3C64XX_GPIO_Q_NR,
255 .label = "GPQ",
256 },
257 },
258};
259
260static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
261{
262 chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
263}
264
265static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
266 int nr_chips,
267 void (*fn)(struct s3c_gpio_chip *))
268{
269 for (; nr_chips > 0; nr_chips--, chips++) {
270 if (fn)
271 (fn)(chips);
272 s3c_gpiolib_add(chips);
273 }
274}
275
276static __init int s3c64xx_gpiolib_init(void)
277{
278 s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
279 samsung_gpiolib_add_4bit);
280
281 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
282 samsung_gpiolib_add_4bit2);
283
284 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
285 s3c64xx_gpiolib_add_2bit);
286
287 return 0;
288}
289
290core_initcall(s3c64xx_gpiolib_init);
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 00000000000..7dffa83d23f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
new file mode 100644
index 00000000000..dd362604dcc
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * Low-level IRQ helper macros for the Samsung S3C64XX series
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13*/
14
15#include <mach/map.h>
16#include <mach/irqs.h>
17
18#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
new file mode 100644
index 00000000000..de5716dbbd6
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/io.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c64xxinclude/mach/io.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben-linux@fluff.org>
5 *
6 * Default IO routines for S3C64XX based
7 */
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12/* No current ISA/PCI bus support. */
13#define __io(a) __typesafe_io(a)
14#define __mem_pci(a) (a)
15
16#define IO_SPACE_LIMIT (0xFFFFFFFF)
17
18#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
new file mode 100644
index 00000000000..4760cdae1eb
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/memory.h
@@ -0,0 +1,20 @@
1/* arch/arm/mach-s3c6400/include/mach/memory.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x50000000)
17
18#define CONSISTENT_DMA_SIZE SZ_8M
19
20#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
new file mode 100644
index 00000000000..5ef0bb698ee
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pll.h
@@ -0,0 +1,45 @@
1/* arch/arm/plat-s3c64xx/include/plat/pll.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX PLL code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
16#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
17#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
18#define S3C6400_PLL_MDIV_SHIFT (16)
19#define S3C6400_PLL_PDIV_SHIFT (8)
20#define S3C6400_PLL_SDIV_SHIFT (0)
21
22#include <asm/div64.h>
23#include <plat/pll6553x.h>
24
25static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
26 u32 pllcon)
27{
28 u32 mdiv, pdiv, sdiv;
29 u64 fvco = baseclk;
30
31 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
32 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
33 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
34
35 fvco *= mdiv;
36 do_div(fvco, (pdiv << sdiv));
37
38 return (unsigned long)fvco;
39}
40
41static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
42{
43 return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
44 __raw_readl(S3C_EPLL_CON1));
45}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
new file mode 100644
index 00000000000..b25bedee0d5
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64xx - pwm clock and timer support
9 */
10
11/**
12 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
13 * @tcfg: The timer TCFG1 register bits shifted down to 0.
14 *
15 * Return true if the given configuration from TCFG1 is a TCLK instead
16 * any of the TDIV clocks.
17 */
18static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
19{
20 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
21}
22
23/**
24 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
25 * @tcfg1: The tcfg1 setting, shifted down.
26 *
27 * Get the divisor value for the given tcfg1 setting. We assume the
28 * caller has already checked to see if this is not a TCLK source.
29 */
30static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
31{
32 return 1 << tcfg1;
33}
34
35/**
36 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
37 *
38 * Return true if we have a /1 in the tdiv setting.
39 */
40static inline unsigned int pwm_tdiv_has_div1(void)
41{
42 return 1;
43}
44
45/**
46 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
47 * @div: The divisor to calculate the bit information for.
48 *
49 * Turn a divisor into the necessary bit field for TCFG1.
50 */
51static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
52{
53 return ilog2(div);
54}
55
56#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
new file mode 100644
index 00000000000..f86958d0535
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
@@ -0,0 +1,36 @@
1/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6400 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S3C6400 related SoCs */
16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_setup_clocks(void);
19
20extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
21
22#ifdef CONFIG_CPU_S3C6400
23
24extern int s3c6400_init(void);
25extern void s3c6400_init_irq(void);
26extern void s3c6400_map_io(void);
27extern void s3c6400_init_clocks(int xtal);
28
29#define s3c6400_init_uarts s3c6400_common_init_uarts
30
31#else
32#define s3c6400_init_clocks NULL
33#define s3c6400_init_uarts NULL
34#define s3c6400_map_io NULL
35#define s3c6400_init NULL
36#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
new file mode 100644
index 00000000000..24f1141ffcb
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
@@ -0,0 +1,29 @@
1/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6410 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifdef CONFIG_CPU_S3C6410
16
17extern int s3c6410_init(void);
18extern void s3c6410_init_irq(void);
19extern void s3c6410_map_io(void);
20extern void s3c6410_init_clocks(int xtal);
21
22#define s3c6410_init_uarts s3c6400_common_init_uarts
23
24#else
25#define s3c6410_init_clocks NULL
26#define s3c6410_init_uarts NULL
27#define s3c6410_map_io NULL
28#define s3c6410_init NULL
29#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
new file mode 100644
index 00000000000..9d0c43b4b68
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
@@ -0,0 +1,18 @@
1/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_CLKS_H
12#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
13
14#define S3C64XX_SPI_SRCCLK_PCLK 0
15#define S3C64XX_SPI_SRCCLK_SPIBUS 1
16#define S3C64XX_SPI_SRCCLK_48M 2
17
18#endif /* __S3C64XX_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
new file mode 100644
index 00000000000..2e58cb7a714
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
@@ -0,0 +1,30 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/system.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - system implementation
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__
13
14#include <plat/watchdog-reset.h>
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20
21static void arch_reset(char mode, const char *cmd)
22{
23 if (mode != 's')
24 arch_wdt_reset();
25
26 /* if all else fails, or mode was for soft, jump to 0 */
27 cpu_reset(0);
28}
29
30#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
new file mode 100644
index 00000000000..23f75e556a3
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/* arch/arm/mach-s3c64xx/include/mach/vmalloc.h
2 *
3 * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
4 *
5 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
6 * http://www.simtec.co.uk/products/SWLINUX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C6400 vmalloc definition
13*/
14
15#ifndef __ASM_ARCH_VMALLOC_H
16#define __ASM_ARCH_VMALLOC_H
17
18#define VMALLOC_END 0xF6000000UL
19
20#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
new file mode 100644
index 00000000000..4d203be1f4c
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/irq-eint.c
@@ -0,0 +1,213 @@
1/* arch/arm/plat-s3c64xx/irq-eint.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Interrupt handling for IRQ_EINT(x)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21
22#include <asm/hardware/vic.h>
23
24#include <plat/regs-irqtype.h>
25#include <mach/regs-gpio.h>
26#include <plat/gpio-cfg.h>
27
28#include <mach/map.h>
29#include <plat/cpu.h>
30#include <plat/pm.h>
31
32#define eint_offset(irq) ((irq) - IRQ_EINT(0))
33#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
34
35static inline void s3c_irq_eint_mask(struct irq_data *data)
36{
37 u32 mask;
38
39 mask = __raw_readl(S3C64XX_EINT0MASK);
40 mask |= (u32)data->chip_data;
41 __raw_writel(mask, S3C64XX_EINT0MASK);
42}
43
44static void s3c_irq_eint_unmask(struct irq_data *data)
45{
46 u32 mask;
47
48 mask = __raw_readl(S3C64XX_EINT0MASK);
49 mask &= ~((u32)data->chip_data);
50 __raw_writel(mask, S3C64XX_EINT0MASK);
51}
52
53static inline void s3c_irq_eint_ack(struct irq_data *data)
54{
55 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
56}
57
58static void s3c_irq_eint_maskack(struct irq_data *data)
59{
60 /* compiler should in-line these */
61 s3c_irq_eint_mask(data);
62 s3c_irq_eint_ack(data);
63}
64
65static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
66{
67 int offs = eint_offset(data->irq);
68 int pin, pin_val;
69 int shift;
70 u32 ctrl, mask;
71 u32 newvalue = 0;
72 void __iomem *reg;
73
74 if (offs > 27)
75 return -EINVAL;
76
77 if (offs <= 15)
78 reg = S3C64XX_EINT0CON0;
79 else
80 reg = S3C64XX_EINT0CON1;
81
82 switch (type) {
83 case IRQ_TYPE_NONE:
84 printk(KERN_WARNING "No edge setting!\n");
85 break;
86
87 case IRQ_TYPE_EDGE_RISING:
88 newvalue = S3C2410_EXTINT_RISEEDGE;
89 break;
90
91 case IRQ_TYPE_EDGE_FALLING:
92 newvalue = S3C2410_EXTINT_FALLEDGE;
93 break;
94
95 case IRQ_TYPE_EDGE_BOTH:
96 newvalue = S3C2410_EXTINT_BOTHEDGE;
97 break;
98
99 case IRQ_TYPE_LEVEL_LOW:
100 newvalue = S3C2410_EXTINT_LOWLEV;
101 break;
102
103 case IRQ_TYPE_LEVEL_HIGH:
104 newvalue = S3C2410_EXTINT_HILEV;
105 break;
106
107 default:
108 printk(KERN_ERR "No such irq type %d", type);
109 return -1;
110 }
111
112 if (offs <= 15)
113 shift = (offs / 2) * 4;
114 else
115 shift = ((offs - 16) / 2) * 4;
116 mask = 0x7 << shift;
117
118 ctrl = __raw_readl(reg);
119 ctrl &= ~mask;
120 ctrl |= newvalue << shift;
121 __raw_writel(ctrl, reg);
122
123 /* set the GPIO pin appropriately */
124
125 if (offs < 16) {
126 pin = S3C64XX_GPN(offs);
127 pin_val = S3C_GPIO_SFN(2);
128 } else if (offs < 23) {
129 pin = S3C64XX_GPL(offs + 8 - 16);
130 pin_val = S3C_GPIO_SFN(3);
131 } else {
132 pin = S3C64XX_GPM(offs - 23);
133 pin_val = S3C_GPIO_SFN(3);
134 }
135
136 s3c_gpio_cfgpin(pin, pin_val);
137
138 return 0;
139}
140
141static struct irq_chip s3c_irq_eint = {
142 .name = "s3c-eint",
143 .irq_mask = s3c_irq_eint_mask,
144 .irq_unmask = s3c_irq_eint_unmask,
145 .irq_mask_ack = s3c_irq_eint_maskack,
146 .irq_ack = s3c_irq_eint_ack,
147 .irq_set_type = s3c_irq_eint_set_type,
148 .irq_set_wake = s3c_irqext_wake,
149};
150
151/* s3c_irq_demux_eint
152 *
153 * This function demuxes the IRQ from the group0 external interrupts,
154 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
155 * the specific handlers s3c_irq_demux_eintX_Y.
156 */
157static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
158{
159 u32 status = __raw_readl(S3C64XX_EINT0PEND);
160 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
161 unsigned int irq;
162
163 status &= ~mask;
164 status >>= start;
165 status &= (1 << (end - start + 1)) - 1;
166
167 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
168 if (status & 1)
169 generic_handle_irq(irq);
170
171 status >>= 1;
172 }
173}
174
175static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
176{
177 s3c_irq_demux_eint(0, 3);
178}
179
180static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
181{
182 s3c_irq_demux_eint(4, 11);
183}
184
185static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
186{
187 s3c_irq_demux_eint(12, 19);
188}
189
190static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
191{
192 s3c_irq_demux_eint(20, 27);
193}
194
195static int __init s3c64xx_init_irq_eint(void)
196{
197 int irq;
198
199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
200 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
201 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
202 set_irq_flags(irq, IRQF_VALID);
203 }
204
205 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
206 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
207 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
208 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
209
210 return 0;
211}
212
213arch_initcall(s3c64xx_init_irq_eint);
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
new file mode 100644
index 00000000000..75d9a0e4919
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -0,0 +1,72 @@
1/* arch/arm/plat-s3c64xx/irq.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Interrupt handling
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/serial_core.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20
21#include <asm/hardware/vic.h>
22
23#include <mach/map.h>
24#include <plat/irq-vic-timer.h>
25#include <plat/irq-uart.h>
26#include <plat/cpu.h>
27
28static struct s3c_uart_irq uart_irqs[] = {
29 [0] = {
30 .regs = S3C_VA_UART0,
31 .base_irq = IRQ_S3CUART_BASE0,
32 .parent_irq = IRQ_UART0,
33 },
34 [1] = {
35 .regs = S3C_VA_UART1,
36 .base_irq = IRQ_S3CUART_BASE1,
37 .parent_irq = IRQ_UART1,
38 },
39 [2] = {
40 .regs = S3C_VA_UART2,
41 .base_irq = IRQ_S3CUART_BASE2,
42 .parent_irq = IRQ_UART2,
43 },
44 [3] = {
45 .regs = S3C_VA_UART3,
46 .base_irq = IRQ_S3CUART_BASE3,
47 .parent_irq = IRQ_UART3,
48 },
49};
50
51/* setup the sources the vic should advertise resume for, even though it
52 * is not doing the wake (set_irq_wake needs to be valid) */
53#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
54#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
55 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
56 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
57 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
58 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
59
60void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
61{
62 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
63
64 /* initialise the pair of VICs */
65 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
66 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
67
68 /* add the timer sub-irqs */
69 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
70
71 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
72}
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
new file mode 100644
index 00000000000..f344a222bc8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-sdhci.c
@@ -0,0 +1,72 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c64xx_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "mmc_bus",
33 /* [3] = "48m", - note not successfully used yet */
34};
35
36void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
46 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
47 S3C_SDHCI_CTRL2_ENFBCLKRX |
48 S3C_SDHCI_CTRL2_DFCNT_NONE |
49 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
50
51 if (ios->clock < 25 * 1000000)
52 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
53 S3C_SDHCI_CTRL3_FCSEL2 |
54 S3C_SDHCI_CTRL3_FCSEL1 |
55 S3C_SDHCI_CTRL3_FCSEL0);
56 else
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
58
59 pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
60 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
61 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
62}
63
64void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
65 void __iomem *r,
66 struct mmc_ios *ios,
67 struct mmc_card *card)
68{
69 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
70
71 s3c6400_setup_sdhci_cfg_card(dev, r, ios, card);
72}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-04 15:28:00 -0400