aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c2443
diff options
context:
space:
mode:
authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-s3c2443
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-s3c2443')
-rw-r--r--arch/arm/mach-s3c2443/Kconfig33
-rw-r--r--arch/arm/mach-s3c2443/Makefile20
-rw-r--r--arch/arm/mach-s3c2443/clock.c368
-rw-r--r--arch/arm/mach-s3c2443/dma.c180
-rw-r--r--arch/arm/mach-s3c2443/irq.c278
-rw-r--r--arch/arm/mach-s3c2443/mach-smdk2443.c148
-rw-r--r--arch/arm/mach-s3c2443/s3c2443.c110
7 files changed, 1137 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
new file mode 100644
index 00000000000..d8eb86823df
--- /dev/null
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -0,0 +1,33 @@
1# Copyright 2007 Simtec Electronics
2#
3# Licensed under GPLv2
4
5config CPU_S3C2443
6 bool
7 depends on ARCH_S3C2410
8 select CPU_ARM920T
9 select S3C2443_DMA if S3C2410_DMA
10 select CPU_LLSERIAL_S3C2440
11 select SAMSUNG_CLKSRC
12 select S3C2443_CLOCK
13 select S3C_GPIO_PULL_S3C2443
14 help
15 Support for the S3C2443 SoC from the S3C24XX line
16
17config S3C2443_DMA
18 bool
19 depends on CPU_S3C2443
20 help
21 Internal config node for S3C2443 DMA support
22
23menu "S3C2443 Machines"
24
25config MACH_SMDK2443
26 bool "SMDK2443"
27 select CPU_S3C2443
28 select MACH_SMDK
29 select S3C_DEV_HSMMC1
30 help
31 Say Y here if you are using an SMDK2443
32
33endmenu
diff --git a/arch/arm/mach-s3c2443/Makefile b/arch/arm/mach-s3c2443/Makefile
new file mode 100644
index 00000000000..d1843c9eb8b
--- /dev/null
+++ b/arch/arm/mach-s3c2443/Makefile
@@ -0,0 +1,20 @@
1# arch/arm/mach-s3c2443/Makefile
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12obj-$(CONFIG_CPU_S3C2443) += s3c2443.o
13obj-$(CONFIG_CPU_S3C2443) += irq.o
14obj-$(CONFIG_CPU_S3C2443) += clock.o
15
16obj-$(CONFIG_S3C2443_DMA) += dma.o
17
18# Machine support
19
20obj-$(CONFIG_MACH_SMDK2443) += mach-smdk2443.o
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
new file mode 100644
index 00000000000..38058af4897
--- /dev/null
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -0,0 +1,368 @@
1/* linux/arch/arm/mach-s3c2443/clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/sysdev.h>
31#include <linux/clk.h>
32#include <linux/mutex.h>
33#include <linux/serial_core.h>
34#include <linux/io.h>
35
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39
40#include <mach/regs-s3c2443-clock.h>
41
42#include <plat/cpu-freq.h>
43
44#include <plat/s3c2443.h>
45#include <plat/clock.h>
46#include <plat/clock-clksrc.h>
47#include <plat/cpu.h>
48
49/* We currently have to assume that the system is running
50 * from the XTPll input, and that all ***REFCLKs are being
51 * fed from it, as we cannot read the state of OM[4] from
52 * software.
53 *
54 * It would be possible for each board initialisation to
55 * set the correct muxing at initialisation
56*/
57
58/* clock selections */
59
60static struct clk clk_i2s_ext = {
61 .name = "i2s-ext",
62};
63
64/* armdiv
65 *
66 * this clock is sourced from msysclk and can have a number of
67 * divider values applied to it to then be fed into armclk.
68*/
69
70/* armdiv divisor table */
71
72static unsigned int armdiv[16] = {
73 [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
74 [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
75 [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
76 [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
77 [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
78 [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
79 [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
80 [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
81};
82
83static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
84{
85 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
86
87 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
88}
89
90static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
91 unsigned long rate)
92{
93 unsigned long parent = clk_get_rate(clk->parent);
94 unsigned long calc;
95 unsigned best = 256; /* bigger than any value */
96 unsigned div;
97 int ptr;
98
99 for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
100 div = armdiv[ptr];
101 calc = parent / div;
102 if (calc <= rate && div < best)
103 best = div;
104 }
105
106 return parent / best;
107}
108
109static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
110{
111 unsigned long parent = clk_get_rate(clk->parent);
112 unsigned long calc;
113 unsigned div;
114 unsigned best = 256; /* bigger than any value */
115 int ptr;
116 int val = -1;
117
118 for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
119 div = armdiv[ptr];
120 calc = parent / div;
121 if (calc <= rate && div < best) {
122 best = div;
123 val = ptr;
124 }
125 }
126
127 if (val >= 0) {
128 unsigned long clkcon0;
129
130 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
131 clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
132 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
133 __raw_writel(clkcon0, S3C2443_CLKDIV0);
134 }
135
136 return (val == -1) ? -EINVAL : 0;
137}
138
139static struct clk clk_armdiv = {
140 .name = "armdiv",
141 .parent = &clk_msysclk.clk,
142 .ops = &(struct clk_ops) {
143 .round_rate = s3c2443_armclk_roundrate,
144 .set_rate = s3c2443_armclk_setrate,
145 },
146};
147
148/* armclk
149 *
150 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
151 */
152
153static struct clk *clk_arm_sources[] = {
154 [0] = &clk_armdiv,
155 [1] = &clk_h,
156};
157
158static struct clksrc_clk clk_arm = {
159 .clk = {
160 .name = "armclk",
161 },
162 .sources = &(struct clksrc_sources) {
163 .sources = clk_arm_sources,
164 .nr_sources = ARRAY_SIZE(clk_arm_sources),
165 },
166 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
167};
168
169/* hsspi
170 *
171 * high-speed spi clock, sourced from esysclk
172*/
173
174static struct clksrc_clk clk_hsspi = {
175 .clk = {
176 .name = "hsspi",
177 .parent = &clk_esysclk.clk,
178 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
179 .enable = s3c2443_clkcon_enable_s,
180 },
181 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
182};
183
184
185/* clk_hsmcc_div
186 *
187 * this clock is sourced from epll, and is fed through a divider,
188 * to a mux controlled by sclkcon where either it or a extclk can
189 * be fed to the hsmmc block
190*/
191
192static struct clksrc_clk clk_hsmmc_div = {
193 .clk = {
194 .name = "hsmmc-div",
195 .devname = "s3c-sdhci.1",
196 .parent = &clk_esysclk.clk,
197 },
198 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
199};
200
201static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
202{
203 unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
204
205 clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
206 S3C2443_SCLKCON_HSMMCCLK_EPLL);
207
208 if (parent == &clk_epll)
209 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
210 else if (parent == &clk_ext)
211 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
212 else
213 return -EINVAL;
214
215 if (clk->usage > 0) {
216 __raw_writel(clksrc, S3C2443_SCLKCON);
217 }
218
219 clk->parent = parent;
220 return 0;
221}
222
223static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
224{
225 return s3c2443_setparent_hsmmc(clk, clk->parent);
226}
227
228static struct clk clk_hsmmc = {
229 .name = "hsmmc-if",
230 .devname = "s3c-sdhci.1",
231 .parent = &clk_hsmmc_div.clk,
232 .enable = s3c2443_enable_hsmmc,
233 .ops = &(struct clk_ops) {
234 .set_parent = s3c2443_setparent_hsmmc,
235 },
236};
237
238/* i2s_eplldiv
239 *
240 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
241 * from the mux that comes after it (cannot merge into one single clock)
242*/
243
244static struct clksrc_clk clk_i2s_eplldiv = {
245 .clk = {
246 .name = "i2s-eplldiv",
247 .parent = &clk_esysclk.clk,
248 },
249 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
250};
251
252/* i2s-ref
253 *
254 * i2s bus reference clock, selectable from external, esysclk or epllref
255 *
256 * Note, this used to be two clocks, but was compressed into one.
257*/
258
259struct clk *clk_i2s_srclist[] = {
260 [0] = &clk_i2s_eplldiv.clk,
261 [1] = &clk_i2s_ext,
262 [2] = &clk_epllref.clk,
263 [3] = &clk_epllref.clk,
264};
265
266static struct clksrc_clk clk_i2s = {
267 .clk = {
268 .name = "i2s-if",
269 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
270 .enable = s3c2443_clkcon_enable_s,
271
272 },
273 .sources = &(struct clksrc_sources) {
274 .sources = clk_i2s_srclist,
275 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
276 },
277 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
278};
279
280/* standard clock definitions */
281
282static struct clk init_clocks_off[] = {
283 {
284 .name = "sdi",
285 .parent = &clk_p,
286 .enable = s3c2443_clkcon_enable_p,
287 .ctrlbit = S3C2443_PCLKCON_SDI,
288 }, {
289 .name = "iis",
290 .parent = &clk_p,
291 .enable = s3c2443_clkcon_enable_p,
292 .ctrlbit = S3C2443_PCLKCON_IIS,
293 }, {
294 .name = "spi",
295 .devname = "s3c2410-spi.0",
296 .parent = &clk_p,
297 .enable = s3c2443_clkcon_enable_p,
298 .ctrlbit = S3C2443_PCLKCON_SPI0,
299 }, {
300 .name = "spi",
301 .devname = "s3c2410-spi.1",
302 .parent = &clk_p,
303 .enable = s3c2443_clkcon_enable_p,
304 .ctrlbit = S3C2443_PCLKCON_SPI1,
305 }
306};
307
308static struct clk init_clocks[] = {
309};
310
311/* clocks to add straight away */
312
313static struct clksrc_clk *clksrcs[] __initdata = {
314 &clk_arm,
315 &clk_i2s_eplldiv,
316 &clk_i2s,
317 &clk_hsspi,
318 &clk_hsmmc_div,
319};
320
321static struct clk *clks[] __initdata = {
322 &clk_hsmmc,
323 &clk_armdiv,
324};
325
326void __init_or_cpufreq s3c2443_setup_clocks(void)
327{
328 s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
329}
330
331void __init s3c2443_init_clocks(int xtal)
332{
333 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
334 int ptr;
335
336 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
337 clk_epll.parent = &clk_epllref.clk;
338
339 s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
340
341 s3c2443_setup_clocks();
342
343 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
344
345 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
346 s3c_register_clksrc(clksrcs[ptr], 1);
347
348 /* register clocks from clock array */
349
350 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
351
352 /* We must be careful disabling the clocks we are not intending to
353 * be using at boot time, as subsystems such as the LCD which do
354 * their own DMA requests to the bus can cause the system to lockup
355 * if they where in the middle of requesting bus access.
356 *
357 * Disabling the LCD clock if the LCD is active is very dangerous,
358 * and therefore the bootloader should be careful to not enable
359 * the LCD clock if it is not needed.
360 */
361
362 /* install (and disable) the clocks we do not need immediately */
363
364 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
365 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
366
367 s3c_pwmclk_init();
368}
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
new file mode 100644
index 00000000000..3f658685ec1
--- /dev/null
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -0,0 +1,180 @@
1/* linux/arch/arm/mach-s3c2443/dma.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18#include <linux/serial_core.h>
19#include <linux/io.h>
20
21#include <mach/dma.h>
22
23#include <plat/dma-s3c24xx.h>
24#include <plat/cpu.h>
25
26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h>
34#include <plat/regs-spi.h>
35
36#define MAP(x) { \
37 [0] = (x) | DMA_CH_VALID, \
38 [1] = (x) | DMA_CH_VALID, \
39 [2] = (x) | DMA_CH_VALID, \
40 [3] = (x) | DMA_CH_VALID, \
41 [4] = (x) | DMA_CH_VALID, \
42 [5] = (x) | DMA_CH_VALID, \
43 }
44
45static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
46 [DMACH_XD0] = {
47 .name = "xdreq0",
48 .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
49 },
50 [DMACH_XD1] = {
51 .name = "xdreq1",
52 .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
53 },
54 [DMACH_SDI] = {
55 .name = "sdi",
56 .channels = MAP(S3C2443_DMAREQSEL_SDI),
57 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
58 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
59 },
60 [DMACH_SPI0] = {
61 .name = "spi0",
62 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
63 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
65 },
66 [DMACH_SPI1] = {
67 .name = "spi1",
68 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
69 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
70 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
71 },
72 [DMACH_UART0] = {
73 .name = "uart0",
74 .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
75 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
77 },
78 [DMACH_UART1] = {
79 .name = "uart1",
80 .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
81 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
83 },
84 [DMACH_UART2] = {
85 .name = "uart2",
86 .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
87 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
88 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
89 },
90 [DMACH_UART3] = {
91 .name = "uart3",
92 .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
93 .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
94 .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
95 },
96 [DMACH_UART0_SRC2] = {
97 .name = "uart0",
98 .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
99 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
100 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
101 },
102 [DMACH_UART1_SRC2] = {
103 .name = "uart1",
104 .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
105 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
106 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
107 },
108 [DMACH_UART2_SRC2] = {
109 .name = "uart2",
110 .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
111 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
112 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
113 },
114 [DMACH_UART3_SRC2] = {
115 .name = "uart3",
116 .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
117 .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
118 .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
119 },
120 [DMACH_TIMER] = {
121 .name = "timer",
122 .channels = MAP(S3C2443_DMAREQSEL_TIMER),
123 },
124 [DMACH_I2S_IN] = {
125 .name = "i2s-sdi",
126 .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
127 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
128 },
129 [DMACH_I2S_OUT] = {
130 .name = "i2s-sdo",
131 .channels = MAP(S3C2443_DMAREQSEL_I2STX),
132 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
133 },
134 [DMACH_PCM_IN] = {
135 .name = "pcm-in",
136 .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
137 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
138 },
139 [DMACH_PCM_OUT] = {
140 .name = "pcm-out",
141 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
142 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
143 },
144 [DMACH_MIC_IN] = {
145 .name = "mic-in",
146 .channels = MAP(S3C2443_DMAREQSEL_MICIN),
147 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
148 },
149};
150
151static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
152 struct s3c24xx_dma_map *map)
153{
154 writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
155 chan->regs + S3C2443_DMA_DMAREQSEL);
156}
157
158static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
159 .select = s3c2443_dma_select,
160 .dcon_mask = 0,
161 .map = s3c2443_dma_mappings,
162 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
163};
164
165static int __init s3c2443_dma_add(struct sys_device *sysdev)
166{
167 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
168 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
169}
170
171static struct sysdev_driver s3c2443_dma_driver = {
172 .add = s3c2443_dma_add,
173};
174
175static int __init s3c2443_dma_init(void)
176{
177 return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver);
178}
179
180arch_initcall(s3c2443_dma_init);
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
new file mode 100644
index 00000000000..83ecb1173fb
--- /dev/null
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -0,0 +1,278 @@
1/* linux/arch/arm/mach-s3c2443/irq.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/sysdev.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
42
43static inline void s3c2443_irq_demux(unsigned int irq, unsigned int len)
44{
45 unsigned int subsrc, submsk;
46 unsigned int end;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= (irq - S3C2410_IRQSUB(0));
56 subsrc &= (1 << len)-1;
57
58 end = len + irq;
59
60 for (; irq < end && subsrc; irq++) {
61 if (subsrc & 1)
62 generic_handle_irq(irq);
63
64 subsrc >>= 1;
65 }
66}
67
68/* WDT/AC97 sub interrupts */
69
70static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
71{
72 s3c2443_irq_demux(IRQ_S3C2443_WDT, 4);
73}
74
75#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
76#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
77
78static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
79{
80 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
81}
82
83static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
84{
85 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
86}
87
88static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
89{
90 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
91}
92
93static struct irq_chip s3c2443_irq_wdtac97 = {
94 .irq_mask = s3c2443_irq_wdtac97_mask,
95 .irq_unmask = s3c2443_irq_wdtac97_unmask,
96 .irq_ack = s3c2443_irq_wdtac97_ack,
97};
98
99/* LCD sub interrupts */
100
101static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
102{
103 s3c2443_irq_demux(IRQ_S3C2443_LCD1, 4);
104}
105
106#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
107#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
108
109static void s3c2443_irq_lcd_mask(struct irq_data *data)
110{
111 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
112}
113
114static void s3c2443_irq_lcd_unmask(struct irq_data *data)
115{
116 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
117}
118
119static void s3c2443_irq_lcd_ack(struct irq_data *data)
120{
121 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
122}
123
124static struct irq_chip s3c2443_irq_lcd = {
125 .irq_mask = s3c2443_irq_lcd_mask,
126 .irq_unmask = s3c2443_irq_lcd_unmask,
127 .irq_ack = s3c2443_irq_lcd_ack,
128};
129
130/* DMA sub interrupts */
131
132static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
133{
134 s3c2443_irq_demux(IRQ_S3C2443_DMA0, 6);
135}
136
137#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
138#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
139
140static void s3c2443_irq_dma_mask(struct irq_data *data)
141{
142 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
143}
144
145static void s3c2443_irq_dma_unmask(struct irq_data *data)
146{
147 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
148}
149
150static void s3c2443_irq_dma_ack(struct irq_data *data)
151{
152 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
153}
154
155static struct irq_chip s3c2443_irq_dma = {
156 .irq_mask = s3c2443_irq_dma_mask,
157 .irq_unmask = s3c2443_irq_dma_unmask,
158 .irq_ack = s3c2443_irq_dma_ack,
159};
160
161/* UART3 sub interrupts */
162
163static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
164{
165 s3c2443_irq_demux(IRQ_S3C2443_RX3, 3);
166}
167
168#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
169#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
170
171static void s3c2443_irq_uart3_mask(struct irq_data *data)
172{
173 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
174}
175
176static void s3c2443_irq_uart3_unmask(struct irq_data *data)
177{
178 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
179}
180
181static void s3c2443_irq_uart3_ack(struct irq_data *data)
182{
183 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
184}
185
186static struct irq_chip s3c2443_irq_uart3 = {
187 .irq_mask = s3c2443_irq_uart3_mask,
188 .irq_unmask = s3c2443_irq_uart3_unmask,
189 .irq_ack = s3c2443_irq_uart3_ack,
190};
191
192/* CAM sub interrupts */
193
194static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
195{
196 s3c2443_irq_demux(IRQ_S3C2440_CAM_C, 4);
197}
198
199#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
200#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
201
202static void s3c2443_irq_cam_mask(struct irq_data *data)
203{
204 s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
205}
206
207static void s3c2443_irq_cam_unmask(struct irq_data *data)
208{
209 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
210}
211
212static void s3c2443_irq_cam_ack(struct irq_data *data)
213{
214 s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
215}
216
217static struct irq_chip s3c2443_irq_cam = {
218 .irq_mask = s3c2443_irq_cam_mask,
219 .irq_unmask = s3c2443_irq_cam_unmask,
220 .irq_ack = s3c2443_irq_cam_ack,
221};
222
223/* IRQ initialisation code */
224
225static int __init s3c2443_add_sub(unsigned int base,
226 void (*demux)(unsigned int,
227 struct irq_desc *),
228 struct irq_chip *chip,
229 unsigned int start, unsigned int end)
230{
231 unsigned int irqno;
232
233 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
234 irq_set_chained_handler(base, demux);
235
236 for (irqno = start; irqno <= end; irqno++) {
237 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
238 set_irq_flags(irqno, IRQF_VALID);
239 }
240
241 return 0;
242}
243
244static int __init s3c2443_irq_add(struct sys_device *sysdev)
245{
246 printk("S3C2443: IRQ Support\n");
247
248 s3c2443_add_sub(IRQ_CAM, s3c2443_irq_demux_cam, &s3c2443_irq_cam,
249 IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P);
250
251 s3c2443_add_sub(IRQ_LCD, s3c2443_irq_demux_lcd, &s3c2443_irq_lcd,
252 IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4);
253
254 s3c2443_add_sub(IRQ_S3C2443_DMA, s3c2443_irq_demux_dma,
255 &s3c2443_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
256
257 s3c2443_add_sub(IRQ_S3C2443_UART3, s3c2443_irq_demux_uart3,
258 &s3c2443_irq_uart3,
259 IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
260
261 s3c2443_add_sub(IRQ_WDT, s3c2443_irq_demux_wdtac97,
262 &s3c2443_irq_wdtac97,
263 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
264
265 return 0;
266}
267
268static struct sysdev_driver s3c2443_irq_driver = {
269 .add = s3c2443_irq_add,
270};
271
272static int __init s3c2443_irq_init(void)
273{
274 return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver);
275}
276
277arch_initcall(s3c2443_irq_init);
278
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
new file mode 100644
index 00000000000..514275e43ca
--- /dev/null
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -0,0 +1,148 @@
1/* linux/arch/arm/mach-s3c2443/mach-smdk2443.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.fluff.org/ben/smdk2443/
7 *
8 * Thanks to Samsung for the loan of an SMDK2443
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-gpio.h>
36#include <mach/regs-lcd.h>
37
38#include <mach/idle.h>
39#include <mach/fb.h>
40#include <plat/iic.h>
41
42#include <plat/s3c2410.h>
43#include <plat/s3c2443.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#include <plat/common-smdk.h>
49
50static struct map_desc smdk2443_iodesc[] __initdata = {
51 /* ISA IO Space map (memory space selected by A24) */
52
53 {
54 .virtual = (u32)S3C24XX_VA_ISA_WORD,
55 .pfn = __phys_to_pfn(S3C2410_CS2),
56 .length = 0x10000,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
60 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
61 .length = SZ_4M,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
65 .pfn = __phys_to_pfn(S3C2410_CS2),
66 .length = 0x10000,
67 .type = MT_DEVICE,
68 }, {
69 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
70 .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
71 .length = SZ_4M,
72 .type = MT_DEVICE,
73 }
74};
75
76#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
77#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
78#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
79
80static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
87 },
88 [1] = {
89 .hwport = 1,
90 .flags = 0,
91 .ucon = 0x3c5,
92 .ulcon = 0x03,
93 .ufcon = 0x51,
94 },
95 /* IR port */
96 [2] = {
97 .hwport = 2,
98 .flags = 0,
99 .ucon = 0x3c5,
100 .ulcon = 0x43,
101 .ufcon = 0x51,
102 },
103 [3] = {
104 .hwport = 3,
105 .flags = 0,
106 .ucon = 0x3c5,
107 .ulcon = 0x03,
108 .ufcon = 0x51,
109 }
110};
111
112static struct platform_device *smdk2443_devices[] __initdata = {
113 &s3c_device_wdt,
114 &s3c_device_i2c0,
115 &s3c_device_hsmmc1,
116#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
117 &s3c_device_ac97,
118#endif
119};
120
121static void __init smdk2443_map_io(void)
122{
123 s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
124 s3c24xx_init_clocks(12000000);
125 s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
126}
127
128static void __init smdk2443_machine_init(void)
129{
130 s3c_i2c0_set_platdata(NULL);
131
132#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
133 s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0);
134#endif
135
136 platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
137 smdk_machine_init();
138}
139
140MACHINE_START(SMDK2443, "SMDK2443")
141 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
142 .boot_params = S3C2410_SDRAM_PA + 0x100,
143
144 .init_irq = s3c24xx_init_irq,
145 .map_io = smdk2443_map_io,
146 .init_machine = smdk2443_machine_init,
147 .timer = &s3c24xx_timer,
148MACHINE_END
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
new file mode 100644
index 00000000000..e6a28ba52c7
--- /dev/null
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -0,0 +1,110 @@
1/* linux/arch/arm/mach-s3c2443/s3c2443.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2443 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/platform_device.h>
21#include <linux/serial_core.h>
22#include <linux/sysdev.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/irq.h>
32
33#include <mach/regs-s3c2443-clock.h>
34#include <mach/reset.h>
35
36#include <plat/gpio-core.h>
37#include <plat/gpio-cfg.h>
38#include <plat/gpio-cfg-helpers.h>
39#include <plat/s3c2443.h>
40#include <plat/devs.h>
41#include <plat/cpu.h>
42#include <plat/fb-core.h>
43#include <plat/nand-core.h>
44
45static struct map_desc s3c2443_iodesc[] __initdata = {
46 IODESC_ENT(WATCHDOG),
47 IODESC_ENT(CLKPWR),
48 IODESC_ENT(TIMER),
49};
50
51struct sysdev_class s3c2443_sysclass = {
52 .name = "s3c2443-core",
53};
54
55static struct sys_device s3c2443_sysdev = {
56 .cls = &s3c2443_sysclass,
57};
58
59static void s3c2443_hard_reset(void)
60{
61 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
62}
63
64int __init s3c2443_init(void)
65{
66 printk("S3C2443: Initialising architecture\n");
67
68 s3c24xx_reset_hook = s3c2443_hard_reset;
69
70 s3c_nand_setname("s3c2412-nand");
71 s3c_fb_setname("s3c2443-fb");
72
73 /* change WDT IRQ number */
74 s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
75 s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
76
77 return sysdev_register(&s3c2443_sysdev);
78}
79
80void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
81{
82 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
83}
84
85/* s3c2443_map_io
86 *
87 * register the standard cpu IO areas, and any passed in from the
88 * machine specific initialisation.
89 */
90
91void __init s3c2443_map_io(void)
92{
93 s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443;
94 s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443;
95
96 iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
97}
98
99/* need to register class before we actually register the device, and
100 * we also need to ensure that it has been initialised before any of the
101 * drivers even try to use it (even if not on an s3c2443 based system)
102 * as a driver which may support both 2443 and 2440 may try and use it.
103*/
104
105static int __init s3c2443_core_init(void)
106{
107 return sysdev_class_register(&s3c2443_sysclass);
108}
109
110core_initcall(s3c2443_core_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 00:14:03 -0400