diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
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committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-22 10:38:37 -0500 |
commit | fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch) | |
tree | a57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | |
parent | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff) |
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h')
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | 192 |
1 files changed, 192 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h new file mode 100644 index 00000000000..5e06c726583 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | |||
@@ -0,0 +1,192 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2007 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * S3C2443 clock register definitions | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARM_REGS_S3C2443_CLOCK | ||
15 | #define __ASM_ARM_REGS_S3C2443_CLOCK | ||
16 | |||
17 | #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) | ||
18 | |||
19 | #define S3C2443_PLLCON_MDIVSHIFT 16 | ||
20 | #define S3C2443_PLLCON_PDIVSHIFT 8 | ||
21 | #define S3C2443_PLLCON_SDIVSHIFT 0 | ||
22 | #define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1) | ||
23 | #define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1) | ||
24 | #define S3C2443_PLLCON_SDIVMASK (3) | ||
25 | |||
26 | #define S3C2443_MPLLCON S3C2443_CLKREG(0x10) | ||
27 | #define S3C2443_EPLLCON S3C2443_CLKREG(0x18) | ||
28 | #define S3C2443_CLKSRC S3C2443_CLKREG(0x20) | ||
29 | #define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24) | ||
30 | #define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28) | ||
31 | #define S3C2443_HCLKCON S3C2443_CLKREG(0x30) | ||
32 | #define S3C2443_PCLKCON S3C2443_CLKREG(0x34) | ||
33 | #define S3C2443_SCLKCON S3C2443_CLKREG(0x38) | ||
34 | #define S3C2443_PWRMODE S3C2443_CLKREG(0x40) | ||
35 | #define S3C2443_SWRST S3C2443_CLKREG(0x44) | ||
36 | #define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50) | ||
37 | #define S3C2443_SYSID S3C2443_CLKREG(0x5C) | ||
38 | #define S3C2443_PWRCFG S3C2443_CLKREG(0x60) | ||
39 | #define S3C2443_RSTCON S3C2443_CLKREG(0x64) | ||
40 | #define S3C2443_PHYCTRL S3C2443_CLKREG(0x80) | ||
41 | #define S3C2443_PHYPWR S3C2443_CLKREG(0x84) | ||
42 | #define S3C2443_URSTCON S3C2443_CLKREG(0x88) | ||
43 | #define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) | ||
44 | |||
45 | #define S3C2443_SWRST_RESET (0x533c2443) | ||
46 | |||
47 | #define S3C2443_PLLCON_OFF (1<<24) | ||
48 | |||
49 | #define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) | ||
50 | #define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7) | ||
51 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7) | ||
52 | #define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7) | ||
53 | #define S3C2443_CLKSRC_EPLLREF_MASK (3<<7) | ||
54 | |||
55 | #define S3C2443_CLKSRC_EXTCLK_DIV (1<<3) | ||
56 | |||
57 | #define S3C2443_CLKDIV0_HALF_HCLK (1<<3) | ||
58 | #define S3C2443_CLKDIV0_HALF_PCLK (1<<2) | ||
59 | |||
60 | #define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0) | ||
61 | |||
62 | #define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6) | ||
63 | #define S3C2443_CLKDIV0_EXTDIV_SHIFT (6) | ||
64 | |||
65 | #define S3C2443_CLKDIV0_PREDIV_MASK (3<<4) | ||
66 | #define S3C2443_CLKDIV0_PREDIV_SHIFT (4) | ||
67 | |||
68 | #define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9) | ||
69 | #define S3C2443_CLKDIV0_ARMDIV_SHIFT (9) | ||
70 | #define S3C2443_CLKDIV0_ARMDIV_1 (0<<9) | ||
71 | #define S3C2443_CLKDIV0_ARMDIV_2 (8<<9) | ||
72 | #define S3C2443_CLKDIV0_ARMDIV_3 (2<<9) | ||
73 | #define S3C2443_CLKDIV0_ARMDIV_4 (9<<9) | ||
74 | #define S3C2443_CLKDIV0_ARMDIV_6 (10<<9) | ||
75 | #define S3C2443_CLKDIV0_ARMDIV_8 (11<<9) | ||
76 | #define S3C2443_CLKDIV0_ARMDIV_12 (13<<9) | ||
77 | #define S3C2443_CLKDIV0_ARMDIV_16 (15<<9) | ||
78 | |||
79 | /* S3C2443_CLKDIV1 removed, only used in clock.c code */ | ||
80 | |||
81 | #define S3C2443_CLKCON_NAND | ||
82 | |||
83 | #define S3C2443_HCLKCON_DMA0 (1<<0) | ||
84 | #define S3C2443_HCLKCON_DMA1 (1<<1) | ||
85 | #define S3C2443_HCLKCON_DMA2 (1<<2) | ||
86 | #define S3C2443_HCLKCON_DMA3 (1<<3) | ||
87 | #define S3C2443_HCLKCON_DMA4 (1<<4) | ||
88 | #define S3C2443_HCLKCON_DMA5 (1<<5) | ||
89 | #define S3C2443_HCLKCON_CAMIF (1<<8) | ||
90 | #define S3C2443_HCLKCON_LCDC (1<<9) | ||
91 | #define S3C2443_HCLKCON_USBH (1<<11) | ||
92 | #define S3C2443_HCLKCON_USBD (1<<12) | ||
93 | #define S3C2416_HCLKCON_HSMMC0 (1<<15) | ||
94 | #define S3C2443_HCLKCON_HSMMC (1<<16) | ||
95 | #define S3C2443_HCLKCON_CFC (1<<17) | ||
96 | #define S3C2443_HCLKCON_SSMC (1<<18) | ||
97 | #define S3C2443_HCLKCON_DRAMC (1<<19) | ||
98 | |||
99 | #define S3C2443_PCLKCON_UART0 (1<<0) | ||
100 | #define S3C2443_PCLKCON_UART1 (1<<1) | ||
101 | #define S3C2443_PCLKCON_UART2 (1<<2) | ||
102 | #define S3C2443_PCLKCON_UART3 (1<<3) | ||
103 | #define S3C2443_PCLKCON_IIC (1<<4) | ||
104 | #define S3C2443_PCLKCON_SDI (1<<5) | ||
105 | #define S3C2443_PCLKCON_ADC (1<<7) | ||
106 | #define S3C2443_PCLKCON_AC97 (1<<8) | ||
107 | #define S3C2443_PCLKCON_IIS (1<<9) | ||
108 | #define S3C2443_PCLKCON_PWMT (1<<10) | ||
109 | #define S3C2443_PCLKCON_WDT (1<<11) | ||
110 | #define S3C2443_PCLKCON_RTC (1<<12) | ||
111 | #define S3C2443_PCLKCON_GPIO (1<<13) | ||
112 | #define S3C2443_PCLKCON_SPI0 (1<<14) | ||
113 | #define S3C2443_PCLKCON_SPI1 (1<<15) | ||
114 | |||
115 | #define S3C2443_SCLKCON_DDRCLK (1<<16) | ||
116 | #define S3C2443_SCLKCON_SSMCCLK (1<<15) | ||
117 | #define S3C2443_SCLKCON_HSSPICLK (1<<14) | ||
118 | #define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13) | ||
119 | #define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12) | ||
120 | #define S3C2443_SCLKCON_CAMCLK (1<<11) | ||
121 | #define S3C2443_SCLKCON_DISPCLK (1<<10) | ||
122 | #define S3C2443_SCLKCON_I2SCLK (1<<9) | ||
123 | #define S3C2443_SCLKCON_UARTCLK (1<<8) | ||
124 | #define S3C2443_SCLKCON_USBHOST (1<<1) | ||
125 | |||
126 | #define S3C2443_PWRCFG_SLEEP (1<<15) | ||
127 | |||
128 | #define S3C2443_PWRCFG_USBPHY (1 << 4) | ||
129 | |||
130 | #define S3C2443_URSTCON_FUNCRST (1 << 2) | ||
131 | #define S3C2443_URSTCON_PHYRST (1 << 0) | ||
132 | |||
133 | #define S3C2443_PHYCTRL_CLKSEL (1 << 3) | ||
134 | #define S3C2443_PHYCTRL_EXTCLK (1 << 2) | ||
135 | #define S3C2443_PHYCTRL_PLLSEL (1 << 1) | ||
136 | #define S3C2443_PHYCTRL_DSPORT (1 << 0) | ||
137 | |||
138 | #define S3C2443_PHYPWR_COMMON_ON (1 << 31) | ||
139 | #define S3C2443_PHYPWR_ANALOG_PD (1 << 4) | ||
140 | #define S3C2443_PHYPWR_PLL_REFCLK (1 << 3) | ||
141 | #define S3C2443_PHYPWR_XO_ON (1 << 2) | ||
142 | #define S3C2443_PHYPWR_PLL_PWRDN (1 << 1) | ||
143 | #define S3C2443_PHYPWR_FSUSPEND (1 << 0) | ||
144 | |||
145 | #define S3C2443_UCLKCON_DETECT_VBUS (1 << 31) | ||
146 | #define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2) | ||
147 | #define S3C2443_UCLKCON_TCLKEN (1 << 0) | ||
148 | |||
149 | #include <asm/div64.h> | ||
150 | |||
151 | static inline unsigned int | ||
152 | s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk) | ||
153 | { | ||
154 | unsigned int mdiv, pdiv, sdiv; | ||
155 | uint64_t fvco; | ||
156 | |||
157 | mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; | ||
158 | pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; | ||
159 | sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; | ||
160 | |||
161 | mdiv &= S3C2443_PLLCON_MDIVMASK; | ||
162 | pdiv &= S3C2443_PLLCON_PDIVMASK; | ||
163 | sdiv &= S3C2443_PLLCON_SDIVMASK; | ||
164 | |||
165 | fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); | ||
166 | do_div(fvco, pdiv << sdiv); | ||
167 | |||
168 | return (unsigned int)fvco; | ||
169 | } | ||
170 | |||
171 | static inline unsigned int | ||
172 | s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) | ||
173 | { | ||
174 | unsigned int mdiv, pdiv, sdiv; | ||
175 | uint64_t fvco; | ||
176 | |||
177 | mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; | ||
178 | pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT; | ||
179 | sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT; | ||
180 | |||
181 | mdiv &= S3C2443_PLLCON_MDIVMASK; | ||
182 | pdiv &= S3C2443_PLLCON_PDIVMASK; | ||
183 | sdiv &= S3C2443_PLLCON_SDIVMASK; | ||
184 | |||
185 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
186 | do_div(fvco, (pdiv + 2) << sdiv); | ||
187 | |||
188 | return (unsigned int)fvco; | ||
189 | } | ||
190 | |||
191 | #endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ | ||
192 | |||