ARM: S3C2416: Add S3C2416-specific registers definitions

Add macros for S3C2416 SoC support.

Signed-off-by: Yauhen Kharuzhy <jekhor@gmail.com>
[ben-linux@fluff.org: removed files that need changing]
[ben-linux@fluff.org: Fix S3C2416_GPH0_TXD0 definition]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>

1 files changed, 10 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
index de86ee8812b..0f07ba30b1f 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
@@ -27,6 +27,16 @@
 #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
 #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
 
+#define S3C2416_PRIORITY_MODE1          S3C2410_IRQREG(0x030)
+#define S3C2416_PRIORITY_UPDATE1        S3C2410_IRQREG(0x034)
+#define S3C2416_SRCPND2                 S3C2410_IRQREG(0x040)
+#define S3C2416_INTMOD2                 S3C2410_IRQREG(0x044)
+#define S3C2416_INTMSK2                 S3C2410_IRQREG(0x048)
+#define S3C2416_INTPND2                 S3C2410_IRQREG(0x050)
+#define S3C2416_INTOFFSET2              S3C2410_IRQREG(0x054)
+#define S3C2416_PRIORITY_MODE2          S3C2410_IRQREG(0x070)
+#define S3C2416_PRIORITY_UPDATE2        S3C2410_IRQREG(0x074)
+
 /* mask: 0=enable, 1=disable
  * 1 bit EINT, 4=EINT4, 23=EINT23
  * EINT0,1,2,3 are not handled here.