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authorPawel Moll <pawel.moll@arm.com>2011-03-17 08:10:22 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-26 06:06:08 -0400
commit0efc48ecaf0f84430524a1759ab9c60aad8eab1e (patch)
treeb49c1ee680de596663da6df0a73c7a399dce3fa1 /arch/arm/mach-realview
parent16c29dafcc86024048f1dbb8349d31cb22c7c55a (diff)
ARM: 6807/1: realview: Fix secondary GIC initialisation for EB with MPCore tile
The second GIC, present when EB board is used with a MPCore tile, was initialised starting with irq number 64, which made interrupts 64-95 in the primary GIC unusable. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-realview')
-rw-r--r--arch/arm/mach-realview/realview_eb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 2ecc1d94284..10e75faba4c 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -348,7 +348,7 @@ static void __init gic_init_irq(void)
348 348
349#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB 349#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
350 /* board GIC, secondary */ 350 /* board GIC, secondary */
351 gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), 351 gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE),
352 __io_address(REALVIEW_EB_GIC_CPU_BASE)); 352 __io_address(REALVIEW_EB_GIC_CPU_BASE));
353 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); 353 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
354#endif 354#endif