aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-pxa/lpd270.c
diff options
context:
space:
mode:
authorEric Miao <eric.miao@marvell.com>2008-09-11 03:53:50 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-09-26 18:43:22 -0400
commitfd90ff200012db86cb96294e2992edf15ec313b3 (patch)
treee84f566945f3ea76c2619f5e418689b07d1adf7a /arch/arm/mach-pxa/lpd270.c
parentb40c6762ba7640be4bd0e1e1bfeb2c629bda9808 (diff)
[ARM] pxa/lpd270: convert to use new MFP API
Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/lpd270.c')
-rw-r--r--arch/arm/mach-pxa/lpd270.c60
1 files changed, 40 insertions, 20 deletions
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index b7038948d1d..8ada6b0f4fb 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -40,7 +40,7 @@
40 40
41#include <mach/pxa-regs.h> 41#include <mach/pxa-regs.h>
42#include <mach/pxa2xx-regs.h> 42#include <mach/pxa2xx-regs.h>
43#include <mach/pxa2xx-gpio.h> 43#include <mach/mfp-pxa27x.h>
44#include <mach/lpd270.h> 44#include <mach/lpd270.h>
45#include <mach/audio.h> 45#include <mach/audio.h>
46#include <mach/pxafb.h> 46#include <mach/pxafb.h>
@@ -51,6 +51,43 @@
51#include "generic.h" 51#include "generic.h"
52#include "devices.h" 52#include "devices.h"
53 53
54static unsigned long lpd270_pin_config[] __initdata = {
55 /* Chip Selects */
56 GPIO15_nCS_1, /* Mainboard Flash */
57 GPIO78_nCS_2, /* CPLD + Ethernet */
58
59 /* LCD - 16bpp Active TFT */
60 GPIO58_LCD_LDD_0,
61 GPIO59_LCD_LDD_1,
62 GPIO60_LCD_LDD_2,
63 GPIO61_LCD_LDD_3,
64 GPIO62_LCD_LDD_4,
65 GPIO63_LCD_LDD_5,
66 GPIO64_LCD_LDD_6,
67 GPIO65_LCD_LDD_7,
68 GPIO66_LCD_LDD_8,
69 GPIO67_LCD_LDD_9,
70 GPIO68_LCD_LDD_10,
71 GPIO69_LCD_LDD_11,
72 GPIO70_LCD_LDD_12,
73 GPIO71_LCD_LDD_13,
74 GPIO72_LCD_LDD_14,
75 GPIO73_LCD_LDD_15,
76 GPIO74_LCD_FCLK,
77 GPIO75_LCD_LCLK,
78 GPIO76_LCD_PCLK,
79 GPIO77_LCD_BIAS,
80 GPIO16_PWM0_OUT, /* Backlight */
81
82 /* USB Host */
83 GPIO88_USBH1_PWR,
84 GPIO89_USBH1_PEN,
85
86 /* AC97 */
87 GPIO45_AC97_SYSCLK,
88
89 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
90};
54 91
55static unsigned int lpd270_irq_enabled; 92static unsigned int lpd270_irq_enabled;
56 93
@@ -413,10 +450,6 @@ static struct platform_device *platform_devices[] __initdata = {
413 450
414static int lpd270_ohci_init(struct device *dev) 451static int lpd270_ohci_init(struct device *dev)
415{ 452{
416 /* setup Port1 GPIO pin. */
417 pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
418 pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
419
420 /* Set the Power Control Polarity Low and Power Sense 453 /* Set the Power Control Polarity Low and Power Sense
421 Polarity Low to active low. */ 454 Polarity Low to active low. */
422 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & 455 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
@@ -432,6 +465,8 @@ static struct pxaohci_platform_data lpd270_ohci_platform_data = {
432 465
433static void __init lpd270_init(void) 466static void __init lpd270_init(void)
434{ 467{
468 pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
469
435 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; 470 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
436 lpd270_flash_data[1].width = 4; 471 lpd270_flash_data[1].width = 4;
437 472
@@ -442,12 +477,6 @@ static void __init lpd270_init(void)
442 */ 477 */
443 ARB_CNTRL = ARB_CORE_PARK | 0x234; 478 ARB_CNTRL = ARB_CORE_PARK | 0x234;
444 479
445 /*
446 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
447 */
448 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
449 pxa_gpio_mode(GPIO16_PWM0_MD);
450
451 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 480 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
452 481
453 pxa_set_ac97_info(NULL); 482 pxa_set_ac97_info(NULL);
@@ -473,15 +502,6 @@ static void __init lpd270_map_io(void)
473 pxa_map_io(); 502 pxa_map_io();
474 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); 503 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
475 504
476 /* initialize sleep mode regs (wake-up sources, etc) */
477 PGSR0 = 0x00008800;
478 PGSR1 = 0x00000002;
479 PGSR2 = 0x0001FC00;
480 PGSR3 = 0x00001F81;
481 PWER = 0xC0000002;
482 PRER = 0x00000002;
483 PFER = 0x00000002;
484
485 /* for use I SRAM as framebuffer. */ 505 /* for use I SRAM as framebuffer. */
486 PSLR |= 0x00000F04; 506 PSLR |= 0x00000F04;
487 PCFR = 0x00000066; 507 PCFR = 0x00000066;