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authorBenoit Cousson <b-cousson@ti.com>2010-12-23 17:30:31 -0500
committerTony Lindgren <tony@atomide.com>2010-12-24 12:39:27 -0500
commitd7cf5f33fc68573d7bb9d4fc244ea1a3ed0b011b (patch)
treea68fbdbb8f0d773eaf81a339d8795843871c1f1a /arch/arm/mach-omap2
parent1f6a717f1c000bb6184fe09c5ae99bad5965cadf (diff)
OMAP4: hwmod data: Move the DMA structures
The merge of the DMA series on top of the already modified omap_hwmod_data_44xx.c put the dma_system structures at the wrong position in the file. Re-order it properly. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Tested-by: G, Manjunath Kondaiah <manjugk@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c196
1 files changed, 97 insertions, 99 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 378d4a73f9a..f35a99dde0b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -254,6 +254,14 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
254}; 254};
255 255
256/* l3_main_2 interface data */ 256/* l3_main_2 interface data */
257/* dma_system -> l3_main_2 */
258static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
259 .master = &omap44xx_dma_system_hwmod,
260 .slave = &omap44xx_l3_main_2_hwmod,
261 .clk = "l3_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
257/* iva -> l3_main_2 */ 265/* iva -> l3_main_2 */
258static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { 266static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
259 .master = &omap44xx_iva_hwmod, 267 .master = &omap44xx_iva_hwmod,
@@ -270,14 +278,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
270 .user = OCP_USER_MPU | OCP_USER_SDMA, 278 .user = OCP_USER_MPU | OCP_USER_SDMA,
271}; 279};
272 280
273/* dma_system -> l3_main_2 */
274static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
275 .master = &omap44xx_dma_system_hwmod,
276 .slave = &omap44xx_l3_main_2_hwmod,
277 .clk = "l3_div_ck",
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
279};
280
281/* l4_cfg -> l3_main_2 */ 281/* l4_cfg -> l3_main_2 */
282static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { 282static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
283 .master = &omap44xx_l4_cfg_hwmod, 283 .master = &omap44xx_l4_cfg_hwmod,
@@ -506,7 +506,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
506 * ctrl_module_pad_wkup 506 * ctrl_module_pad_wkup
507 * ctrl_module_wkup 507 * ctrl_module_wkup
508 * debugss 508 * debugss
509 * dma_system
510 * dmic 509 * dmic
511 * dss 510 * dss
512 * dss_dispc 511 * dss_dispc
@@ -577,6 +576,92 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
577 */ 576 */
578 577
579/* 578/*
579 * 'dma' class
580 * dma controller for data exchange between memory to memory (i.e. internal or
581 * external memory) and gp peripherals to memory or memory to gp peripherals
582 */
583
584static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
585 .rev_offs = 0x0000,
586 .sysc_offs = 0x002c,
587 .syss_offs = 0x0028,
588 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
589 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
590 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
591 SYSS_HAS_RESET_STATUS),
592 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
593 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
594 .sysc_fields = &omap_hwmod_sysc_type1,
595};
596
597static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
598 .name = "dma",
599 .sysc = &omap44xx_dma_sysc,
600};
601
602/* dma dev_attr */
603static struct omap_dma_dev_attr dma_dev_attr = {
604 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
605 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
606 .lch_count = 32,
607};
608
609/* dma_system */
610static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
611 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
612 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
613 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
614 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
615};
616
617/* dma_system master ports */
618static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
619 &omap44xx_dma_system__l3_main_2,
620};
621
622static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
623 {
624 .pa_start = 0x4a056000,
625 .pa_end = 0x4a0560ff,
626 .flags = ADDR_TYPE_RT
627 },
628};
629
630/* l4_cfg -> dma_system */
631static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
632 .master = &omap44xx_l4_cfg_hwmod,
633 .slave = &omap44xx_dma_system_hwmod,
634 .clk = "l4_div_ck",
635 .addr = omap44xx_dma_system_addrs,
636 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
637 .user = OCP_USER_MPU | OCP_USER_SDMA,
638};
639
640/* dma_system slave ports */
641static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
642 &omap44xx_l4_cfg__dma_system,
643};
644
645static struct omap_hwmod omap44xx_dma_system_hwmod = {
646 .name = "dma_system",
647 .class = &omap44xx_dma_hwmod_class,
648 .mpu_irqs = omap44xx_dma_system_irqs,
649 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
650 .main_clk = "l3_div_ck",
651 .prcm = {
652 .omap4 = {
653 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
654 },
655 },
656 .dev_attr = &dma_dev_attr,
657 .slaves = omap44xx_dma_system_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
659 .masters = omap44xx_dma_system_masters,
660 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
661 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
662};
663
664/*
580 * 'dsp' class 665 * 'dsp' class
581 * dsp sub-system 666 * dsp sub-system
582 */ 667 */
@@ -1916,93 +2001,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1916 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 2001 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1917}; 2002};
1918 2003
1919
1920/*
1921 * 'dma' class
1922 * dma controller for data exchange between memory to memory (i.e. internal or
1923 * external memory) and gp peripherals to memory or memory to gp peripherals
1924 */
1925
1926static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1927 .rev_offs = 0x0000,
1928 .sysc_offs = 0x002c,
1929 .syss_offs = 0x0028,
1930 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1931 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1932 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1933 SYSS_HAS_RESET_STATUS),
1934 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1935 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1936 .sysc_fields = &omap_hwmod_sysc_type1,
1937};
1938
1939/* dma attributes */
1940static struct omap_dma_dev_attr dma_dev_attr = {
1941 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1942 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1943 .lch_count = 32,
1944};
1945
1946static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1947 .name = "dma",
1948 .sysc = &omap44xx_dma_sysc,
1949};
1950
1951/* dma_system */
1952static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1953 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1954 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1955 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1956 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1957};
1958
1959/* dma_system master ports */
1960static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1961 &omap44xx_dma_system__l3_main_2,
1962};
1963
1964static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1965 {
1966 .pa_start = 0x4a056000,
1967 .pa_end = 0x4a0560ff,
1968 .flags = ADDR_TYPE_RT
1969 },
1970};
1971
1972/* l4_cfg -> dma_system */
1973static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1974 .master = &omap44xx_l4_cfg_hwmod,
1975 .slave = &omap44xx_dma_system_hwmod,
1976 .clk = "l4_div_ck",
1977 .addr = omap44xx_dma_system_addrs,
1978 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
1979 .user = OCP_USER_MPU | OCP_USER_SDMA,
1980};
1981
1982/* dma_system slave ports */
1983static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1984 &omap44xx_l4_cfg__dma_system,
1985};
1986
1987static struct omap_hwmod omap44xx_dma_system_hwmod = {
1988 .name = "dma_system",
1989 .class = &omap44xx_dma_hwmod_class,
1990 .mpu_irqs = omap44xx_dma_system_irqs,
1991 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
1992 .main_clk = "l3_div_ck",
1993 .prcm = {
1994 .omap4 = {
1995 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1996 },
1997 },
1998 .slaves = omap44xx_dma_system_slaves,
1999 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
2000 .masters = omap44xx_dma_system_masters,
2001 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
2002 .dev_attr = &dma_dev_attr,
2003 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2004};
2005
2006static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 2004static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2007 /* dmm class */ 2005 /* dmm class */
2008 &omap44xx_dmm_hwmod, 2006 &omap44xx_dmm_hwmod,
@@ -2022,12 +2020,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2022 &omap44xx_l4_per_hwmod, 2020 &omap44xx_l4_per_hwmod,
2023 &omap44xx_l4_wkup_hwmod, 2021 &omap44xx_l4_wkup_hwmod,
2024 2022
2025 /* dma class */
2026 &omap44xx_dma_system_hwmod,
2027
2028 /* mpu_bus class */ 2023 /* mpu_bus class */
2029 &omap44xx_mpu_private_hwmod, 2024 &omap44xx_mpu_private_hwmod,
2030 2025
2026 /* dma class */
2027 &omap44xx_dma_system_hwmod,
2028
2031 /* dsp class */ 2029 /* dsp class */
2032 &omap44xx_dsp_hwmod, 2030 &omap44xx_dsp_hwmod,
2033 &omap44xx_dsp_c0_hwmod, 2031 &omap44xx_dsp_c0_hwmod,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 10:32:57 -0400