diff options
author | Kevin Hilman <khilman@deeprootsystems.com> | 2010-10-01 16:24:10 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-10-01 16:24:10 -0400 |
commit | 69758ab7a1e2de5636a2188d5357dd03140bf1d8 (patch) | |
tree | 13d65cbee4cc6bfed697bd164a15529ad86c2b25 /arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |
parent | 963bfb0939232e415c7bfb19b08dce300eb148d9 (diff) | |
parent | 257f23d87f9309fee41d468575404b9371bf4c7d (diff) |
manual merge for pm-hwmod-uart due to conflicts
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 235 |
1 files changed, 235 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 9523b4c9537..7274db4de48 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -468,6 +468,21 @@ static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |||
468 | .sysc_fields = &omap_hwmod_sysc_type1, | 468 | .sysc_fields = &omap_hwmod_sysc_type1, |
469 | }; | 469 | }; |
470 | 470 | ||
471 | /* | ||
472 | * 'uart' class | ||
473 | * universal asynchronous receiver/transmitter (uart) | ||
474 | */ | ||
475 | |||
476 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { | ||
477 | .rev_offs = 0x0050, | ||
478 | .sysc_offs = 0x0054, | ||
479 | .syss_offs = 0x0058, | ||
480 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
481 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
482 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
483 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
484 | }; | ||
485 | |||
471 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { | 486 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
472 | .name = "wd_timer", | 487 | .name = "wd_timer", |
473 | .sysc = &omap44xx_wd_timer_sysc, | 488 | .sysc = &omap44xx_wd_timer_sysc, |
@@ -487,6 +502,82 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |||
487 | }, | 502 | }, |
488 | }; | 503 | }; |
489 | 504 | ||
505 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { | ||
506 | .name = "uart", | ||
507 | .sysc = &omap44xx_uart_sysc, | ||
508 | }; | ||
509 | |||
510 | /* uart1 */ | ||
511 | static struct omap_hwmod omap44xx_uart1_hwmod; | ||
512 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | ||
513 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | ||
514 | }; | ||
515 | |||
516 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { | ||
517 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | ||
518 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | ||
519 | }; | ||
520 | |||
521 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { | ||
522 | { | ||
523 | .pa_start = 0x4806a000, | ||
524 | .pa_end = 0x4806a0ff, | ||
525 | .flags = ADDR_TYPE_RT | ||
526 | }, | ||
527 | }; | ||
528 | |||
529 | /* l4_per -> uart1 */ | ||
530 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | ||
531 | .master = &omap44xx_l4_per_hwmod, | ||
532 | .slave = &omap44xx_uart1_hwmod, | ||
533 | .clk = "l4_div_ck", | ||
534 | .addr = omap44xx_uart1_addrs, | ||
535 | .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), | ||
536 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
537 | }; | ||
538 | |||
539 | /* uart1 slave ports */ | ||
540 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | ||
541 | &omap44xx_l4_per__uart1, | ||
542 | }; | ||
543 | |||
544 | static struct omap_hwmod omap44xx_uart1_hwmod = { | ||
545 | .name = "uart1", | ||
546 | .class = &omap44xx_uart_hwmod_class, | ||
547 | .mpu_irqs = omap44xx_uart1_irqs, | ||
548 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), | ||
549 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | ||
550 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), | ||
551 | .main_clk = "uart1_fck", | ||
552 | .prcm = { | ||
553 | .omap4 = { | ||
554 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | ||
555 | }, | ||
556 | }, | ||
557 | .slaves = omap44xx_uart1_slaves, | ||
558 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | ||
559 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
560 | }; | ||
561 | |||
562 | /* uart2 */ | ||
563 | static struct omap_hwmod omap44xx_uart2_hwmod; | ||
564 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | ||
565 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | ||
566 | }; | ||
567 | |||
568 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { | ||
569 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | ||
570 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | ||
571 | }; | ||
572 | |||
573 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | ||
574 | { | ||
575 | .pa_start = 0x4806c000, | ||
576 | .pa_end = 0x4806c0ff, | ||
577 | .flags = ADDR_TYPE_RT | ||
578 | }, | ||
579 | }; | ||
580 | |||
490 | /* l4_wkup -> wd_timer2 */ | 581 | /* l4_wkup -> wd_timer2 */ |
491 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | 582 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { |
492 | .master = &omap44xx_l4_wkup_hwmod, | 583 | .master = &omap44xx_l4_wkup_hwmod, |
@@ -532,6 +623,58 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |||
532 | }, | 623 | }, |
533 | }; | 624 | }; |
534 | 625 | ||
626 | /* l4_per -> uart2 */ | ||
627 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | ||
628 | .master = &omap44xx_l4_per_hwmod, | ||
629 | .slave = &omap44xx_uart2_hwmod, | ||
630 | .clk = "l4_div_ck", | ||
631 | .addr = omap44xx_uart2_addrs, | ||
632 | .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), | ||
633 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
634 | }; | ||
635 | |||
636 | /* uart2 slave ports */ | ||
637 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | ||
638 | &omap44xx_l4_per__uart2, | ||
639 | }; | ||
640 | |||
641 | static struct omap_hwmod omap44xx_uart2_hwmod = { | ||
642 | .name = "uart2", | ||
643 | .class = &omap44xx_uart_hwmod_class, | ||
644 | .mpu_irqs = omap44xx_uart2_irqs, | ||
645 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), | ||
646 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | ||
647 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), | ||
648 | .main_clk = "uart2_fck", | ||
649 | .prcm = { | ||
650 | .omap4 = { | ||
651 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | ||
652 | }, | ||
653 | }, | ||
654 | .slaves = omap44xx_uart2_slaves, | ||
655 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | ||
656 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
657 | }; | ||
658 | |||
659 | /* uart3 */ | ||
660 | static struct omap_hwmod omap44xx_uart3_hwmod; | ||
661 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | ||
662 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | ||
663 | }; | ||
664 | |||
665 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { | ||
666 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | ||
667 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | ||
668 | }; | ||
669 | |||
670 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | ||
671 | { | ||
672 | .pa_start = 0x48020000, | ||
673 | .pa_end = 0x480200ff, | ||
674 | .flags = ADDR_TYPE_RT | ||
675 | }, | ||
676 | }; | ||
677 | |||
535 | /* l4_abe -> wd_timer3 */ | 678 | /* l4_abe -> wd_timer3 */ |
536 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | 679 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { |
537 | .master = &omap44xx_l4_abe_hwmod, | 680 | .master = &omap44xx_l4_abe_hwmod, |
@@ -551,6 +694,59 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |||
551 | }, | 694 | }, |
552 | }; | 695 | }; |
553 | 696 | ||
697 | /* l4_per -> uart3 */ | ||
698 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | ||
699 | .master = &omap44xx_l4_per_hwmod, | ||
700 | .slave = &omap44xx_uart3_hwmod, | ||
701 | .clk = "l4_div_ck", | ||
702 | .addr = omap44xx_uart3_addrs, | ||
703 | .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), | ||
704 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
705 | }; | ||
706 | |||
707 | /* uart3 slave ports */ | ||
708 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | ||
709 | &omap44xx_l4_per__uart3, | ||
710 | }; | ||
711 | |||
712 | static struct omap_hwmod omap44xx_uart3_hwmod = { | ||
713 | .name = "uart3", | ||
714 | .class = &omap44xx_uart_hwmod_class, | ||
715 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | ||
716 | .mpu_irqs = omap44xx_uart3_irqs, | ||
717 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), | ||
718 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | ||
719 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), | ||
720 | .main_clk = "uart3_fck", | ||
721 | .prcm = { | ||
722 | .omap4 = { | ||
723 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | ||
724 | }, | ||
725 | }, | ||
726 | .slaves = omap44xx_uart3_slaves, | ||
727 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | ||
728 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
729 | }; | ||
730 | |||
731 | /* uart4 */ | ||
732 | static struct omap_hwmod omap44xx_uart4_hwmod; | ||
733 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | ||
734 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | ||
735 | }; | ||
736 | |||
737 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { | ||
738 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | ||
739 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | ||
740 | }; | ||
741 | |||
742 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | ||
743 | { | ||
744 | .pa_start = 0x4806e000, | ||
745 | .pa_end = 0x4806e0ff, | ||
746 | .flags = ADDR_TYPE_RT | ||
747 | }, | ||
748 | }; | ||
749 | |||
554 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | 750 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { |
555 | .master = &omap44xx_l4_abe_hwmod, | 751 | .master = &omap44xx_l4_abe_hwmod, |
556 | .slave = &omap44xx_wd_timer3_hwmod, | 752 | .slave = &omap44xx_wd_timer3_hwmod, |
@@ -582,6 +778,39 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |||
582 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 778 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
583 | }; | 779 | }; |
584 | 780 | ||
781 | /* l4_per -> uart4 */ | ||
782 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | ||
783 | .master = &omap44xx_l4_per_hwmod, | ||
784 | .slave = &omap44xx_uart4_hwmod, | ||
785 | .clk = "l4_div_ck", | ||
786 | .addr = omap44xx_uart4_addrs, | ||
787 | .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), | ||
788 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
789 | }; | ||
790 | |||
791 | /* uart4 slave ports */ | ||
792 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | ||
793 | &omap44xx_l4_per__uart4, | ||
794 | }; | ||
795 | |||
796 | static struct omap_hwmod omap44xx_uart4_hwmod = { | ||
797 | .name = "uart4", | ||
798 | .class = &omap44xx_uart_hwmod_class, | ||
799 | .mpu_irqs = omap44xx_uart4_irqs, | ||
800 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), | ||
801 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | ||
802 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), | ||
803 | .main_clk = "uart4_fck", | ||
804 | .prcm = { | ||
805 | .omap4 = { | ||
806 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | ||
807 | }, | ||
808 | }, | ||
809 | .slaves = omap44xx_uart4_slaves, | ||
810 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | ||
811 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
812 | }; | ||
813 | |||
585 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { | 814 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
586 | /* dmm class */ | 815 | /* dmm class */ |
587 | &omap44xx_dmm_hwmod, | 816 | &omap44xx_dmm_hwmod, |
@@ -605,6 +834,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { | |||
605 | /* wd_timer class */ | 834 | /* wd_timer class */ |
606 | &omap44xx_wd_timer2_hwmod, | 835 | &omap44xx_wd_timer2_hwmod, |
607 | &omap44xx_wd_timer3_hwmod, | 836 | &omap44xx_wd_timer3_hwmod, |
837 | |||
838 | /* uart class */ | ||
839 | &omap44xx_uart1_hwmod, | ||
840 | &omap44xx_uart2_hwmod, | ||
841 | &omap44xx_uart3_hwmod, | ||
842 | &omap44xx_uart4_hwmod, | ||
608 | NULL, | 843 | NULL, |
609 | }; | 844 | }; |
610 | 845 | ||