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authorBenoit Cousson <b-cousson@ti.com>2011-07-09 21:15:05 -0400
committerPaul Walmsley <paul@pwsan.com>2011-07-09 21:15:05 -0400
commit7b342a8d4c310b5cc153b35ea80aab03ddf2e6da (patch)
tree84a2dde9a08637e21f2663848e292e5a3282654a /arch/arm/mach-omap2/cm-regbits-44xx.h
parent0fef658331354138d422500509d6e006d9f070d6 (diff)
OMAP4: cm: Remove RESTORE macros to avoid access from SW
The restore part of the CM is an alias of some regular registers used only during the SAR restore to facilate the dma to write a contiguous set of registers. The registers should never be used by the SW, only the original register have to be used. Remove them from cmX_44xx.h files to avoid anybody to use them by mistake. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-44xx.h')
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h623
1 files changed, 254 insertions, 369 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b..0e77945d26e 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,22 +22,18 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
24 24
25/* 25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
26 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
27 * CM_TESLA_DYNAMICDEP
28 */
29#define OMAP4430_ABE_DYNDEP_SHIFT 3 26#define OMAP4430_ABE_DYNDEP_SHIFT 3
30#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) 27#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
31 28
32/* 29/*
33 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 30 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
34 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 31 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
35 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
36 */ 32 */
37#define OMAP4430_ABE_STATDEP_SHIFT 3 33#define OMAP4430_ABE_STATDEP_SHIFT 3
38#define OMAP4430_ABE_STATDEP_MASK (1 << 3) 34#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
39 35
40/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 36/* Used by CM_L4CFG_DYNAMICDEP */
41#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 37#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
42#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) 38#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
43 39
@@ -47,14 +43,13 @@
47 43
48/* 44/*
49 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 45 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
50 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, 46 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
51 * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, 47 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
52 * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
53 */ 48 */
54#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 49#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
55#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 50#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
56 51
57/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 52/* Used by CM_L4CFG_DYNAMICDEP */
58#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 53#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
59#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) 54#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
60 55
@@ -82,15 +77,15 @@
82#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 77#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
83#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 78#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
84 79
85/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 80/* Used by CM_MEMIF_CLKSTCTRL */
86#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 81#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
87#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) 82#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
88 83
89/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 84/* Used by CM_MEMIF_CLKSTCTRL */
90#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 85#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
91#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) 86#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
92 87
93/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 88/* Used by CM_MEMIF_CLKSTCTRL */
94#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 89#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
95#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) 90#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
96 91
@@ -110,31 +105,31 @@
110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 105#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
111#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 106#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
112 107
113/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 108/* Used by CM_MEMIF_CLKSTCTRL */
114#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 109#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
115#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) 110#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
116 111
117/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 112/* Used by CM_L4PER_CLKSTCTRL */
118#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 113#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
119#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) 114#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
120 115
121/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 116/* Used by CM_L4PER_CLKSTCTRL */
122#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 117#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
123#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) 118#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
124 119
125/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 120/* Used by CM_L4PER_CLKSTCTRL */
126#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 121#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
127#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) 122#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
128 123
129/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 124/* Used by CM_L4PER_CLKSTCTRL */
130#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 125#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
131#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) 126#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
132 127
133/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 128/* Used by CM_L4PER_CLKSTCTRL */
134#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 129#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
135#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) 130#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
136 131
137/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 132/* Used by CM_L4PER_CLKSTCTRL */
138#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 133#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
139#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) 134#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
140 135
@@ -158,7 +153,7 @@
158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 153#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
159#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) 154#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
160 155
161/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 156/* Used by CM_L4PER_CLKSTCTRL */
162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 157#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
163#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) 158#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
164 159
@@ -170,55 +165,55 @@
170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 165#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
171#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) 166#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
172 167
173/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 168/* Used by CM_L3INIT_CLKSTCTRL */
174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 169#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
175#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 170#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
176 171
177/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 172/* Used by CM_L3INIT_CLKSTCTRL */
178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 173#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
179#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 174#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
180 175
181/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 176/* Used by CM_L3INIT_CLKSTCTRL */
182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 177#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
183#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 178#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
184 179
185/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 180/* Used by CM_L3INIT_CLKSTCTRL */
186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 181#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
187#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 182#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
188 183
189/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 184/* Used by CM_L3INIT_CLKSTCTRL */
190#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 185#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
191#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) 186#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
192 187
193/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 188/* Used by CM_L3INIT_CLKSTCTRL */
194#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 189#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
195#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) 190#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
196 191
197/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 192/* Used by CM_L3INIT_CLKSTCTRL */
198#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 193#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
199#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) 194#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
200 195
201/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 196/* Used by CM_L3INIT_CLKSTCTRL */
202#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 197#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
203#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) 198#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
204 199
205/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 200/* Used by CM_L3INIT_CLKSTCTRL */
206#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 201#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
207#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) 202#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
208 203
209/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 204/* Used by CM_L3INIT_CLKSTCTRL */
210#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 205#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
211#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) 206#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
212 207
213/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 208/* Used by CM_L3INIT_CLKSTCTRL */
214#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 209#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
215#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) 210#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
216 211
217/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 212/* Used by CM_L3INIT_CLKSTCTRL */
218#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 213#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
219#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) 214#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
220 215
221/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 216/* Used by CM_L3INIT_CLKSTCTRL */
222#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 217#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
223#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) 218#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
224 219
@@ -234,11 +229,11 @@
234#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 229#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
235#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) 230#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
236 231
237/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 232/* Used by CM_L3_1_CLKSTCTRL */
238#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 233#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
239#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) 234#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
240 235
241/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 236/* Used by CM_L3_2_CLKSTCTRL */
242#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 237#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
243#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) 238#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
244 239
@@ -254,7 +249,7 @@
254#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 249#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
255#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) 250#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
256 251
257/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 252/* Used by CM_MEMIF_CLKSTCTRL */
258#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 253#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
259#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) 254#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
260 255
@@ -262,7 +257,7 @@
262#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 257#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
263#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) 258#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
264 259
265/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 260/* Used by CM_L3INIT_CLKSTCTRL */
266#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 261#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
267#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) 262#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
268 263
@@ -282,7 +277,7 @@
282#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 277#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
283#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 278#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
284 279
285/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 280/* Used by CM_L4CFG_CLKSTCTRL */
286#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 281#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
287#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) 282#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
288 283
@@ -290,11 +285,11 @@
290#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 285#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
291#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) 286#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
292 287
293/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 288/* Used by CM_L3INIT_CLKSTCTRL */
294#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 289#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
295#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) 290#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
296 291
297/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 292/* Used by CM_L4PER_CLKSTCTRL */
298#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 293#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
299#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) 294#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
300 295
@@ -306,7 +301,7 @@
306#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 301#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
307#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) 302#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
308 303
309/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 304/* Used by CM_MPU_CLKSTCTRL */
310#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 305#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
311#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) 306#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
312 307
@@ -314,43 +309,43 @@
314#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 309#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
315#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) 310#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
316 311
317/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 312/* Used by CM_L4PER_CLKSTCTRL */
318#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 313#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
319#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) 314#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
320 315
321/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 316/* Used by CM_L4PER_CLKSTCTRL */
322#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 317#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
323#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 318#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
324 319
325/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 320/* Used by CM_L4PER_CLKSTCTRL */
326#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 321#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
327#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 322#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
328 323
329/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 324/* Used by CM_L4PER_CLKSTCTRL */
330#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 325#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
331#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 326#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
332 327
333/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 328/* Used by CM_L4PER_CLKSTCTRL */
334#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 329#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
335#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) 330#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
336 331
337/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 332/* Used by CM_L4PER_CLKSTCTRL */
338#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 333#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
339#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) 334#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
340 335
341/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 336/* Used by CM_L4PER_CLKSTCTRL */
342#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 337#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
343#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) 338#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
344 339
345/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 340/* Used by CM_L4PER_CLKSTCTRL */
346#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 341#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
347#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) 342#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
348 343
349/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 344/* Used by CM_L4PER_CLKSTCTRL */
350#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 345#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
351#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) 346#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
352 347
353/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 348/* Used by CM_MEMIF_CLKSTCTRL */
354#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 349#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
355#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) 350#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
356 351
@@ -378,27 +373,27 @@
378#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 373#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
379#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) 374#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
380 375
381/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 376/* Used by CM_L3INIT_CLKSTCTRL */
382#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 377#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
383#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 378#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
384 379
385/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 380/* Used by CM_L3INIT_CLKSTCTRL */
386#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 381#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
387#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 382#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
388 383
389/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 384/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 385#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
391#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 386#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
392 387
393/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 388/* Used by CM_L3INIT_CLKSTCTRL */
394#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 389#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
395#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) 390#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
396 391
397/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 392/* Used by CM_L3INIT_CLKSTCTRL */
398#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 393#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
399#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 394#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
400 395
401/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 396/* Used by CM_L3INIT_CLKSTCTRL */
402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 397#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
403#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 398#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
404 399
@@ -406,11 +401,11 @@
406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 401#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
407#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) 402#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
408 403
409/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 404/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 405#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
411#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 406#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
412 407
413/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 408/* Used by CM_L3INIT_CLKSTCTRL */
414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 409#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
415#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 410#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
416 411
@@ -432,7 +427,7 @@
432 427
433/* 428/*
434 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 429 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
435 * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ 430 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
436 */ 431 */
437#define OMAP4430_CLKSEL_0_0_SHIFT 0 432#define OMAP4430_CLKSEL_0_0_SHIFT 0
438#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) 433#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
@@ -453,14 +448,11 @@
453#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 448#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
454#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 449#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
455 450
456/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 451/* Used by CM_CLKSEL_CORE */
457#define OMAP4430_CLKSEL_CORE_SHIFT 0 452#define OMAP4430_CLKSEL_CORE_SHIFT 0
458#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) 453#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
459 454
460/* 455/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
461 * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
462 * CM_SHADOW_FREQ_CONFIG2
463 */
464#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 456#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
465#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) 457#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
466 458
@@ -484,18 +476,15 @@
484#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 476#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
485#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) 477#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
486 478
487/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 479/* Used by CM_CLKSEL_CORE */
488#define OMAP4430_CLKSEL_L3_SHIFT 4 480#define OMAP4430_CLKSEL_L3_SHIFT 4
489#define OMAP4430_CLKSEL_L3_MASK (1 << 4) 481#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
490 482
491/* 483/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
492 * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
493 * CM_SHADOW_FREQ_CONFIG2
494 */
495#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 484#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
496#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) 485#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
497 486
498/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 487/* Used by CM_CLKSEL_CORE */
499#define OMAP4430_CLKSEL_L4_SHIFT 8 488#define OMAP4430_CLKSEL_L4_SHIFT 8
500#define OMAP4430_CLKSEL_L4_MASK (1 << 8) 489#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
501 490
@@ -526,11 +515,11 @@
526#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 515#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
527#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 516#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
528 517
529/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 518/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
530#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 519#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
531#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) 520#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
532 521
533/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 522/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
534#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 523#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
535#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) 524#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
536 525
@@ -538,13 +527,10 @@
538 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, 527 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
539 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, 528 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
540 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, 529 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
541 * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, 530 * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
542 * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, 531 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
543 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, 532 * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
544 * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, 533 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
545 * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
546 * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
547 * CM_WKUP_CLKSTCTRL
548 */ 534 */
549#define OMAP4430_CLKTRCTRL_SHIFT 0 535#define OMAP4430_CLKTRCTRL_SHIFT 0
550#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 536#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
@@ -561,10 +547,7 @@
561#define OMAP4430_CUSTOM_SHIFT 6 547#define OMAP4430_CUSTOM_SHIFT 6
562#define OMAP4430_CUSTOM_MASK (0x3 << 6) 548#define OMAP4430_CUSTOM_MASK (0x3 << 6)
563 549
564/* 550/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
565 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
566 * CM_L4CFG_DYNAMICDEP_RESTORE
567 */
568#define OMAP4430_D2D_DYNDEP_SHIFT 18 551#define OMAP4430_D2D_DYNDEP_SHIFT 18
569#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) 552#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
570 553
@@ -574,31 +557,29 @@
574 557
575/* 558/*
576 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 559 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
577 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, 560 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
578 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, 561 * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
579 * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 562 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
580 * CM_SSC_DELTAMSTEP_DPLL_USB
581 */ 563 */
582#define OMAP4430_DELTAMSTEP_SHIFT 0 564#define OMAP4430_DELTAMSTEP_SHIFT 0
583#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 565#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
584 566
585/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 567/* Used by CM_DLL_CTRL */
586#define OMAP4430_DLL_OVERRIDE_SHIFT 2 568#define OMAP4430_DLL_OVERRIDE_SHIFT 0
587#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) 569#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
588 570
589/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 571/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
590#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 572#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
591#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) 573#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
592 574
593/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 575/* Used by CM_SHADOW_FREQ_CONFIG1 */
594#define OMAP4430_DLL_RESET_SHIFT 3 576#define OMAP4430_DLL_RESET_SHIFT 3
595#define OMAP4430_DLL_RESET_MASK (1 << 3) 577#define OMAP4430_DLL_RESET_MASK (1 << 3)
596 578
597/* 579/*
598 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 580 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
599 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 581 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
600 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 582 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
601 * CM_CLKSEL_DPLL_USB
602 */ 583 */
603#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 584#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
604#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) 585#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
@@ -607,28 +588,19 @@
607#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 588#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
608#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 589#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
609 590
610/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ 591/* Used by CM_CLKSEL_DPLL_CORE */
611#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 592#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
612#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 593#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
613 594
614/* 595/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
615 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
616 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
617 */
618#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 596#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
619#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 597#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
620 598
621/* 599/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
622 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
623 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
624 */
625#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 600#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
626#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) 601#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
627 602
628/* 603/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
629 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
630 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
631 */
632#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 604#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
633#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) 605#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
634 606
@@ -637,9 +609,8 @@
637#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 609#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
638 610
639/* 611/*
640 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 612 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
641 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 613 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
642 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
643 */ 614 */
644#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 615#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
645#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 616#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
@@ -649,9 +620,8 @@
649#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 620#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
650 621
651/* 622/*
652 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 623 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
653 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 624 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
654 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
655 */ 625 */
656#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 626#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
657#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 627#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
@@ -661,29 +631,28 @@
661#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) 631#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
662 632
663/* 633/*
664 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 634 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
665 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 635 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
666 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
667 */ 636 */
668#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 637#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
669#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 638#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
670 639
671/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 640/* Used by CM_SHADOW_FREQ_CONFIG1 */
672#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 641#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
673#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 642#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
674 643
675/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 644/* Used by CM_SHADOW_FREQ_CONFIG1 */
676#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 645#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
677#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 646#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
678 647
679/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 648/* Used by CM_SHADOW_FREQ_CONFIG2 */
680#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 649#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
681#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) 650#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
682 651
683/* 652/*
684 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 653 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
685 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 654 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
686 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 655 * CM_CLKSEL_DPLL_UNIPRO
687 */ 656 */
688#define OMAP4430_DPLL_DIV_SHIFT 0 657#define OMAP4430_DPLL_DIV_SHIFT 0
689#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 658#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
@@ -693,9 +662,8 @@
693#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 662#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
694 663
695/* 664/*
696 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 665 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
697 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 666 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
698 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
699 */ 667 */
700#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 668#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
701#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 669#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
@@ -705,26 +673,25 @@
705#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) 673#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
706 674
707/* 675/*
708 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 676 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
709 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 677 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
710 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 678 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
711 * CM_CLKMODE_DPLL_USB
712 */ 679 */
713#define OMAP4430_DPLL_EN_SHIFT 0 680#define OMAP4430_DPLL_EN_SHIFT 0
714#define OMAP4430_DPLL_EN_MASK (0x7 << 0) 681#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
715 682
716/* 683/*
717 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 684 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
718 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 685 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
719 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 686 * CM_CLKMODE_DPLL_UNIPRO
720 */ 687 */
721#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 688#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
722#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 689#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
723 690
724/* 691/*
725 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 692 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
726 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 693 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
727 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 694 * CM_CLKSEL_DPLL_UNIPRO
728 */ 695 */
729#define OMAP4430_DPLL_MULT_SHIFT 8 696#define OMAP4430_DPLL_MULT_SHIFT 8
730#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 697#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
@@ -734,9 +701,9 @@
734#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 701#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
735 702
736/* 703/*
737 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 704 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
738 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 705 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
739 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 706 * CM_CLKMODE_DPLL_UNIPRO
740 */ 707 */
741#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 708#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
742#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 709#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
@@ -746,55 +713,46 @@
746#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 713#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
747 714
748/* 715/*
749 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 716 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
750 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 717 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
751 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 718 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
752 * CM_CLKMODE_DPLL_USB
753 */ 719 */
754#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 720#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
755#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) 721#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
756 722
757/* 723/*
758 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 724 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
759 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 725 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
760 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 726 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
761 * CM_CLKMODE_DPLL_USB
762 */ 727 */
763#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 728#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
764#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 729#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
765 730
766/* 731/*
767 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 732 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
768 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 733 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
769 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 734 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
770 * CM_CLKMODE_DPLL_USB
771 */ 735 */
772#define OMAP4430_DPLL_SSC_EN_SHIFT 12 736#define OMAP4430_DPLL_SSC_EN_SHIFT 12
773#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) 737#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
774 738
775/* 739/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
776 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
777 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
778 */
779#define OMAP4430_DSS_DYNDEP_SHIFT 8 740#define OMAP4430_DSS_DYNDEP_SHIFT 8
780#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) 741#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
781 742
782/* 743/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
783 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
784 * CM_SDMA_STATICDEP_RESTORE
785 */
786#define OMAP4430_DSS_STATDEP_SHIFT 8 744#define OMAP4430_DSS_STATDEP_SHIFT 8
787#define OMAP4430_DSS_STATDEP_MASK (1 << 8) 745#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
788 746
789/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 747/* Used by CM_L3_2_DYNAMICDEP */
790#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 748#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
791#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) 749#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
792 750
793/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ 751/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
794#define OMAP4430_DUCATI_STATDEP_SHIFT 0 752#define OMAP4430_DUCATI_STATDEP_SHIFT 0
795#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) 753#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
796 754
797/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 755/* Used by CM_SHADOW_FREQ_CONFIG1 */
798#define OMAP4430_FREQ_UPDATE_SHIFT 0 756#define OMAP4430_FREQ_UPDATE_SHIFT 0
799#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) 757#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
800 758
@@ -802,7 +760,7 @@
802#define OMAP4430_FUNC_SHIFT 16 760#define OMAP4430_FUNC_SHIFT 16
803#define OMAP4430_FUNC_MASK (0xfff << 16) 761#define OMAP4430_FUNC_MASK (0xfff << 16)
804 762
805/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 763/* Used by CM_L3_2_DYNAMICDEP */
806#define OMAP4430_GFX_DYNDEP_SHIFT 10 764#define OMAP4430_GFX_DYNDEP_SHIFT 10
807#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) 765#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
808 766
@@ -810,119 +768,95 @@
810#define OMAP4430_GFX_STATDEP_SHIFT 10 768#define OMAP4430_GFX_STATDEP_SHIFT 10
811#define OMAP4430_GFX_STATDEP_MASK (1 << 10) 769#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
812 770
813/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 771/* Used by CM_SHADOW_FREQ_CONFIG2 */
814#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 772#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
815#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) 773#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
816 774
817/* 775/*
818 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 776 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
819 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 777 * CM_DIV_M4_DPLL_PER
820 */ 778 */
821#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 779#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
822#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 780#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
823 781
824/* 782/*
825 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 783 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
826 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 784 * CM_DIV_M4_DPLL_PER
827 */ 785 */
828#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 786#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
829#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 787#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
830 788
831/* 789/*
832 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 790 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
833 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 791 * CM_DIV_M4_DPLL_PER
834 */ 792 */
835#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 793#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
836#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 794#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
837 795
838/* 796/*
839 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 797 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
840 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 798 * CM_DIV_M4_DPLL_PER
841 */ 799 */
842#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 800#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
843#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 801#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
844 802
845/* 803/*
846 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 804 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
847 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 805 * CM_DIV_M5_DPLL_PER
848 */ 806 */
849#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 807#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
850#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 808#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
851 809
852/* 810/*
853 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 811 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
854 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 812 * CM_DIV_M5_DPLL_PER
855 */ 813 */
856#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 814#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
857#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 815#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
858 816
859/* 817/*
860 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 818 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
861 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 819 * CM_DIV_M5_DPLL_PER
862 */ 820 */
863#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 821#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
864#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 822#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
865 823
866/* 824/*
867 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 825 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
868 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 826 * CM_DIV_M5_DPLL_PER
869 */ 827 */
870#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 828#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
871#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 829#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
872 830
873/* 831/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
874 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
875 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
876 */
877#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 832#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
878#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 833#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
879 834
880/* 835/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
881 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
882 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
883 */
884#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 836#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
885#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 837#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
886 838
887/* 839/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
888 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
889 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
890 */
891#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 840#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
892#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 841#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
893 842
894/* 843/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
895 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
896 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
897 */
898#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 844#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
899#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 845#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
900 846
901/* 847/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
902 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
903 * CM_DIV_M7_DPLL_PER
904 */
905#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 848#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
906#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 849#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
907 850
908/* 851/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
909 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
910 * CM_DIV_M7_DPLL_PER
911 */
912#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 852#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
913#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) 853#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
914 854
915/* 855/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
916 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
917 * CM_DIV_M7_DPLL_PER
918 */
919#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 856#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
920#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) 857#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
921 858
922/* 859/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
923 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
924 * CM_DIV_M7_DPLL_PER
925 */
926#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 860#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
927#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) 861#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
928 862
@@ -934,8 +868,7 @@
934 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 868 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
935 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 869 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
936 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 870 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
937 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 871 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
938 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
939 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 872 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
940 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 873 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
941 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 874 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -944,30 +877,24 @@
944 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 877 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
945 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 878 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
946 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 879 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
947 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 880 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
948 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 881 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
949 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 882 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
950 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
951 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
952 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
953 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 883 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
954 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 884 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
955 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 885 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
956 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 886 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
957 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 887 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
958 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 888 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
959 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 889 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
960 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 890 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
961 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 891 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
962 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 892 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
963 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 893 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
964 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 894 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
965 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 895 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
966 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 896 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
967 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 897 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
968 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
969 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
970 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
971 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 898 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
972 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 899 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
973 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 900 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -983,166 +910,148 @@
983#define OMAP4430_IDLEST_SHIFT 16 910#define OMAP4430_IDLEST_SHIFT 16
984#define OMAP4430_IDLEST_MASK (0x3 << 16) 911#define OMAP4430_IDLEST_MASK (0x3 << 16)
985 912
986/* 913/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
987 * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
988 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
989 */
990#define OMAP4430_ISS_DYNDEP_SHIFT 9 914#define OMAP4430_ISS_DYNDEP_SHIFT 9
991#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) 915#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
992 916
993/* 917/*
994 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 918 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
995 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 919 * CM_TESLA_STATICDEP
996 */ 920 */
997#define OMAP4430_ISS_STATDEP_SHIFT 9 921#define OMAP4430_ISS_STATDEP_SHIFT 9
998#define OMAP4430_ISS_STATDEP_MASK (1 << 9) 922#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
999 923
1000/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ 924/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
1001#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 925#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
1002#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) 926#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
1003 927
1004/* 928/*
1005 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 929 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1006 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, 930 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
1007 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 931 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1008 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1009 */ 932 */
1010#define OMAP4430_IVAHD_STATDEP_SHIFT 2 933#define OMAP4430_IVAHD_STATDEP_SHIFT 2
1011#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) 934#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
1012 935
1013/* 936/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1014 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1015 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1016 */
1017#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 937#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
1018#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) 938#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
1019 939
1020/* 940/*
1021 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 941 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
1022 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 942 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1023 * CM_TESLA_STATICDEP
1024 */ 943 */
1025#define OMAP4430_L3INIT_STATDEP_SHIFT 7 944#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1026#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) 945#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
1027 946
1028/* 947/*
1029 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, 948 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1030 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 949 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1031 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1032 */ 950 */
1033#define OMAP4430_L3_1_DYNDEP_SHIFT 5 951#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1034#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) 952#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
1035 953
1036/* 954/*
1037 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 955 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1038 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 956 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1039 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 957 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1040 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 958 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1041 */ 959 */
1042#define OMAP4430_L3_1_STATDEP_SHIFT 5 960#define OMAP4430_L3_1_STATDEP_SHIFT 5
1043#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) 961#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
1044 962
1045/* 963/*
1046 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, 964 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
1047 * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, 965 * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
1048 * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, 966 * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1049 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 967 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1050 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1051 */ 968 */
1052#define OMAP4430_L3_2_DYNDEP_SHIFT 6 969#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1053#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) 970#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
1054 971
1055/* 972/*
1056 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 973 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1057 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 974 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1058 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 975 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1059 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 976 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1060 */ 977 */
1061#define OMAP4430_L3_2_STATDEP_SHIFT 6 978#define OMAP4430_L3_2_STATDEP_SHIFT 6
1062#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) 979#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1063 980
1064/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ 981/* Used by CM_L3_1_DYNAMICDEP */
1065#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 982#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1066#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) 983#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1067 984
1068/* 985/*
1069 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 986 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1070 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 987 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1071 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1072 */ 988 */
1073#define OMAP4430_L4CFG_STATDEP_SHIFT 12 989#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1074#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) 990#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1075 991
1076/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 992/* Used by CM_L3_2_DYNAMICDEP */
1077#define OMAP4430_L4PER_DYNDEP_SHIFT 13 993#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1078#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) 994#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1079 995
1080/* 996/*
1081 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 997 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1082 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 998 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1083 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1084 */ 999 */
1085#define OMAP4430_L4PER_STATDEP_SHIFT 13 1000#define OMAP4430_L4PER_STATDEP_SHIFT 13
1086#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) 1001#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1087 1002
1088/* 1003/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1089 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1090 * CM_L4PER_DYNAMICDEP_RESTORE
1091 */
1092#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1004#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1093#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) 1005#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1094 1006
1095/* 1007/*
1096 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1008 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1097 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE 1009 * CM_SDMA_STATICDEP
1098 */ 1010 */
1099#define OMAP4430_L4SEC_STATDEP_SHIFT 14 1011#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1100#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) 1012#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1101 1013
1102/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1014/* Used by CM_L4CFG_DYNAMICDEP */
1103#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1015#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1104#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) 1016#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1105 1017
1106/* 1018/*
1107 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1019 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1108 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1020 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1109 */ 1021 */
1110#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1022#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1111#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) 1023#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1112 1024
1113/* 1025/*
1114 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, 1026 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1115 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1027 * CM_MPU_DYNAMICDEP
1116 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1117 */ 1028 */
1118#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1029#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1119#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) 1030#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1120 1031
1121/* 1032/*
1122 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1033 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1123 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1034 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1124 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1035 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1125 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1036 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1126 */ 1037 */
1127#define OMAP4430_MEMIF_STATDEP_SHIFT 4 1038#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1128#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) 1039#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1129 1040
1130/* 1041/*
1131 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1042 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1132 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1043 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1133 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1044 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1134 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1045 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1135 * CM_SSC_MODFREQDIV_DPLL_USB
1136 */ 1046 */
1137#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1047#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1138#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1048#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1139 1049
1140/* 1050/*
1141 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1051 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1142 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1052 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1143 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1053 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1144 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1054 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1145 * CM_SSC_MODFREQDIV_DPLL_USB
1146 */ 1055 */
1147#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1056#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1148#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1057#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
@@ -1155,8 +1064,7 @@
1155 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1064 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1156 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1065 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1157 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1066 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1158 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 1067 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
1159 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1160 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1068 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1161 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1069 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1162 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1070 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -1165,30 +1073,24 @@
1165 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1073 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1166 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1074 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1167 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1075 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1168 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1076 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1169 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1077 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
1170 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 1078 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
1171 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1172 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1173 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1174 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 1079 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1175 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 1080 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1176 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 1081 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1177 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1082 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1178 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1083 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1179 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1084 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1180 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1085 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1181 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1086 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1182 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1087 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
1183 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 1088 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
1184 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1089 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
1185 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 1090 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
1186 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 1091 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
1187 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 1092 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
1188 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 1093 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1189 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1190 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1191 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1192 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1094 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1193 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1095 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1194 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1096 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -1221,11 +1123,9 @@
1221#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1123#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1222 1124
1223/* 1125/*
1224 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1126 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1225 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1127 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1226 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1128 * CM_WKUP_GPIO1_CLKCTRL
1227 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1228 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1229 */ 1129 */
1230#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1130#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1231#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) 1131#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
@@ -1254,23 +1154,23 @@
1254#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1154#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1255#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) 1155#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1256 1156
1257/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1157/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1258#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1158#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1259#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) 1159#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1260 1160
1261/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1161/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1262#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1162#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1263#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1163#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1264 1164
1265/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1165/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1266#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1166#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1267#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1167#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1268 1168
1269/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1169/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1270#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1170#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1271#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1171#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1272 1172
1273/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1173/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1274#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1174#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1275#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1175#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1276 1176
@@ -1306,27 +1206,27 @@
1306#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1206#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1307#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) 1207#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1308 1208
1309/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1209/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1310#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1210#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1311#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1211#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1312 1212
1313/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1213/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1314#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1214#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1315#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1215#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1316 1216
1317/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1217/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1318#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1218#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1319#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1219#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1320 1220
1321/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1221/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1322#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1222#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1323#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1223#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1324 1224
1325/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1225/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1326#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1226#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1327#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1227#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1328 1228
1329/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1229/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1330#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1230#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1331#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1231#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1332 1232
@@ -1374,7 +1274,7 @@
1374#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1274#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1375#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) 1275#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1376 1276
1377/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ 1277/* Used by CM_DYN_DEP_PRESCAL */
1378#define OMAP4430_PRESCAL_SHIFT 0 1278#define OMAP4430_PRESCAL_SHIFT 0
1379#define OMAP4430_PRESCAL_MASK (0x3f << 0) 1279#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1380 1280
@@ -1382,10 +1282,7 @@
1382#define OMAP4430_R_RTL_SHIFT 11 1282#define OMAP4430_R_RTL_SHIFT 11
1383#define OMAP4430_R_RTL_MASK (0x1f << 11) 1283#define OMAP4430_R_RTL_MASK (0x1f << 11)
1384 1284
1385/* 1285/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1386 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1387 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1388 */
1389#define OMAP4430_SAR_MODE_SHIFT 4 1286#define OMAP4430_SAR_MODE_SHIFT 4
1390#define OMAP4430_SAR_MODE_MASK (1 << 4) 1287#define OMAP4430_SAR_MODE_MASK (1 << 4)
1391 1288
@@ -1397,7 +1294,7 @@
1397#define OMAP4430_SCHEME_SHIFT 30 1294#define OMAP4430_SCHEME_SHIFT 30
1398#define OMAP4430_SCHEME_MASK (0x3 << 30) 1295#define OMAP4430_SCHEME_MASK (0x3 << 30)
1399 1296
1400/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1297/* Used by CM_L4CFG_DYNAMICDEP */
1401#define OMAP4430_SDMA_DYNDEP_SHIFT 11 1298#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1402#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) 1299#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1403 1300
@@ -1417,10 +1314,10 @@
1417 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1314 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1418 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1315 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1419 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1316 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1420 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1317 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1421 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1318 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
1422 * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1319 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1423 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL 1320 * CM_TESLA_TESLA_CLKCTRL
1424 */ 1321 */
1425#define OMAP4430_STBYST_SHIFT 18 1322#define OMAP4430_STBYST_SHIFT 18
1426#define OMAP4430_STBYST_MASK (1 << 18) 1323#define OMAP4430_STBYST_MASK (1 << 18)
@@ -1438,17 +1335,13 @@
1438#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1335#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1439 1336
1440/* 1337/*
1441 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 1338 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
1442 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 1339 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1443 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1444 */ 1340 */
1445#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1341#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1446#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) 1342#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1447 1343
1448/* 1344/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1449 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1450 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1451 */
1452#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1345#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1453#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) 1346#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1454 1347
@@ -1457,30 +1350,24 @@
1457#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) 1350#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1458 1351
1459/* 1352/*
1460 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 1353 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
1461 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 1354 * CM_DIV_M4_DPLL_PER
1462 */ 1355 */
1463#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1356#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1464#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 1357#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1465 1358
1466/* 1359/*
1467 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 1360 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1468 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 1361 * CM_DIV_M5_DPLL_PER
1469 */ 1362 */
1470#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1363#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1471#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 1364#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1472 1365
1473/* 1366/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1474 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1475 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1476 */
1477#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1367#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1478#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 1368#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1479 1369
1480/* 1370/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1481 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1482 * CM_DIV_M7_DPLL_PER
1483 */
1484#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1371#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1485#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) 1372#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1486 1373
@@ -1496,7 +1383,7 @@
1496#define OMAP4430_SYS_CLKSEL_SHIFT 0 1383#define OMAP4430_SYS_CLKSEL_SHIFT 0
1497#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) 1384#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1498 1385
1499/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1386/* Used by CM_L4CFG_DYNAMICDEP */
1500#define OMAP4430_TESLA_DYNDEP_SHIFT 1 1387#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1501#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) 1388#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1502 1389
@@ -1505,11 +1392,9 @@
1505#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) 1392#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1506 1393
1507/* 1394/*
1508 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, 1395 * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1509 * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, 1396 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1510 * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1397 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1511 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1512 * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1513 */ 1398 */
1514#define OMAP4430_WINDOWSIZE_SHIFT 24 1399#define OMAP4430_WINDOWSIZE_SHIFT 24
1515#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) 1400#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 23:09:19 -0400