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authorJon Hunter <jon-hunter@ti.com>2011-10-07 02:53:09 -0400
committerPaul Walmsley <paul@pwsan.com>2011-10-07 03:06:48 -0400
commitcf2a82d7462e8c728260ee09e46c573fab2f89cf (patch)
tree5937a03d039c2713de65926c14a3b039001faa49 /arch/arm/mach-omap2/clock44xx_data.c
parent52a3a4d4610cfad536b8ac94b9a2f5ebfa51c06b (diff)
ARM: OMAP4: clock: Add missing clock divider for OCP_ABE_ICLK
The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the parent clock of the AESS_FCLK is the ABE_FCLK... ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which determine their operational frequency. However, the dividers for the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit, which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2. Similarly, when this bit is set to 1, the AESS_FCLK divider is 2 and the OCP_ABE_ICLK is 1. The above relationship between the AESS_FCLK and OCP_ABE_ICLK dividers ensure that the OCP_ABE_ICLK clock is always half the frequency of the ABE_CLK... OCP_ABE_ICLK = ABE_FCLK/2 The divider for the OCP_ABE_ICLK is currently missing so add a divider that will ensure the OCP_ABE_ICLK frequency is always half the ABE_FCLK frequency. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 7b028ecce37..a145e322635 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1195,11 +1195,25 @@ static struct clk l4_wkup_clk_mux_ck = {
1195 .recalc = &omap2_clksel_recalc, 1195 .recalc = &omap2_clksel_recalc,
1196}; 1196};
1197 1197
1198static const struct clksel_rate div2_2to1_rates[] = {
1199 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1200 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1201 { .div = 0 },
1202};
1203
1204static const struct clksel ocp_abe_iclk_div[] = {
1205 { .parent = &aess_fclk, .rates = div2_2to1_rates },
1206 { .parent = NULL },
1207};
1208
1198static struct clk ocp_abe_iclk = { 1209static struct clk ocp_abe_iclk = {
1199 .name = "ocp_abe_iclk", 1210 .name = "ocp_abe_iclk",
1200 .parent = &aess_fclk, 1211 .parent = &aess_fclk,
1212 .clksel = ocp_abe_iclk_div,
1213 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1214 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1201 .ops = &clkops_null, 1215 .ops = &clkops_null,
1202 .recalc = &followparent_recalc, 1216 .recalc = &omap2_clksel_recalc,
1203}; 1217};
1204 1218
1205static struct clk per_abe_24m_fclk = { 1219static struct clk per_abe_24m_fclk = {