ARM: omap: clk: add clk_prepare and clk_unprepare

As part of Common Clk Framework (CCF) the clk_enable() operation
was split into a clk_prepare() which could sleep, and a clk_enable()
which should never sleep. Similarly the clk_disable() was
split into clk_disable() and clk_unprepare(). This was
needed to handle complex cases where in a clk gate/ungate
would require a slow and a fast part to be implemented.
None of the clocks below seem to be in the 'complex' clocks
category and are just simple clocks which are enabled/disabled
through simple register writes.
Most of the instances also seem to be called in non-atomic
context which means its safe to move all of those from
using a clk_enable() to clk_prepare_enable() and clk_disable() to
clk_disable_unprepare().

For some others, mainly the ones handled through the hwmod framework
there is a possibility that they get called in either an atomic
or a non-atomic context.

The way these get handled below work only as long as clk_prepare
is implemented as a no-op (which is the case today) since this gets
called very early at boot while most subsystems are unavailable.
Hence these are marked with a *HACK* comment, which says we need
to re-visit these once we start doing something meaningful with
clk_prepare/clk_unprepare like doing voltage scaling or something
that involves i2c.

This is in preparation of OMAP moving to CCF.

Based on initial changes from Mike Turquette.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index fc2765bcdd4..319ff52220b 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -64,15 +64,15 @@ void __init omap3_clk_lock_dpll5(void)
 
         dpll5_clk = clk_get(NULL, "dpll5_ck");
         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_enable(dpll5_clk);
+        clk_prepare_enable(dpll5_clk);
 
         /* Program dpll5_m2_clk divider for no division */
         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-        clk_enable(dpll5_m2_clk);
+        clk_prepare_enable(dpll5_m2_clk);
         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 
-        clk_disable(dpll5_m2_clk);
-        clk_disable(dpll5_clk);
+        clk_disable_unprepare(dpll5_m2_clk);
+        clk_disable_unprepare(dpll5_clk);
         return;
 }