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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-01-13 10:00:22 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-13 10:00:22 -0500
commit4de3a8e101150feaefa1139611a50ff37467f33e (patch)
treedaada742542518b02d7db7c5d32e715eaa5f166d /arch/arm/mach-msm
parent294064f58953f9964e5945424b09c51800330a83 (diff)
parent099469502f62fbe0d7e4f0b83a2f22538367f734 (diff)
Merge branch 'master' into fixes
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/Kconfig35
-rw-r--r--arch/arm/mach-msm/board-sapphire.c2
-rw-r--r--arch/arm/mach-msm/include/mach/debug-macro.S51
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h12
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h12
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8960.h5
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h12
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h5
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h12
-rw-r--r--arch/arm/mach-msm/include/mach/uncompress.h39
-rw-r--r--arch/arm/mach-msm/io.c15
-rw-r--r--arch/arm/mach-msm/platsmp.c2
-rw-r--r--arch/arm/mach-msm/smd_debug.c2
-rw-r--r--arch/arm/mach-msm/timer.c347
14 files changed, 227 insertions, 324 deletions
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index e6beaff7621..1cd40ad301d 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -13,7 +13,6 @@ config ARCH_MSM7X00A
13 select CPU_V6 13 select CPU_V6
14 select GPIO_MSM_V1 14 select GPIO_MSM_V1
15 select MSM_PROC_COMM 15 select MSM_PROC_COMM
16 select HAS_MSM_DEBUG_UART_PHYS
17 16
18config ARCH_MSM7X30 17config ARCH_MSM7X30
19 bool "MSM7x30" 18 bool "MSM7x30"
@@ -25,7 +24,6 @@ config ARCH_MSM7X30
25 select MSM_GPIOMUX 24 select MSM_GPIOMUX
26 select GPIO_MSM_V1 25 select GPIO_MSM_V1
27 select MSM_PROC_COMM 26 select MSM_PROC_COMM
28 select HAS_MSM_DEBUG_UART_PHYS
29 27
30config ARCH_QSD8X50 28config ARCH_QSD8X50
31 bool "QSD8X50" 29 bool "QSD8X50"
@@ -37,7 +35,6 @@ config ARCH_QSD8X50
37 select MSM_GPIOMUX 35 select MSM_GPIOMUX
38 select GPIO_MSM_V1 36 select GPIO_MSM_V1
39 select MSM_PROC_COMM 37 select MSM_PROC_COMM
40 select HAS_MSM_DEBUG_UART_PHYS
41 38
42config ARCH_MSM8X60 39config ARCH_MSM8X60
43 bool "MSM8X60" 40 bool "MSM8X60"
@@ -63,6 +60,9 @@ config ARCH_MSM8960
63 60
64endchoice 61endchoice
65 62
63config MSM_HAS_DEBUG_UART_HS
64 bool
65
66config MSM_SOC_REV_A 66config MSM_SOC_REV_A
67 bool 67 bool
68config ARCH_MSM_SCORPIONMP 68config ARCH_MSM_SCORPIONMP
@@ -74,9 +74,6 @@ config ARCH_MSM_ARM11
74config ARCH_MSM_SCORPION 74config ARCH_MSM_SCORPION
75 bool 75 bool
76 76
77config HAS_MSM_DEBUG_UART_PHYS
78 bool
79
80config MSM_VIC 77config MSM_VIC
81 bool 78 bool
82 79
@@ -153,32 +150,6 @@ config MACH_MSM8960_RUMI3
153 150
154endmenu 151endmenu
155 152
156config MSM_DEBUG_UART
157 int
158 default 1 if MSM_DEBUG_UART1
159 default 2 if MSM_DEBUG_UART2
160 default 3 if MSM_DEBUG_UART3
161
162if HAS_MSM_DEBUG_UART_PHYS
163choice
164 prompt "Debug UART"
165
166 default MSM_DEBUG_UART_NONE
167
168 config MSM_DEBUG_UART_NONE
169 bool "None"
170
171 config MSM_DEBUG_UART1
172 bool "UART1"
173
174 config MSM_DEBUG_UART2
175 bool "UART2"
176
177 config MSM_DEBUG_UART3
178 bool "UART3"
179endchoice
180endif
181
182config MSM_SMD_PKG3 153config MSM_SMD_PKG3
183 bool 154 bool
184 155
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 32b465763db..97b8191d9d3 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -18,7 +18,7 @@
18#include <linux/input.h> 18#include <linux/input.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/sysdev.h> 21#include <linux/device.h>
22 22
23#include <linux/delay.h> 23#include <linux/delay.h>
24 24
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 2dc73ccddb1..3ffd8668c9a 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -1,6 +1,7 @@
1/* arch/arm/mach-msm7200/include/mach/debug-macro.S 1/*
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 5 * Author: Brian Swetland <swetland@google.com>
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
@@ -14,40 +15,52 @@
14 * 15 *
15 */ 16 */
16 17
17
18
19#include <mach/hardware.h> 18#include <mach/hardware.h>
20#include <mach/msm_iomap.h> 19#include <mach/msm_iomap.h>
21 20
22#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
23 .macro addruart, rp, rv, tmp 21 .macro addruart, rp, rv, tmp
22#ifdef MSM_DEBUG_UART_PHYS
24 ldr \rp, =MSM_DEBUG_UART_PHYS 23 ldr \rp, =MSM_DEBUG_UART_PHYS
25 ldr \rv, =MSM_DEBUG_UART_BASE 24 ldr \rv, =MSM_DEBUG_UART_BASE
25#endif
26 .endm 26 .endm
27 27
28 .macro senduart,rd,rx 28 .macro senduart, rd, rx
29#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
30 @ Write the 1 character to UARTDM_TF
31 str \rd, [\rx, #0x70]
32#else
29 teq \rx, #0 33 teq \rx, #0
30 strne \rd, [\rx, #0x0C] 34 strne \rd, [\rx, #0x0C]
35#endif
31 .endm 36 .endm
32 37
33 .macro waituart,rd,rx 38 .macro waituart, rd, rx
39#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
40 @ check for TX_EMT in UARTDM_SR
41 ldr \rd, [\rx, #0x08]
42 tst \rd, #0x08
43 bne 1002f
44 @ wait for TXREADY in UARTDM_ISR
451001: ldr \rd, [\rx, #0x14]
46 tst \rd, #0x80
47 beq 1001b
481002:
49 @ Clear TX_READY by writing to the UARTDM_CR register
50 mov \rd, #0x300
51 str \rd, [\rx, #0x10]
52 @ Write 0x1 to NCF register
53 mov \rd, #0x1
54 str \rd, [\rx, #0x40]
55 @ UARTDM reg. Read to induce delay
56 ldr \rd, [\rx, #0x08]
57#else
34 @ wait for TX_READY 58 @ wait for TX_READY
351001: ldr \rd, [\rx, #0x08] 591001: ldr \rd, [\rx, #0x08]
36 tst \rd, #0x04 60 tst \rd, #0x04
37 beq 1001b 61 beq 1001b
38 .endm
39#else
40 .macro addruart, rp, rv, tmp
41 mov \rv, #0xff000000
42 orr \rv, \rv, #0x00f00000
43 .endm
44
45 .macro senduart,rd,rx
46 .endm
47
48 .macro waituart,rd,rx
49 .endm
50#endif 62#endif
63 .endm
51 64
52 .macro busyuart,rd,rx 65 .macro busyuart, rd, rx
53 .endm 66 .endm
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 94fe9fe6feb..8af46123dab 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -78,18 +78,6 @@
78#define MSM_UART3_PHYS 0xA9C00000 78#define MSM_UART3_PHYS 0xA9C00000
79#define MSM_UART3_SIZE SZ_4K 79#define MSM_UART3_SIZE SZ_4K
80 80
81#ifdef CONFIG_MSM_DEBUG_UART
82#define MSM_DEBUG_UART_BASE 0xE1000000
83#if CONFIG_MSM_DEBUG_UART == 1
84#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
85#elif CONFIG_MSM_DEBUG_UART == 2
86#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
87#elif CONFIG_MSM_DEBUG_UART == 3
88#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
89#endif
90#define MSM_DEBUG_UART_SIZE SZ_4K
91#endif
92
93#define MSM_SDC1_PHYS 0xA0400000 81#define MSM_SDC1_PHYS 0xA0400000
94#define MSM_SDC1_SIZE SZ_4K 82#define MSM_SDC1_SIZE SZ_4K
95 83
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 37694442d1b..198202c267c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -89,18 +89,6 @@
89#define MSM_UART3_PHYS 0xACC00000 89#define MSM_UART3_PHYS 0xACC00000
90#define MSM_UART3_SIZE SZ_4K 90#define MSM_UART3_SIZE SZ_4K
91 91
92#ifdef CONFIG_MSM_DEBUG_UART
93#define MSM_DEBUG_UART_BASE 0xE1000000
94#if CONFIG_MSM_DEBUG_UART == 1
95#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
96#elif CONFIG_MSM_DEBUG_UART == 2
97#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
98#elif CONFIG_MSM_DEBUG_UART == 3
99#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
100#endif
101#define MSM_DEBUG_UART_SIZE SZ_4K
102#endif
103
104#define MSM_MDC_BASE IOMEM(0xE0200000) 92#define MSM_MDC_BASE IOMEM(0xE0200000)
105#define MSM_MDC_PHYS 0xAA500000 93#define MSM_MDC_PHYS 0xAA500000
106#define MSM_MDC_SIZE SZ_1M 94#define MSM_MDC_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 3c9d9602a31..800b55767e6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -45,4 +45,9 @@
45#define MSM8960_TMR0_PHYS 0x0208A000 45#define MSM8960_TMR0_PHYS 0x0208A000
46#define MSM8960_TMR0_SIZE SZ_4K 46#define MSM8960_TMR0_SIZE SZ_4K
47 47
48#ifdef CONFIG_DEBUG_MSM8960_UART
49#define MSM_DEBUG_UART_BASE 0xE1040000
50#define MSM_DEBUG_UART_PHYS 0x16440000
51#endif
52
48#endif 53#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index d67cd73316f..0faa894729b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -83,18 +83,6 @@
83#define MSM_UART3_PHYS 0xA9C00000 83#define MSM_UART3_PHYS 0xA9C00000
84#define MSM_UART3_SIZE SZ_4K 84#define MSM_UART3_SIZE SZ_4K
85 85
86#ifdef CONFIG_MSM_DEBUG_UART
87#define MSM_DEBUG_UART_BASE 0xE1000000
88#if CONFIG_MSM_DEBUG_UART == 1
89#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
90#elif CONFIG_MSM_DEBUG_UART == 2
91#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
92#elif CONFIG_MSM_DEBUG_UART == 3
93#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
94#endif
95#define MSM_DEBUG_UART_SIZE SZ_4K
96#endif
97
98#define MSM_MDC_BASE IOMEM(0xE0200000) 86#define MSM_MDC_BASE IOMEM(0xE0200000)
99#define MSM_MDC_PHYS 0xAA500000 87#define MSM_MDC_PHYS 0xAA500000
100#define MSM_MDC_SIZE SZ_1M 88#define MSM_MDC_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 3b19b8f244b..54e12caa8d8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -62,4 +62,9 @@
62#define MSM8X60_TMR0_PHYS 0x02040000 62#define MSM8X60_TMR0_PHYS 0x02040000
63#define MSM8X60_TMR0_SIZE SZ_4K 63#define MSM8X60_TMR0_SIZE SZ_4K
64 64
65#ifdef CONFIG_DEBUG_MSM8660_UART
66#define MSM_DEBUG_UART_BASE 0xE1040000
67#define MSM_DEBUG_UART_PHYS 0x19C40000
68#endif
69
65#endif 70#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 4ded15238b6..90682f4599d 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,18 @@
55 55
56#include "msm_iomap-8960.h" 56#include "msm_iomap-8960.h"
57 57
58#define MSM_DEBUG_UART_SIZE SZ_4K
59#if defined(CONFIG_DEBUG_MSM_UART1)
60#define MSM_DEBUG_UART_BASE 0xE1000000
61#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
62#elif defined(CONFIG_DEBUG_MSM_UART2)
63#define MSM_DEBUG_UART_BASE 0xE1000000
64#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
65#elif defined(CONFIG_DEBUG_MSM_UART3)
66#define MSM_DEBUG_UART_BASE 0xE1000000
67#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
68#endif
69
58/* Virtual addresses shared across all MSM targets. */ 70/* Virtual addresses shared across all MSM targets. */
59#define MSM_CSR_BASE IOMEM(0xE0001000) 71#define MSM_CSR_BASE IOMEM(0xE0001000)
60#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) 72#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index d94292c29d8..169a8400745 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -1,6 +1,6 @@
1/* arch/arm/mach-msm/include/mach/uncompress.h 1/*
2 *
3 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -14,17 +14,40 @@
14 */ 14 */
15 15
16#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H 16#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
17#define __ASM_ARCH_MSM_UNCOMPRESS_H
18
19#include <asm/processor.h>
20#include <mach/msm_iomap.h>
21
22#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
23#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
17 24
18#include "hardware.h" 25#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
19#include "linux/io.h" 26#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
20#include "mach/msm_iomap.h" 27#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
28#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
29#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
21 30
22static void putc(int c) 31static void putc(int c)
23{ 32{
24#if defined(MSM_DEBUG_UART_PHYS) 33#if defined(MSM_DEBUG_UART_PHYS)
25 unsigned base = MSM_DEBUG_UART_PHYS; 34#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
26 while (!(readl(base + 0x08) & 0x04)) ; 35 /*
27 writel(c, base + 0x0c); 36 * Wait for TX_READY to be set; but skip it if we have a
37 * TX underrun.
38 */
39 if (UART_DM_SR & 0x08)
40 while (!(UART_DM_ISR & 0x80))
41 cpu_relax();
42
43 UART_DM_CR = 0x300;
44 UART_DM_NCHAR = 0x1;
45 UART_DM_TF = c;
46#else
47 while (!(UART_CSR & 0x04))
48 cpu_relax();
49 UART_TF = c;
50#endif
28#endif 51#endif
29} 52}
30 53
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 8759ecf7454..578b04e42de 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -47,7 +47,8 @@ static struct map_desc msm_io_desc[] __initdata = {
47 MSM_CHIP_DEVICE(GPIO1, MSM7X00), 47 MSM_CHIP_DEVICE(GPIO1, MSM7X00),
48 MSM_CHIP_DEVICE(GPIO2, MSM7X00), 48 MSM_CHIP_DEVICE(GPIO2, MSM7X00),
49 MSM_DEVICE(CLK_CTL), 49 MSM_DEVICE(CLK_CTL),
50#ifdef CONFIG_MSM_DEBUG_UART 50#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
51 defined(CONFIG_DEBUG_MSM_UART3)
51 MSM_DEVICE(DEBUG_UART), 52 MSM_DEVICE(DEBUG_UART),
52#endif 53#endif
53#ifdef CONFIG_ARCH_MSM7X30 54#ifdef CONFIG_ARCH_MSM7X30
@@ -84,7 +85,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
84 MSM_DEVICE(SCPLL), 85 MSM_DEVICE(SCPLL),
85 MSM_DEVICE(AD5), 86 MSM_DEVICE(AD5),
86 MSM_DEVICE(MDC), 87 MSM_DEVICE(MDC),
87#ifdef CONFIG_MSM_DEBUG_UART 88#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
89 defined(CONFIG_DEBUG_MSM_UART3)
88 MSM_DEVICE(DEBUG_UART), 90 MSM_DEVICE(DEBUG_UART),
89#endif 91#endif
90 { 92 {
@@ -109,6 +111,9 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
109 MSM_CHIP_DEVICE(TMR0, MSM8X60), 111 MSM_CHIP_DEVICE(TMR0, MSM8X60),
110 MSM_DEVICE(ACC), 112 MSM_DEVICE(ACC),
111 MSM_DEVICE(GCC), 113 MSM_DEVICE(GCC),
114#ifdef CONFIG_DEBUG_MSM8660_UART
115 MSM_DEVICE(DEBUG_UART),
116#endif
112}; 117};
113 118
114void __init msm_map_msm8x60_io(void) 119void __init msm_map_msm8x60_io(void)
@@ -123,6 +128,9 @@ static struct map_desc msm8960_io_desc[] __initdata = {
123 MSM_CHIP_DEVICE(QGIC_CPU, MSM8960), 128 MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
124 MSM_CHIP_DEVICE(TMR, MSM8960), 129 MSM_CHIP_DEVICE(TMR, MSM8960),
125 MSM_CHIP_DEVICE(TMR0, MSM8960), 130 MSM_CHIP_DEVICE(TMR0, MSM8960),
131#ifdef CONFIG_DEBUG_MSM8960_UART
132 MSM_DEVICE(DEBUG_UART),
133#endif
126}; 134};
127 135
128void __init msm_map_msm8960_io(void) 136void __init msm_map_msm8960_io(void)
@@ -146,7 +154,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
146 MSM_DEVICE(SAW), 154 MSM_DEVICE(SAW),
147 MSM_DEVICE(GCC), 155 MSM_DEVICE(GCC),
148 MSM_DEVICE(TCSR), 156 MSM_DEVICE(TCSR),
149#ifdef CONFIG_MSM_DEBUG_UART 157#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
158 defined(CONFIG_DEBUG_MSM_UART3)
150 MSM_DEVICE(DEBUG_UART), 159 MSM_DEVICE(DEBUG_UART),
151#endif 160#endif
152 { 161 {
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index fdec58aaa35..0b3e357c4c8 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -79,7 +79,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
79 ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), 79 ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
80 SCM_FLAG_COLDBOOT_CPU1); 80 SCM_FLAG_COLDBOOT_CPU1);
81 if (ret == 0) { 81 if (ret == 0) {
82 void *sc1_base_ptr; 82 void __iomem *sc1_base_ptr;
83 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); 83 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
84 if (sc1_base_ptr) { 84 if (sc1_base_ptr) {
85 writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); 85 writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
index 8736afff82f..0c56a5aaf58 100644
--- a/arch/arm/mach-msm/smd_debug.c
+++ b/arch/arm/mach-msm/smd_debug.c
@@ -215,7 +215,7 @@ static const struct file_operations debug_ops = {
215 .llseek = default_llseek, 215 .llseek = default_llseek,
216}; 216};
217 217
218static void debug_create(const char *name, mode_t mode, 218static void debug_create(const char *name, umode_t mode,
219 struct dentry *dent, 219 struct dentry *dent,
220 int (*fill)(char *buf, int max)) 220 int (*fill)(char *buf, int max))
221{ 221{
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index afeeca52fc6..11d0d8f2656 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,6 +1,7 @@
1/* linux/arch/arm/mach-msm/timer.c 1/*
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
4 * 5 *
5 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -13,306 +14,207 @@
13 * 14 *
14 */ 15 */
15 16
17#include <linux/clocksource.h>
18#include <linux/clockchips.h>
16#include <linux/init.h> 19#include <linux/init.h>
17#include <linux/time.h>
18#include <linux/interrupt.h> 20#include <linux/interrupt.h>
19#include <linux/irq.h> 21#include <linux/irq.h>
20#include <linux/clk.h>
21#include <linux/clockchips.h>
22#include <linux/delay.h>
23#include <linux/io.h> 22#include <linux/io.h>
24 23
25#include <asm/mach/time.h> 24#include <asm/mach/time.h>
26#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
26#include <asm/localtimer.h>
27 27
28#include <mach/msm_iomap.h> 28#include <mach/msm_iomap.h>
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30#include <mach/board.h>
30 31
31#define TIMER_MATCH_VAL 0x0000 32#define TIMER_MATCH_VAL 0x0000
32#define TIMER_COUNT_VAL 0x0004 33#define TIMER_COUNT_VAL 0x0004
33#define TIMER_ENABLE 0x0008 34#define TIMER_ENABLE 0x0008
34#define TIMER_ENABLE_CLR_ON_MATCH_EN 2 35#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
35#define TIMER_ENABLE_EN 1 36#define TIMER_ENABLE_EN BIT(0)
36#define TIMER_CLEAR 0x000C 37#define TIMER_CLEAR 0x000C
37#define DGT_CLK_CTL 0x0034 38#define DGT_CLK_CTL 0x0034
38enum { 39#define DGT_CLK_CTL_DIV_4 0x3
39 DGT_CLK_CTL_DIV_1 = 0,
40 DGT_CLK_CTL_DIV_2 = 1,
41 DGT_CLK_CTL_DIV_3 = 2,
42 DGT_CLK_CTL_DIV_4 = 3,
43};
44#define CSR_PROTECTION 0x0020
45#define CSR_PROTECTION_EN 1
46 40
47#define GPT_HZ 32768 41#define GPT_HZ 32768
48 42
49enum timer_location { 43#define MSM_DGT_SHIFT 5
50 LOCAL_TIMER = 0,
51 GLOBAL_TIMER = 1,
52};
53
54#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
55
56/* TODO: Remove these ifdefs */
57#if defined(CONFIG_ARCH_QSD8X50)
58#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
59#define MSM_DGT_SHIFT (0)
60#elif defined(CONFIG_ARCH_MSM7X30)
61#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
62#define MSM_DGT_SHIFT (0)
63#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
64#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
65#define MSM_DGT_SHIFT (0)
66#else
67#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
68#define MSM_DGT_SHIFT (5)
69#endif
70 44
71struct msm_clock { 45static void __iomem *event_base;
72 struct clock_event_device clockevent;
73 struct clocksource clocksource;
74 unsigned int irq;
75 void __iomem *regbase;
76 uint32_t freq;
77 uint32_t shift;
78 void __iomem *global_counter;
79 void __iomem *local_counter;
80 union {
81 struct clock_event_device *evt;
82 struct clock_event_device __percpu **percpu_evt;
83 };
84};
85
86enum {
87 MSM_CLOCK_GPT,
88 MSM_CLOCK_DGT,
89 NR_TIMERS,
90};
91
92
93static struct msm_clock msm_clocks[];
94 46
95static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) 47static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
96{ 48{
97 struct clock_event_device *evt = *(struct clock_event_device **)dev_id; 49 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
98 if (evt->event_handler == NULL) 50 /* Stop the timer tick */
99 return IRQ_HANDLED; 51 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
52 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
53 ctrl &= ~TIMER_ENABLE_EN;
54 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
55 }
100 evt->event_handler(evt); 56 evt->event_handler(evt);
101 return IRQ_HANDLED; 57 return IRQ_HANDLED;
102} 58}
103 59
104static cycle_t msm_read_timer_count(struct clocksource *cs)
105{
106 struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
107
108 /*
109 * Shift timer count down by a constant due to unreliable lower bits
110 * on some targets.
111 */
112 return readl(clk->global_counter) >> clk->shift;
113}
114
115static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
116{
117#ifdef CONFIG_SMP
118 int i;
119 for (i = 0; i < NR_TIMERS; i++)
120 if (evt == &(msm_clocks[i].clockevent))
121 return &msm_clocks[i];
122 return &msm_clocks[MSM_GLOBAL_TIMER];
123#else
124 return container_of(evt, struct msm_clock, clockevent);
125#endif
126}
127
128static int msm_timer_set_next_event(unsigned long cycles, 60static int msm_timer_set_next_event(unsigned long cycles,
129 struct clock_event_device *evt) 61 struct clock_event_device *evt)
130{ 62{
131 struct msm_clock *clock = clockevent_to_clock(evt); 63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
132 uint32_t now = readl(clock->local_counter);
133 uint32_t alarm = now + (cycles << clock->shift);
134 64
135 writel(alarm, clock->regbase + TIMER_MATCH_VAL); 65 writel_relaxed(0, event_base + TIMER_CLEAR);
66 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
67 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
136 return 0; 68 return 0;
137} 69}
138 70
139static void msm_timer_set_mode(enum clock_event_mode mode, 71static void msm_timer_set_mode(enum clock_event_mode mode,
140 struct clock_event_device *evt) 72 struct clock_event_device *evt)
141{ 73{
142 struct msm_clock *clock = clockevent_to_clock(evt); 74 u32 ctrl;
75
76 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
77 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
143 78
144 switch (mode) { 79 switch (mode) {
145 case CLOCK_EVT_MODE_RESUME: 80 case CLOCK_EVT_MODE_RESUME:
146 case CLOCK_EVT_MODE_PERIODIC: 81 case CLOCK_EVT_MODE_PERIODIC:
147 break; 82 break;
148 case CLOCK_EVT_MODE_ONESHOT: 83 case CLOCK_EVT_MODE_ONESHOT:
149 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE); 84 /* Timer is enabled in set_next_event */
150 break; 85 break;
151 case CLOCK_EVT_MODE_UNUSED: 86 case CLOCK_EVT_MODE_UNUSED:
152 case CLOCK_EVT_MODE_SHUTDOWN: 87 case CLOCK_EVT_MODE_SHUTDOWN:
153 writel(0, clock->regbase + TIMER_ENABLE);
154 break; 88 break;
155 } 89 }
90 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
156} 91}
157 92
158static struct msm_clock msm_clocks[] = { 93static struct clock_event_device msm_clockevent = {
159 [MSM_CLOCK_GPT] = { 94 .name = "gp_timer",
160 .clockevent = { 95 .features = CLOCK_EVT_FEAT_ONESHOT,
161 .name = "gp_timer", 96 .rating = 200,
162 .features = CLOCK_EVT_FEAT_ONESHOT, 97 .set_next_event = msm_timer_set_next_event,
163 .shift = 32, 98 .set_mode = msm_timer_set_mode,
164 .rating = 200, 99};
165 .set_next_event = msm_timer_set_next_event, 100
166 .set_mode = msm_timer_set_mode, 101static union {
167 }, 102 struct clock_event_device *evt;
168 .clocksource = { 103 struct clock_event_device __percpu **percpu_evt;
169 .name = "gp_timer", 104} msm_evt;
170 .rating = 200, 105
171 .read = msm_read_timer_count, 106static void __iomem *source_base;
172 .mask = CLOCKSOURCE_MASK(32), 107
173 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 108static cycle_t msm_read_timer_count(struct clocksource *cs)
174 }, 109{
175 .irq = INT_GP_TIMER_EXP, 110 return readl_relaxed(source_base + TIMER_COUNT_VAL);
176 .freq = GPT_HZ, 111}
177 }, 112
178 [MSM_CLOCK_DGT] = { 113static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
179 .clockevent = { 114{
180 .name = "dg_timer", 115 /*
181 .features = CLOCK_EVT_FEAT_ONESHOT, 116 * Shift timer count down by a constant due to unreliable lower bits
182 .shift = 32 + MSM_DGT_SHIFT, 117 * on some targets.
183 .rating = 300, 118 */
184 .set_next_event = msm_timer_set_next_event, 119 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
185 .set_mode = msm_timer_set_mode, 120}
186 }, 121
187 .clocksource = { 122static struct clocksource msm_clocksource = {
188 .name = "dg_timer", 123 .name = "dg_timer",
189 .rating = 300, 124 .rating = 300,
190 .read = msm_read_timer_count, 125 .read = msm_read_timer_count,
191 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), 126 .mask = CLOCKSOURCE_MASK(32),
192 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
193 },
194 .irq = INT_DEBUG_TIMER_EXP,
195 .freq = DGT_HZ >> MSM_DGT_SHIFT,
196 .shift = MSM_DGT_SHIFT,
197 }
198}; 128};
199 129
200static void __init msm_timer_init(void) 130static void __init msm_timer_init(void)
201{ 131{
202 int i; 132 struct clock_event_device *ce = &msm_clockevent;
133 struct clocksource *cs = &msm_clocksource;
203 int res; 134 int res;
204 int global_offset = 0; 135 u32 dgt_hz;
205 136
206 if (cpu_is_msm7x01()) { 137 if (cpu_is_msm7x01()) {
207 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; 138 event_base = MSM_CSR_BASE;
208 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; 139 source_base = MSM_CSR_BASE + 0x10;
140 dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
141 cs->read = msm_read_timer_count_shift;
142 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
209 } else if (cpu_is_msm7x30()) { 143 } else if (cpu_is_msm7x30()) {
210 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04; 144 event_base = MSM_CSR_BASE + 0x04;
211 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24; 145 source_base = MSM_CSR_BASE + 0x24;
146 dgt_hz = 24576000 / 4;
212 } else if (cpu_is_qsd8x50()) { 147 } else if (cpu_is_qsd8x50()) {
213 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE; 148 event_base = MSM_CSR_BASE;
214 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10; 149 source_base = MSM_CSR_BASE + 0x10;
150 dgt_hz = 19200000 / 4;
215 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) { 151 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
216 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04; 152 event_base = MSM_TMR_BASE + 0x04;
217 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24; 153 /* Use CPU0's timer as the global clock source. */
218 154 source_base = MSM_TMR0_BASE + 0x24;
219 /* Use CPU0's timer as the global timer. */ 155 dgt_hz = 27000000 / 4;
220 global_offset = MSM_TMR0_BASE - MSM_TMR_BASE; 156 writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
221 } else 157 } else
222 BUG(); 158 BUG();
223 159
224#ifdef CONFIG_ARCH_MSM_SCORPIONMP 160 writel_relaxed(0, event_base + TIMER_ENABLE);
225 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); 161 writel_relaxed(0, event_base + TIMER_CLEAR);
226#endif 162 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
227 163 ce->cpumask = cpumask_of(0);
228 for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) { 164
229 struct msm_clock *clock = &msm_clocks[i]; 165 ce->irq = INT_GP_TIMER_EXP;
230 struct clock_event_device *ce = &clock->clockevent; 166 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
231 struct clocksource *cs = &clock->clocksource; 167 if (cpu_is_msm8x60() || cpu_is_msm8960()) {
232 168 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
233 clock->local_counter = clock->regbase + TIMER_COUNT_VAL; 169 if (!msm_evt.percpu_evt) {
234 clock->global_counter = clock->local_counter + global_offset; 170 pr_err("memory allocation failed for %s\n", ce->name);
235 171 goto err;
236 writel(0, clock->regbase + TIMER_ENABLE);
237 writel(0, clock->regbase + TIMER_CLEAR);
238 writel(~0, clock->regbase + TIMER_MATCH_VAL);
239
240 ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
241 /* allow at least 10 seconds to notice that the timer wrapped */
242 ce->max_delta_ns =
243 clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
244 /* 4 gets rounded down to 3 */
245 ce->min_delta_ns = clockevent_delta2ns(4, ce);
246 ce->cpumask = cpumask_of(0);
247
248 res = clocksource_register_hz(cs, clock->freq);
249 if (res)
250 printk(KERN_ERR "msm_timer_init: clocksource_register "
251 "failed for %s\n", cs->name);
252
253 ce->irq = clock->irq;
254 if (cpu_is_msm8x60() || cpu_is_msm8960()) {
255 clock->percpu_evt = alloc_percpu(struct clock_event_device *);
256 if (!clock->percpu_evt) {
257 pr_err("msm_timer_init: memory allocation "
258 "failed for %s\n", ce->name);
259 continue;
260 }
261
262 *__this_cpu_ptr(clock->percpu_evt) = ce;
263 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
264 ce->name, clock->percpu_evt);
265 if (!res)
266 enable_percpu_irq(ce->irq, 0);
267 } else {
268 clock->evt = ce;
269 res = request_irq(ce->irq, msm_timer_interrupt,
270 IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
271 ce->name, &clock->evt);
272 } 172 }
273 173 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
274 if (res) 174 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
275 pr_err("msm_timer_init: request_irq failed for %s\n", 175 ce->name, msm_evt.percpu_evt);
276 ce->name); 176 if (!res)
277 177 enable_percpu_irq(ce->irq, 0);
278 clockevents_register_device(ce); 178 } else {
179 msm_evt.evt = ce;
180 res = request_irq(ce->irq, msm_timer_interrupt,
181 IRQF_TIMER | IRQF_NOBALANCING |
182 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
279 } 183 }
184
185 if (res)
186 pr_err("request_irq failed for %s\n", ce->name);
187err:
188 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
189 res = clocksource_register_hz(cs, dgt_hz);
190 if (res)
191 pr_err("clocksource_register failed\n");
280} 192}
281 193
282#ifdef CONFIG_SMP 194#ifdef CONFIG_LOCAL_TIMERS
283int __cpuinit local_timer_setup(struct clock_event_device *evt) 195int __cpuinit local_timer_setup(struct clock_event_device *evt)
284{ 196{
285 static bool local_timer_inited;
286 struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
287
288 /* Use existing clock_event for cpu 0 */ 197 /* Use existing clock_event for cpu 0 */
289 if (!smp_processor_id()) 198 if (!smp_processor_id())
290 return 0; 199 return 0;
291 200
292 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); 201 writel_relaxed(0, event_base + TIMER_ENABLE);
293 202 writel_relaxed(0, event_base + TIMER_CLEAR);
294 if (!local_timer_inited) { 203 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
295 writel(0, clock->regbase + TIMER_ENABLE); 204 evt->irq = msm_clockevent.irq;
296 writel(0, clock->regbase + TIMER_CLEAR);
297 writel(~0, clock->regbase + TIMER_MATCH_VAL);
298 local_timer_inited = true;
299 }
300 evt->irq = clock->irq;
301 evt->name = "local_timer"; 205 evt->name = "local_timer";
302 evt->features = CLOCK_EVT_FEAT_ONESHOT; 206 evt->features = msm_clockevent.features;
303 evt->rating = clock->clockevent.rating; 207 evt->rating = msm_clockevent.rating;
304 evt->set_mode = msm_timer_set_mode; 208 evt->set_mode = msm_timer_set_mode;
305 evt->set_next_event = msm_timer_set_next_event; 209 evt->set_next_event = msm_timer_set_next_event;
306 evt->shift = clock->clockevent.shift; 210 evt->shift = msm_clockevent.shift;
307 evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift); 211 evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
308 evt->max_delta_ns = 212 evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
309 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
310 evt->min_delta_ns = clockevent_delta2ns(4, evt); 213 evt->min_delta_ns = clockevent_delta2ns(4, evt);
311 214
312 *__this_cpu_ptr(clock->percpu_evt) = evt; 215 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
313 enable_percpu_irq(evt->irq, 0);
314
315 clockevents_register_device(evt); 216 clockevents_register_device(evt);
217 enable_percpu_irq(evt->irq, 0);
316 return 0; 218 return 0;
317} 219}
318 220
@@ -321,8 +223,7 @@ void local_timer_stop(struct clock_event_device *evt)
321 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 223 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
322 disable_percpu_irq(evt->irq); 224 disable_percpu_irq(evt->irq);
323} 225}
324 226#endif /* CONFIG_LOCAL_TIMERS */
325#endif
326 227
327struct sys_timer msm_timer = { 228struct sys_timer msm_timer = {
328 .init = msm_timer_init 229 .init = msm_timer_init
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 23:19:39 -0500