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authorBrian Swetland <swetland@google.com>2008-09-10 17:00:53 -0400
committerBrian Swetland <swetland@google.com>2008-10-22 05:40:59 -0400
commitbcc0f6af0798e60e7527485f7125ed26632ce698 (patch)
treeac45678ea4131d7423f64025e8021106937dbf77 /arch/arm/mach-msm/include/mach/msm_iomap.h
parentb8a16e1fdfe9caed734df0e157ad74ae2b13e3bd (diff)
[ARM] msm: clean up iomap and devices
- Add some more peripherals (sdcc, etc) to the iomap. - Remove virtual base addresses for devices that we should be passing physical addresses to drivers via resources and ioremap()ing. - don't try to use uarts for ll debug once the mmu is enabled due to problems with the peripheral window - make base addresses void __iomem * and fixup irq.c and timer.c - Remove common.c and bring in devices.c/devices.h similar to the PXA architecture. Signed-off-by: Brian Swetland <swetland@google.com>
Diffstat (limited to 'arch/arm/mach-msm/include/mach/msm_iomap.h')
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h69
1 files changed, 43 insertions, 26 deletions
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index e221f58ceea..2f7b4c8620d 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -37,11 +37,17 @@
37 * 37 *
38 */ 38 */
39 39
40#define MSM_VIC_BASE 0xE0000000 40#ifdef __ASSEMBLY__
41#define IOMEM(x) x
42#else
43#define IOMEM(x) ((void __force __iomem *)(x))
44#endif
45
46#define MSM_VIC_BASE IOMEM(0xE0000000)
41#define MSM_VIC_PHYS 0xC0000000 47#define MSM_VIC_PHYS 0xC0000000
42#define MSM_VIC_SIZE SZ_4K 48#define MSM_VIC_SIZE SZ_4K
43 49
44#define MSM_CSR_BASE 0xE0001000 50#define MSM_CSR_BASE IOMEM(0xE0001000)
45#define MSM_CSR_PHYS 0xC0100000 51#define MSM_CSR_PHYS 0xC0100000
46#define MSM_CSR_SIZE SZ_4K 52#define MSM_CSR_SIZE SZ_4K
47 53
@@ -49,56 +55,67 @@
49#define MSM_GPT_BASE MSM_CSR_BASE 55#define MSM_GPT_BASE MSM_CSR_BASE
50#define MSM_GPT_SIZE SZ_4K 56#define MSM_GPT_SIZE SZ_4K
51 57
52#define MSM_DMOV_BASE 0xE0002000 58#define MSM_DMOV_BASE IOMEM(0xE0002000)
53#define MSM_DMOV_PHYS 0xA9700000 59#define MSM_DMOV_PHYS 0xA9700000
54#define MSM_DMOV_SIZE SZ_4K 60#define MSM_DMOV_SIZE SZ_4K
55 61
56#define MSM_UART1_BASE 0xE0003000 62#define MSM_GPIO1_BASE IOMEM(0xE0003000)
63#define MSM_GPIO1_PHYS 0xA9200000
64#define MSM_GPIO1_SIZE SZ_4K
65
66#define MSM_GPIO2_BASE IOMEM(0xE0004000)
67#define MSM_GPIO2_PHYS 0xA9300000
68#define MSM_GPIO2_SIZE SZ_4K
69
70#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
71#define MSM_CLK_CTL_PHYS 0xA8600000
72#define MSM_CLK_CTL_SIZE SZ_4K
73
74#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
75#define MSM_SHARED_RAM_PHYS 0x01F00000
76#define MSM_SHARED_RAM_SIZE SZ_1M
77
57#define MSM_UART1_PHYS 0xA9A00000 78#define MSM_UART1_PHYS 0xA9A00000
58#define MSM_UART1_SIZE SZ_4K 79#define MSM_UART1_SIZE SZ_4K
59 80
60#define MSM_UART2_BASE 0xE0004000
61#define MSM_UART2_PHYS 0xA9B00000 81#define MSM_UART2_PHYS 0xA9B00000
62#define MSM_UART2_SIZE SZ_4K 82#define MSM_UART2_SIZE SZ_4K
63 83
64#define MSM_UART3_BASE 0xE0005000
65#define MSM_UART3_PHYS 0xA9C00000 84#define MSM_UART3_PHYS 0xA9C00000
66#define MSM_UART3_SIZE SZ_4K 85#define MSM_UART3_SIZE SZ_4K
67 86
68#define MSM_I2C_BASE 0xE0006000 87#define MSM_SDC1_PHYS 0xA0400000
69#define MSM_I2C_PHYS 0xA9900000 88#define MSM_SDC1_SIZE SZ_4K
70#define MSM_I2C_SIZE SZ_4K
71 89
72#define MSM_GPIO1_BASE 0xE0007000 90#define MSM_SDC2_PHYS 0xA0500000
73#define MSM_GPIO1_PHYS 0xA9200000 91#define MSM_SDC2_SIZE SZ_4K
74#define MSM_GPIO1_SIZE SZ_4K
75 92
76#define MSM_GPIO2_BASE 0xE0008000 93#define MSM_SDC3_PHYS 0xA0600000
77#define MSM_GPIO2_PHYS 0xA9300000 94#define MSM_SDC3_SIZE SZ_4K
78#define MSM_GPIO2_SIZE SZ_4K 95
96#define MSM_SDC4_PHYS 0xA0700000
97#define MSM_SDC4_SIZE SZ_4K
98
99#define MSM_I2C_PHYS 0xA9900000
100#define MSM_I2C_SIZE SZ_4K
79 101
80#define MSM_HSUSB_BASE 0xE0009000
81#define MSM_HSUSB_PHYS 0xA0800000 102#define MSM_HSUSB_PHYS 0xA0800000
82#define MSM_HSUSB_SIZE SZ_4K 103#define MSM_HSUSB_SIZE SZ_4K
83 104
84#define MSM_CLK_CTL_BASE 0xE000A000
85#define MSM_CLK_CTL_PHYS 0xA8600000
86#define MSM_CLK_CTL_SIZE SZ_4K
87
88#define MSM_PMDH_BASE 0xE000B000
89#define MSM_PMDH_PHYS 0xAA600000 105#define MSM_PMDH_PHYS 0xAA600000
90#define MSM_PMDH_SIZE SZ_4K 106#define MSM_PMDH_SIZE SZ_4K
91 107
92#define MSM_EMDH_BASE 0xE000C000
93#define MSM_EMDH_PHYS 0xAA700000 108#define MSM_EMDH_PHYS 0xAA700000
94#define MSM_EMDH_SIZE SZ_4K 109#define MSM_EMDH_SIZE SZ_4K
95 110
96#define MSM_MDP_BASE 0xE0010000
97#define MSM_MDP_PHYS 0xAA200000 111#define MSM_MDP_PHYS 0xAA200000
98#define MSM_MDP_SIZE 0x000F0000 112#define MSM_MDP_SIZE 0x000F0000
99 113
100#define MSM_SHARED_RAM_BASE 0xE0100000 114#define MSM_MDC_PHYS 0xAA500000
101#define MSM_SHARED_RAM_PHYS 0x01F00000 115#define MSM_MDC_SIZE SZ_1M
102#define MSM_SHARED_RAM_SIZE SZ_1M 116
117#define MSM_AD5_PHYS 0xAC000000
118#define MSM_AD5_SIZE (SZ_1M*13)
119
103 120
104#endif 121#endif