diff options
| author | Chao Xie <chao.xie@marvell.com> | 2012-08-26 22:54:03 -0400 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-09-08 11:40:09 -0400 |
| commit | 7f744b17140af1a9c8804a1c81c9dae6bb52a7fb (patch) | |
| tree | 4328d16328d4e9e5f1f935580a97fd91badef074 /arch/arm/mach-mmp/include/mach | |
| parent | 8430305dc3f3a286a337f1b4419c04afe55a2583 (diff) | |
ARM: mmp: remove unused definition in APBC and APMU
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp/include/mach')
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 95 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apmu.h | 15 |
2 files changed, 0 insertions, 110 deletions
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 68b0c93ec6a..ddc812f4034 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h | |||
| @@ -13,101 +13,6 @@ | |||
| 13 | 13 | ||
| 14 | #include <mach/addr-map.h> | 14 | #include <mach/addr-map.h> |
| 15 | 15 | ||
| 16 | /* | ||
| 17 | * APB clock register offsets for PXA168 | ||
| 18 | */ | ||
| 19 | #define APBC_PXA168_UART1 APBC_REG(0x000) | ||
| 20 | #define APBC_PXA168_UART2 APBC_REG(0x004) | ||
| 21 | #define APBC_PXA168_GPIO APBC_REG(0x008) | ||
| 22 | #define APBC_PXA168_PWM1 APBC_REG(0x00c) | ||
| 23 | #define APBC_PXA168_PWM2 APBC_REG(0x010) | ||
| 24 | #define APBC_PXA168_PWM3 APBC_REG(0x014) | ||
| 25 | #define APBC_PXA168_PWM4 APBC_REG(0x018) | ||
| 26 | #define APBC_PXA168_RTC APBC_REG(0x028) | ||
| 27 | #define APBC_PXA168_TWSI0 APBC_REG(0x02c) | ||
| 28 | #define APBC_PXA168_KPC APBC_REG(0x030) | ||
| 29 | #define APBC_PXA168_TIMERS APBC_REG(0x034) | ||
| 30 | #define APBC_PXA168_AIB APBC_REG(0x03c) | ||
| 31 | #define APBC_PXA168_SW_JTAG APBC_REG(0x040) | ||
| 32 | #define APBC_PXA168_ONEWIRE APBC_REG(0x048) | ||
| 33 | #define APBC_PXA168_ASFAR APBC_REG(0x050) | ||
| 34 | #define APBC_PXA168_ASSAR APBC_REG(0x054) | ||
| 35 | #define APBC_PXA168_TWSI1 APBC_REG(0x06c) | ||
| 36 | #define APBC_PXA168_UART3 APBC_REG(0x070) | ||
| 37 | #define APBC_PXA168_AC97 APBC_REG(0x084) | ||
| 38 | #define APBC_PXA168_SSP1 APBC_REG(0x81c) | ||
| 39 | #define APBC_PXA168_SSP2 APBC_REG(0x820) | ||
| 40 | #define APBC_PXA168_SSP3 APBC_REG(0x84c) | ||
| 41 | #define APBC_PXA168_SSP4 APBC_REG(0x858) | ||
| 42 | #define APBC_PXA168_SSP5 APBC_REG(0x85c) | ||
| 43 | |||
| 44 | /* | ||
| 45 | * APB Clock register offsets for PXA910 | ||
| 46 | */ | ||
| 47 | #define APBC_PXA910_UART0 APBC_REG(0x000) | ||
| 48 | #define APBC_PXA910_UART1 APBC_REG(0x004) | ||
| 49 | #define APBC_PXA910_GPIO APBC_REG(0x008) | ||
| 50 | #define APBC_PXA910_PWM1 APBC_REG(0x00c) | ||
| 51 | #define APBC_PXA910_PWM2 APBC_REG(0x010) | ||
| 52 | #define APBC_PXA910_PWM3 APBC_REG(0x014) | ||
| 53 | #define APBC_PXA910_PWM4 APBC_REG(0x018) | ||
| 54 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) | ||
| 55 | #define APBC_PXA910_SSP2 APBC_REG(0x020) | ||
| 56 | #define APBC_PXA910_IPC APBC_REG(0x024) | ||
| 57 | #define APBC_PXA910_RTC APBC_REG(0x028) | ||
| 58 | #define APBC_PXA910_TWSI0 APBC_REG(0x02c) | ||
| 59 | #define APBC_PXA910_KPC APBC_REG(0x030) | ||
| 60 | #define APBC_PXA910_TIMERS APBC_REG(0x034) | ||
| 61 | #define APBC_PXA910_TBROT APBC_REG(0x038) | ||
| 62 | #define APBC_PXA910_AIB APBC_REG(0x03c) | ||
| 63 | #define APBC_PXA910_SW_JTAG APBC_REG(0x040) | ||
| 64 | #define APBC_PXA910_TIMERS1 APBC_REG(0x044) | ||
| 65 | #define APBC_PXA910_ONEWIRE APBC_REG(0x048) | ||
| 66 | #define APBC_PXA910_SSP3 APBC_REG(0x04c) | ||
| 67 | #define APBC_PXA910_ASFAR APBC_REG(0x050) | ||
| 68 | #define APBC_PXA910_ASSAR APBC_REG(0x054) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * APB Clock register offsets for MMP2 | ||
| 72 | */ | ||
| 73 | #define APBC_MMP2_RTC APBC_REG(0x000) | ||
| 74 | #define APBC_MMP2_TWSI1 APBC_REG(0x004) | ||
| 75 | #define APBC_MMP2_TWSI2 APBC_REG(0x008) | ||
| 76 | #define APBC_MMP2_TWSI3 APBC_REG(0x00c) | ||
| 77 | #define APBC_MMP2_TWSI4 APBC_REG(0x010) | ||
| 78 | #define APBC_MMP2_ONEWIRE APBC_REG(0x014) | ||
| 79 | #define APBC_MMP2_KPC APBC_REG(0x018) | ||
| 80 | #define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) | ||
| 81 | #define APBC_MMP2_SW_JTAG APBC_REG(0x020) | ||
| 82 | #define APBC_MMP2_TIMERS APBC_REG(0x024) | ||
| 83 | #define APBC_MMP2_UART1 APBC_REG(0x02c) | ||
| 84 | #define APBC_MMP2_UART2 APBC_REG(0x030) | ||
| 85 | #define APBC_MMP2_UART3 APBC_REG(0x034) | ||
| 86 | #define APBC_MMP2_GPIO APBC_REG(0x038) | ||
| 87 | #define APBC_MMP2_PWM0 APBC_REG(0x03c) | ||
| 88 | #define APBC_MMP2_PWM1 APBC_REG(0x040) | ||
| 89 | #define APBC_MMP2_PWM2 APBC_REG(0x044) | ||
| 90 | #define APBC_MMP2_PWM3 APBC_REG(0x048) | ||
| 91 | #define APBC_MMP2_SSP0 APBC_REG(0x04c) | ||
| 92 | #define APBC_MMP2_SSP1 APBC_REG(0x050) | ||
| 93 | #define APBC_MMP2_SSP2 APBC_REG(0x054) | ||
| 94 | #define APBC_MMP2_SSP3 APBC_REG(0x058) | ||
| 95 | #define APBC_MMP2_SSP4 APBC_REG(0x05c) | ||
| 96 | #define APBC_MMP2_SSP5 APBC_REG(0x060) | ||
| 97 | #define APBC_MMP2_AIB APBC_REG(0x064) | ||
| 98 | #define APBC_MMP2_ASFAR APBC_REG(0x068) | ||
| 99 | #define APBC_MMP2_ASSAR APBC_REG(0x06c) | ||
| 100 | #define APBC_MMP2_USIM APBC_REG(0x070) | ||
| 101 | #define APBC_MMP2_MPMU APBC_REG(0x074) | ||
| 102 | #define APBC_MMP2_IPC APBC_REG(0x078) | ||
| 103 | #define APBC_MMP2_TWSI5 APBC_REG(0x07c) | ||
| 104 | #define APBC_MMP2_TWSI6 APBC_REG(0x080) | ||
| 105 | #define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) | ||
| 106 | #define APBC_MMP2_UART4 APBC_REG(0x088) | ||
| 107 | #define APBC_MMP2_RIPC APBC_REG(0x08c) | ||
| 108 | #define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ | ||
| 109 | #define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) | ||
| 110 | |||
| 111 | /* Common APB clock register bit definitions */ | 16 | /* Common APB clock register bit definitions */ |
| 112 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ | 17 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ |
| 113 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ | 18 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ |
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index 7af8deb63e8..93c8d0e29bb 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h | |||
| @@ -13,21 +13,6 @@ | |||
| 13 | 13 | ||
| 14 | #include <mach/addr-map.h> | 14 | #include <mach/addr-map.h> |
| 15 | 15 | ||
| 16 | /* Clock Reset Control */ | ||
| 17 | #define APMU_IRE APMU_REG(0x048) | ||
| 18 | #define APMU_LCD APMU_REG(0x04c) | ||
| 19 | #define APMU_CCIC APMU_REG(0x050) | ||
| 20 | #define APMU_SDH0 APMU_REG(0x054) | ||
| 21 | #define APMU_SDH1 APMU_REG(0x058) | ||
| 22 | #define APMU_USB APMU_REG(0x05c) | ||
| 23 | #define APMU_NAND APMU_REG(0x060) | ||
| 24 | #define APMU_DMA APMU_REG(0x064) | ||
| 25 | #define APMU_GEU APMU_REG(0x068) | ||
| 26 | #define APMU_BUS APMU_REG(0x06c) | ||
| 27 | #define APMU_SDH2 APMU_REG(0x0e8) | ||
| 28 | #define APMU_SDH3 APMU_REG(0x0ec) | ||
| 29 | #define APMU_ETH APMU_REG(0x0fc) | ||
| 30 | |||
| 31 | #define APMU_FNCLK_EN (1 << 4) | 16 | #define APMU_FNCLK_EN (1 << 4) |
| 32 | #define APMU_AXICLK_EN (1 << 3) | 17 | #define APMU_AXICLK_EN (1 << 3) |
| 33 | #define APMU_FNRST_DIS (1 << 1) | 18 | #define APMU_FNRST_DIS (1 << 1) |