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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-mmp
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r--arch/arm/mach-mmp/include/mach/io.h21
-rw-r--r--arch/arm/mach-mmp/include/mach/memory.h14
-rw-r--r--arch/arm/mach-mmp/include/mach/system.h26
-rw-r--r--arch/arm/mach-mmp/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-mmp/irq-mmp2.c157
-rw-r--r--arch/arm/mach-mmp/irq-pxa168.c54
6 files changed, 277 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
new file mode 100644
index 00000000000..e7adf3d012c
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -0,0 +1,21 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/io.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_IO_H
10#define __ASM_MACH_IO_H
11
12#define IO_SPACE_LIMIT 0xffffffff
13
14/*
15 * We don't actually have real ISA nor PCI buses, but there is so many
16 * drivers out there that might just work if we fake them...
17 */
18#define __io(a) __typesafe_io(a)
19#define __mem_pci(a) (a)
20
21#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
new file mode 100644
index 00000000000..d68b50a2d6a
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/memory.h
@@ -0,0 +1,14 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/memory.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_MEMORY_H
10#define __ASM_MACH_MEMORY_H
11
12#define PLAT_PHYS_OFFSET UL(0x00000000)
13
14#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
new file mode 100644
index 00000000000..1a8a25edb1b
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -0,0 +1,26 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/system.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_SYSTEM_H
10#define __ASM_MACH_SYSTEM_H
11
12#include <mach/cputype.h>
13
14static inline void arch_idle(void)
15{
16 cpu_do_idle();
17}
18
19static inline void arch_reset(char mode, const char *cmd)
20{
21 if (cpu_is_pxa168())
22 cpu_reset(0xffff0000);
23 else
24 cpu_reset(0);
25}
26#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
new file mode 100644
index 00000000000..1d0bac003ad
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000UL
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
new file mode 100644
index 00000000000..d21c5441a3d
--- /dev/null
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -0,0 +1,157 @@
1/*
2 * linux/arch/arm/mach-mmp/irq-mmp2.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
7 * Copyright: Marvell International Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17
18#include <mach/regs-icu.h>
19#include <mach/mmp2.h>
20
21#include "common.h"
22
23static void icu_mask_irq(struct irq_data *d)
24{
25 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
26
27 r &= ~ICU_INT_ROUTE_PJ4_IRQ;
28 __raw_writel(r, ICU_INT_CONF(d->irq));
29}
30
31static void icu_unmask_irq(struct irq_data *d)
32{
33 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
34
35 r |= ICU_INT_ROUTE_PJ4_IRQ;
36 __raw_writel(r, ICU_INT_CONF(d->irq));
37}
38
39static struct irq_chip icu_irq_chip = {
40 .name = "icu_irq",
41 .irq_mask = icu_mask_irq,
42 .irq_mask_ack = icu_mask_irq,
43 .irq_unmask = icu_unmask_irq,
44};
45
46static void pmic_irq_ack(struct irq_data *d)
47{
48 if (d->irq == IRQ_MMP2_PMIC)
49 mmp2_clear_pmic_int();
50}
51
52#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
53static void _name_##_mask_irq(struct irq_data *d) \
54{ \
55 uint32_t r; \
56 r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
57 __raw_writel(r, prefix##_MASK); \
58}
59
60#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
61static void _name_##_unmask_irq(struct irq_data *d) \
62{ \
63 uint32_t r; \
64 r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
65 __raw_writel(r, prefix##_MASK); \
66}
67
68#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
69static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
70{ \
71 unsigned long status, mask, n; \
72 mask = __raw_readl(prefix##_MASK); \
73 while (1) { \
74 status = __raw_readl(prefix##_STATUS) & ~mask; \
75 if (status == 0) \
76 break; \
77 n = find_first_bit(&status, BITS_PER_LONG); \
78 while (n < BITS_PER_LONG) { \
79 generic_handle_irq(irq_base + n); \
80 n = find_next_bit(&status, BITS_PER_LONG, n+1); \
81 } \
82 } \
83}
84
85#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \
86SECOND_IRQ_MASK(_name_, irq_base, prefix) \
87SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
88SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
89static struct irq_chip _name_##_irq_chip = { \
90 .name = #_name_, \
91 .irq_mask = _name_##_mask_irq, \
92 .irq_unmask = _name_##_unmask_irq, \
93}
94
95SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
96SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5);
97SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
98SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
99SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51);
100
101static void init_mux_irq(struct irq_chip *chip, int start, int num)
102{
103 int irq;
104
105 for (irq = start; num > 0; irq++, num--) {
106 struct irq_data *d = irq_get_irq_data(irq);
107
108 /* mask and clear the IRQ */
109 chip->irq_mask(d);
110 if (chip->irq_ack)
111 chip->irq_ack(d);
112
113 irq_set_chip(irq, chip);
114 set_irq_flags(irq, IRQF_VALID);
115 irq_set_handler(irq, handle_level_irq);
116 }
117}
118
119void __init mmp2_init_icu(void)
120{
121 int irq;
122
123 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
124 icu_mask_irq(irq_get_irq_data(irq));
125 irq_set_chip(irq, &icu_irq_chip);
126 set_irq_flags(irq, IRQF_VALID);
127
128 switch (irq) {
129 case IRQ_MMP2_PMIC_MUX:
130 case IRQ_MMP2_RTC_MUX:
131 case IRQ_MMP2_TWSI_MUX:
132 case IRQ_MMP2_MISC_MUX:
133 case IRQ_MMP2_SSP_MUX:
134 break;
135 default:
136 irq_set_handler(irq, handle_level_irq);
137 break;
138 }
139 }
140
141 /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
142 * to be written to clear the interrupt
143 */
144 pmic_irq_chip.irq_ack = pmic_irq_ack;
145
146 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
147 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
148 init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
149 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
150 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
151
152 irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
153 irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
154 irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
155 irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
156 irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
157}
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
new file mode 100644
index 00000000000..89706a0d08f
--- /dev/null
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -0,0 +1,54 @@
1/*
2 * linux/arch/arm/mach-mmp/irq.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Bin Yang <bin.yang@marvell.com>
7 * Created: Sep 30, 2008
8 * Copyright: Marvell International Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18
19#include <mach/regs-icu.h>
20
21#include "common.h"
22
23#define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
24
25#define PRIORITY_DEFAULT 0x1
26#define PRIORITY_NONE 0x0 /* means IRQ disabled */
27
28static void icu_mask_irq(struct irq_data *d)
29{
30 __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
31}
32
33static void icu_unmask_irq(struct irq_data *d)
34{
35 __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
36}
37
38static struct irq_chip icu_irq_chip = {
39 .name = "icu_irq",
40 .irq_ack = icu_mask_irq,
41 .irq_mask = icu_mask_irq,
42 .irq_unmask = icu_unmask_irq,
43};
44
45void __init icu_init_irq(void)
46{
47 int irq;
48
49 for (irq = 0; irq < 64; irq++) {
50 icu_mask_irq(irq_get_irq_data(irq));
51 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
52 set_irq_flags(irq, IRQF_VALID);
53 }
54}
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