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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-ixp2000
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-ixp2000')
-rw-r--r--arch/arm/mach-ixp2000/Kconfig72
-rw-r--r--arch/arm/mach-ixp2000/Makefile14
-rw-r--r--arch/arm/mach-ixp2000/Makefile.boot3
-rw-r--r--arch/arm/mach-ixp2000/core.c516
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c264
-rw-r--r--arch/arm/mach-ixp2000/include/mach/debug-macro.S25
-rw-r--r--arch/arm/mach-ixp2000/include/mach/enp2611.h46
-rw-r--r--arch/arm/mach-ixp2000/include/mach/entry-macro.S60
-rw-r--r--arch/arm/mach-ixp2000/include/mach/gpio.h48
-rw-r--r--arch/arm/mach-ixp2000/include/mach/hardware.h36
-rw-r--r--arch/arm/mach-ixp2000/include/mach/io.h134
-rw-r--r--arch/arm/mach-ixp2000/include/mach/irqs.h207
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixdp2x00.h92
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixdp2x01.h57
-rw-r--r--arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h451
-rw-r--r--arch/arm/mach-ixp2000/include/mach/memory.h31
-rw-r--r--arch/arm/mach-ixp2000/include/mach/platform.h152
-rw-r--r--arch/arm/mach-ixp2000/include/mach/system.h49
-rw-r--r--arch/arm/mach-ixp2000/include/mach/timex.h13
-rw-r--r--arch/arm/mach-ixp2000/include/mach/uncompress.h47
-rw-r--r--arch/arm/mach-ixp2000/include/mach/vmalloc.h20
-rw-r--r--arch/arm/mach-ixp2000/ixdp2400.c180
-rw-r--r--arch/arm/mach-ixp2000/ixdp2800.c295
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x00.c307
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c452
-rw-r--r--arch/arm/mach-ixp2000/pci.c251
26 files changed, 3822 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig
new file mode 100644
index 00000000000..08d2707f6ca
--- /dev/null
+++ b/arch/arm/mach-ixp2000/Kconfig
@@ -0,0 +1,72 @@
1
2if ARCH_IXP2000
3
4config ARCH_SUPPORTS_BIG_ENDIAN
5 bool
6 default y
7
8menu "Intel IXP2400/2800 Implementation Options"
9
10comment "IXP2400/2800 Platforms"
11
12config ARCH_ENP2611
13 bool "Support Radisys ENP-2611"
14 help
15 Say 'Y' here if you want your kernel to support the Radisys
16 ENP2611 PCI network processing card. For more information on
17 this card, see <file:Documentation/arm/IXP2000>.
18
19config ARCH_IXDP2400
20 bool "Support Intel IXDP2400"
21 help
22 Say 'Y' here if you want your kernel to support the Intel
23 IXDP2400 reference platform. For more information on
24 this platform, see <file:Documentation/arm/IXP2000>.
25
26config ARCH_IXDP2800
27 bool "Support Intel IXDP2800"
28 help
29 Say 'Y' here if you want your kernel to support the Intel
30 IXDP2800 reference platform. For more information on
31 this platform, see <file:Documentation/arm/IXP2000>.
32
33config ARCH_IXDP2X00
34 bool
35 depends on ARCH_IXDP2400 || ARCH_IXDP2800
36 default y
37
38config ARCH_IXDP2401
39 bool "Support Intel IXDP2401"
40 help
41 Say 'Y' here if you want your kernel to support the Intel
42 IXDP2401 reference platform. For more information on
43 this platform, see <file:Documentation/arm/IXP2000>.
44
45config ARCH_IXDP2801
46 bool "Support Intel IXDP2801 and IXDP28x5"
47 help
48 Say 'Y' here if you want your kernel to support the Intel
49 IXDP2801/2805/2855 reference platforms. For more information on
50 this platform, see <file:Documentation/arm/IXP2000>.
51
52config MACH_IXDP28X5
53 bool
54 depends on ARCH_IXDP2801
55 default y
56
57config ARCH_IXDP2X01
58 bool
59 depends on ARCH_IXDP2401 || ARCH_IXDP2801
60 default y
61
62config IXP2000_SUPPORT_BROKEN_PCI_IO
63 bool "Support broken PCI I/O on older IXP2000s"
64 default y
65 help
66 Say 'N' here if you only intend to run your kernel on an
67 IXP2000 B0 or later model and do not need the PCI I/O
68 byteswap workaround. Say 'Y' otherwise.
69
70endmenu
71
72endif
diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile
new file mode 100644
index 00000000000..1e6139d42a9
--- /dev/null
+++ b/arch/arm/mach-ixp2000/Makefile
@@ -0,0 +1,14 @@
1#
2# Makefile for the linux kernel.
3#
4obj-y := core.o pci.o
5obj-m :=
6obj-n :=
7obj- :=
8
9obj-$(CONFIG_ARCH_ENP2611) += enp2611.o
10obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o
11obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o
12obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o
13obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o
14
diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot
new file mode 100644
index 00000000000..d84c5807a43
--- /dev/null
+++ b/arch/arm/mach-ixp2000/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
new file mode 100644
index 00000000000..4068166c899
--- /dev/null
+++ b/arch/arm/mach-ixp2000/core.c
@@ -0,0 +1,516 @@
1/*
2 * arch/arm/mach-ixp2000/core.c
3 *
4 * Common routines used by all IXP2400/2800 based platforms.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (C) MontaVista Software, Inc.
9 *
10 * Based on work Copyright (C) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/serial_8250.h>
27#include <linux/mm.h>
28
29#include <asm/types.h>
30#include <asm/setup.h>
31#include <asm/memory.h>
32#include <mach/hardware.h>
33#include <asm/irq.h>
34#include <asm/system.h>
35#include <asm/tlbflush.h>
36#include <asm/pgtable.h>
37
38#include <asm/mach/map.h>
39#include <asm/mach/time.h>
40#include <asm/mach/irq.h>
41
42#include <mach/gpio.h>
43
44static DEFINE_SPINLOCK(ixp2000_slowport_lock);
45static unsigned long ixp2000_slowport_irq_flags;
46
47/*************************************************************************
48 * Slowport access routines
49 *************************************************************************/
50void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
51{
52 spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
53
54 old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
55 old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
56 old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
57 old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
58 old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
59
60 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
61 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
62 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
63 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
64 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
65}
66
67void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
68{
69 ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
70 ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
71 ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
72 ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
73 ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
74
75 spin_unlock_irqrestore(&ixp2000_slowport_lock,
76 ixp2000_slowport_irq_flags);
77}
78
79/*************************************************************************
80 * Chip specific mappings shared by all IXP2000 systems
81 *************************************************************************/
82static struct map_desc ixp2000_io_desc[] __initdata = {
83 {
84 .virtual = IXP2000_CAP_VIRT_BASE,
85 .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
86 .length = IXP2000_CAP_SIZE,
87 .type = MT_DEVICE,
88 }, {
89 .virtual = IXP2000_INTCTL_VIRT_BASE,
90 .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
91 .length = IXP2000_INTCTL_SIZE,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = IXP2000_PCI_CREG_VIRT_BASE,
95 .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
96 .length = IXP2000_PCI_CREG_SIZE,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = IXP2000_PCI_CSR_VIRT_BASE,
100 .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
101 .length = IXP2000_PCI_CSR_SIZE,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = IXP2000_MSF_VIRT_BASE,
105 .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
106 .length = IXP2000_MSF_SIZE,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
110 .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
111 .length = IXP2000_SCRATCH_RING_SIZE,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = IXP2000_SRAM0_VIRT_BASE,
115 .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
116 .length = IXP2000_SRAM0_SIZE,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = IXP2000_PCI_IO_VIRT_BASE,
120 .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
121 .length = IXP2000_PCI_IO_SIZE,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = IXP2000_PCI_CFG0_VIRT_BASE,
125 .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
126 .length = IXP2000_PCI_CFG0_SIZE,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = IXP2000_PCI_CFG1_VIRT_BASE,
130 .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
131 .length = IXP2000_PCI_CFG1_SIZE,
132 .type = MT_DEVICE,
133 }
134};
135
136void __init ixp2000_map_io(void)
137{
138 iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
139
140 /* Set slowport to 8-bit mode. */
141 ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
142}
143
144
145/*************************************************************************
146 * Serial port support for IXP2000
147 *************************************************************************/
148static struct plat_serial8250_port ixp2000_serial_port[] = {
149 {
150 .mapbase = IXP2000_UART_PHYS_BASE,
151 .membase = (char *)(IXP2000_UART_VIRT_BASE + 3),
152 .irq = IRQ_IXP2000_UART,
153 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
154 .iotype = UPIO_MEM,
155 .regshift = 2,
156 .uartclk = 50000000,
157 },
158 { },
159};
160
161static struct resource ixp2000_uart_resource = {
162 .start = IXP2000_UART_PHYS_BASE,
163 .end = IXP2000_UART_PHYS_BASE + 0x1f,
164 .flags = IORESOURCE_MEM,
165};
166
167static struct platform_device ixp2000_serial_device = {
168 .name = "serial8250",
169 .id = PLAT8250_DEV_PLATFORM,
170 .dev = {
171 .platform_data = ixp2000_serial_port,
172 },
173 .num_resources = 1,
174 .resource = &ixp2000_uart_resource,
175};
176
177void __init ixp2000_uart_init(void)
178{
179 platform_device_register(&ixp2000_serial_device);
180}
181
182
183/*************************************************************************
184 * Timer-tick functions for IXP2000
185 *************************************************************************/
186static unsigned ticks_per_jiffy;
187static unsigned ticks_per_usec;
188static unsigned next_jiffy_time;
189static volatile unsigned long *missing_jiffy_timer_csr;
190
191unsigned long ixp2000_gettimeoffset (void)
192{
193 unsigned long offset;
194
195 offset = next_jiffy_time - *missing_jiffy_timer_csr;
196
197 return offset / ticks_per_usec;
198}
199
200static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
201{
202 /* clear timer 1 */
203 ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
204
205 while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
206 >= ticks_per_jiffy) {
207 timer_tick();
208 next_jiffy_time -= ticks_per_jiffy;
209 }
210
211 return IRQ_HANDLED;
212}
213
214static struct irqaction ixp2000_timer_irq = {
215 .name = "IXP2000 Timer Tick",
216 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
217 .handler = ixp2000_timer_interrupt,
218};
219
220void __init ixp2000_init_time(unsigned long tick_rate)
221{
222 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
223 ticks_per_usec = tick_rate / 1000000;
224
225 /*
226 * We use timer 1 as our timer interrupt.
227 */
228 ixp2000_reg_write(IXP2000_T1_CLR, 0);
229 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
230 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
231
232 /*
233 * We use a second timer as a monotonic counter for tracking
234 * missed jiffies. The IXP2000 has four timers, but if we're
235 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
236 * chips we use timer 4. Timer 4 is the only timer that can
237 * be used for the watchdog, so we use timer 2 if we're on a
238 * non-buggy chip.
239 */
240 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
241 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
242
243 ixp2000_reg_write(IXP2000_T4_CLR, 0);
244 ixp2000_reg_write(IXP2000_T4_CLD, -1);
245 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
246 missing_jiffy_timer_csr = IXP2000_T4_CSR;
247 } else {
248 ixp2000_reg_write(IXP2000_T2_CLR, 0);
249 ixp2000_reg_write(IXP2000_T2_CLD, -1);
250 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
251 missing_jiffy_timer_csr = IXP2000_T2_CSR;
252 }
253 next_jiffy_time = 0xffffffff;
254
255 /* register for interrupt */
256 setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
257}
258
259/*************************************************************************
260 * GPIO helpers
261 *************************************************************************/
262static unsigned long GPIO_IRQ_falling_edge;
263static unsigned long GPIO_IRQ_rising_edge;
264static unsigned long GPIO_IRQ_level_low;
265static unsigned long GPIO_IRQ_level_high;
266
267static void update_gpio_int_csrs(void)
268{
269 ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
270 ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
271 ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
272 ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
273}
274
275void gpio_line_config(int line, int direction)
276{
277 unsigned long flags;
278
279 local_irq_save(flags);
280 if (direction == GPIO_OUT) {
281 /* if it's an output, it ain't an interrupt anymore */
282 GPIO_IRQ_falling_edge &= ~(1 << line);
283 GPIO_IRQ_rising_edge &= ~(1 << line);
284 GPIO_IRQ_level_low &= ~(1 << line);
285 GPIO_IRQ_level_high &= ~(1 << line);
286 update_gpio_int_csrs();
287
288 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
289 } else if (direction == GPIO_IN) {
290 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
291 }
292 local_irq_restore(flags);
293}
294EXPORT_SYMBOL(gpio_line_config);
295
296
297/*************************************************************************
298 * IRQ handling IXP2000
299 *************************************************************************/
300static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
301{
302 int i;
303 unsigned long status = *IXP2000_GPIO_INST;
304
305 for (i = 0; i <= 7; i++) {
306 if (status & (1<<i)) {
307 generic_handle_irq(i + IRQ_IXP2000_GPIO0);
308 }
309 }
310}
311
312static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
313{
314 int line = d->irq - IRQ_IXP2000_GPIO0;
315
316 /*
317 * First, configure this GPIO line as an input.
318 */
319 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
320
321 /*
322 * Then, set the proper trigger type.
323 */
324 if (type & IRQ_TYPE_EDGE_FALLING)
325 GPIO_IRQ_falling_edge |= 1 << line;
326 else
327 GPIO_IRQ_falling_edge &= ~(1 << line);
328 if (type & IRQ_TYPE_EDGE_RISING)
329 GPIO_IRQ_rising_edge |= 1 << line;
330 else
331 GPIO_IRQ_rising_edge &= ~(1 << line);
332 if (type & IRQ_TYPE_LEVEL_LOW)
333 GPIO_IRQ_level_low |= 1 << line;
334 else
335 GPIO_IRQ_level_low &= ~(1 << line);
336 if (type & IRQ_TYPE_LEVEL_HIGH)
337 GPIO_IRQ_level_high |= 1 << line;
338 else
339 GPIO_IRQ_level_high &= ~(1 << line);
340 update_gpio_int_csrs();
341
342 return 0;
343}
344
345static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
346{
347 unsigned int irq = d->irq;
348
349 ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
350
351 ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
352 ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
353 ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
354}
355
356static void ixp2000_GPIO_irq_mask(struct irq_data *d)
357{
358 unsigned int irq = d->irq;
359
360 ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
361}
362
363static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
364{
365 unsigned int irq = d->irq;
366
367 ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
368}
369
370static struct irq_chip ixp2000_GPIO_irq_chip = {
371 .irq_ack = ixp2000_GPIO_irq_mask_ack,
372 .irq_mask = ixp2000_GPIO_irq_mask,
373 .irq_unmask = ixp2000_GPIO_irq_unmask,
374 .irq_set_type = ixp2000_GPIO_irq_type,
375};
376
377static void ixp2000_pci_irq_mask(struct irq_data *d)
378{
379 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
380 if (d->irq == IRQ_IXP2000_PCIA)
381 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
382 else if (d->irq == IRQ_IXP2000_PCIB)
383 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
384}
385
386static void ixp2000_pci_irq_unmask(struct irq_data *d)
387{
388 unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
389 if (d->irq == IRQ_IXP2000_PCIA)
390 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
391 else if (d->irq == IRQ_IXP2000_PCIB)
392 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
393}
394
395/*
396 * Error interrupts. These are used extensively by the microengine drivers
397 */
398static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
399{
400 int i;
401 unsigned long status = *IXP2000_IRQ_ERR_STATUS;
402
403 for(i = 31; i >= 0; i--) {
404 if(status & (1 << i)) {
405 generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
406 }
407 }
408}
409
410static void ixp2000_err_irq_mask(struct irq_data *d)
411{
412 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
413 (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
414}
415
416static void ixp2000_err_irq_unmask(struct irq_data *d)
417{
418 ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
419 (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
420}
421
422static struct irq_chip ixp2000_err_irq_chip = {
423 .irq_ack = ixp2000_err_irq_mask,
424 .irq_mask = ixp2000_err_irq_mask,
425 .irq_unmask = ixp2000_err_irq_unmask
426};
427
428static struct irq_chip ixp2000_pci_irq_chip = {
429 .irq_ack = ixp2000_pci_irq_mask,
430 .irq_mask = ixp2000_pci_irq_mask,
431 .irq_unmask = ixp2000_pci_irq_unmask
432};
433
434static void ixp2000_irq_mask(struct irq_data *d)
435{
436 ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
437}
438
439static void ixp2000_irq_unmask(struct irq_data *d)
440{
441 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
442}
443
444static struct irq_chip ixp2000_irq_chip = {
445 .irq_ack = ixp2000_irq_mask,
446 .irq_mask = ixp2000_irq_mask,
447 .irq_unmask = ixp2000_irq_unmask
448};
449
450void __init ixp2000_init_irq(void)
451{
452 int irq;
453
454 /*
455 * Mask all sources
456 */
457 ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
458 ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
459
460 /* clear all GPIO edge/level detects */
461 ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
462 ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
463 ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
464 ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
465 ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
466
467 /* clear PCI interrupt sources */
468 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
469
470 /*
471 * Certain bits in the IRQ status register of the
472 * IXP2000 are reserved. Instead of trying to map
473 * things non 1:1 from bit position to IRQ number,
474 * we mark the reserved IRQs as invalid. This makes
475 * our mask/unmask code much simpler.
476 */
477 for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
478 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
479 irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
480 handle_level_irq);
481 set_irq_flags(irq, IRQF_VALID);
482 } else set_irq_flags(irq, 0);
483 }
484
485 for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
486 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
487 IXP2000_VALID_ERR_IRQ_MASK) {
488 irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
489 handle_level_irq);
490 set_irq_flags(irq, IRQF_VALID);
491 }
492 else
493 set_irq_flags(irq, 0);
494 }
495 irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
496
497 for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
498 irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
499 handle_level_irq);
500 set_irq_flags(irq, IRQF_VALID);
501 }
502 irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
503
504 /*
505 * Enable PCI irqs. The actual PCI[AB] decoding is done in
506 * entry-macro.S, so we don't need a chained handler for the
507 * PCI interrupt source.
508 */
509 ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
510 for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
511 irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
512 handle_level_irq);
513 set_irq_flags(irq, IRQF_VALID);
514 }
515}
516
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
new file mode 100644
index 00000000000..62c60ade527
--- /dev/null
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -0,0 +1,264 @@
1/*
2 * arch/arm/mach-ixp2000/enp2611.c
3 *
4 * Radisys ENP-2611 support.
5 *
6 * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
7 * original version carries the following notices:
8 *
9 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
10 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
11 *
12 * Copyright (C) 2002-2003 Intel Corp.
13 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/sched.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27#include <linux/pci.h>
28#include <linux/ioport.h>
29#include <linux/delay.h>
30#include <linux/serial.h>
31#include <linux/tty.h>
32#include <linux/serial_core.h>
33#include <linux/platform_device.h>
34#include <linux/io.h>
35
36#include <asm/irq.h>
37#include <asm/pgtable.h>
38#include <asm/page.h>
39#include <asm/system.h>
40#include <mach/hardware.h>
41#include <asm/mach-types.h>
42
43#include <asm/mach/pci.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46#include <asm/mach/time.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/flash.h>
49
50/*************************************************************************
51 * ENP-2611 timer tick configuration
52 *************************************************************************/
53static void __init enp2611_timer_init(void)
54{
55 ixp2000_init_time(50 * 1000 * 1000);
56}
57
58static struct sys_timer enp2611_timer = {
59 .init = enp2611_timer_init,
60 .offset = ixp2000_gettimeoffset,
61};
62
63
64/*************************************************************************
65 * ENP-2611 I/O
66 *************************************************************************/
67static struct map_desc enp2611_io_desc[] __initdata = {
68 {
69 .virtual = ENP2611_CALEB_VIRT_BASE,
70 .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
71 .length = ENP2611_CALEB_SIZE,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = ENP2611_PM3386_0_VIRT_BASE,
75 .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
76 .length = ENP2611_PM3386_0_SIZE,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = ENP2611_PM3386_1_VIRT_BASE,
80 .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
81 .length = ENP2611_PM3386_1_SIZE,
82 .type = MT_DEVICE,
83 }
84};
85
86void __init enp2611_map_io(void)
87{
88 ixp2000_map_io();
89 iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc));
90}
91
92
93/*************************************************************************
94 * ENP-2611 PCI
95 *************************************************************************/
96static int enp2611_pci_setup(int nr, struct pci_sys_data *sys)
97{
98 sys->mem_offset = 0xe0000000;
99 ixp2000_pci_setup(nr, sys);
100 return 1;
101}
102
103static void __init enp2611_pci_preinit(void)
104{
105 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
106 ixp2000_pci_preinit();
107 pcibios_setup("firmware");
108}
109
110static inline int enp2611_pci_valid_device(struct pci_bus *bus,
111 unsigned int devfn)
112{
113 /* The 82559 ethernet controller appears at both PCI:1:0:0 and
114 * PCI:1:2:0, so let's pretend the second one isn't there.
115 */
116 if (bus->number == 0x01 && devfn == 0x10)
117 return 0;
118
119 return 1;
120}
121
122static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn,
123 int where, int size, u32 *value)
124{
125 if (enp2611_pci_valid_device(bus, devfn))
126 return ixp2000_pci_read_config(bus, devfn, where, size, value);
127
128 return PCIBIOS_DEVICE_NOT_FOUND;
129}
130
131static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn,
132 int where, int size, u32 value)
133{
134 if (enp2611_pci_valid_device(bus, devfn))
135 return ixp2000_pci_write_config(bus, devfn, where, size, value);
136
137 return PCIBIOS_DEVICE_NOT_FOUND;
138}
139
140static struct pci_ops enp2611_pci_ops = {
141 .read = enp2611_pci_read_config,
142 .write = enp2611_pci_write_config
143};
144
145static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
146 struct pci_sys_data *sys)
147{
148 return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys);
149}
150
151static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
152 u8 pin)
153{
154 int irq;
155
156 if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) {
157 /* IXP2400. */
158 irq = IRQ_IXP2000_PCIA;
159 } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) {
160 /* 21555 non-transparent bridge. */
161 irq = IRQ_IXP2000_PCIB;
162 } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) {
163 /* PCI2050B transparent bridge. */
164 irq = -1;
165 } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) {
166 /* 82559 ethernet. */
167 irq = IRQ_IXP2000_PCIA;
168 } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) {
169 /* SPI-3 option board. */
170 irq = IRQ_IXP2000_PCIB;
171 } else {
172 printk(KERN_ERR "enp2611_pci_map_irq() called for unknown "
173 "device PCI:%d:%d:%d\n", dev->bus->number,
174 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
175 irq = -1;
176 }
177
178 return irq;
179}
180
181struct hw_pci enp2611_pci __initdata = {
182 .nr_controllers = 1,
183 .setup = enp2611_pci_setup,
184 .preinit = enp2611_pci_preinit,
185 .scan = enp2611_pci_scan_bus,
186 .map_irq = enp2611_pci_map_irq,
187};
188
189int __init enp2611_pci_init(void)
190{
191 if (machine_is_enp2611())
192 pci_common_init(&enp2611_pci);
193
194 return 0;
195}
196
197subsys_initcall(enp2611_pci_init);
198
199
200/*************************************************************************
201 * ENP-2611 Machine Initialization
202 *************************************************************************/
203static struct flash_platform_data enp2611_flash_platform_data = {
204 .map_name = "cfi_probe",
205 .width = 1,
206};
207
208static struct ixp2000_flash_data enp2611_flash_data = {
209 .platform_data = &enp2611_flash_platform_data,
210 .nr_banks = 1
211};
212
213static struct resource enp2611_flash_resource = {
214 .start = 0xc4000000,
215 .end = 0xc4000000 + 0x00ffffff,
216 .flags = IORESOURCE_MEM,
217};
218
219static struct platform_device enp2611_flash = {
220 .name = "IXP2000-Flash",
221 .id = 0,
222 .dev = {
223 .platform_data = &enp2611_flash_data,
224 },
225 .num_resources = 1,
226 .resource = &enp2611_flash_resource,
227};
228
229static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = {
230 .sda_pin = ENP2611_GPIO_SDA,
231 .scl_pin = ENP2611_GPIO_SCL,
232};
233
234static struct platform_device enp2611_i2c_controller = {
235 .name = "IXP2000-I2C",
236 .id = 0,
237 .dev = {
238 .platform_data = &enp2611_i2c_gpio_pins
239 },
240 .num_resources = 0
241};
242
243static struct platform_device *enp2611_devices[] __initdata = {
244 &enp2611_flash,
245 &enp2611_i2c_controller
246};
247
248static void __init enp2611_init_machine(void)
249{
250 platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices));
251 ixp2000_uart_init();
252}
253
254
255MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
256 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
257 .boot_params = 0x00000100,
258 .map_io = enp2611_map_io,
259 .init_irq = ixp2000_init_irq,
260 .timer = &enp2611_timer,
261 .init_machine = enp2611_init_machine,
262MACHINE_END
263
264
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
new file mode 100644
index 00000000000..0ef533b2097
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -0,0 +1,25 @@
1/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart, rp, rv
15 mov \rp, #0x00030000
16#ifdef __ARMEB__
17 orr \rp, \rp, #0x00000003
18#endif
19 orr \rv, \rp, #0xfe000000 @ virtual base
20 orr \rv, \rv, #0x00f00000
21 orr \rp, \rp, #0xc0000000 @ Physical base
22 .endm
23
24#define UART_SHIFT 2
25#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h
new file mode 100644
index 00000000000..9ce3690061d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/enp2611.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/enp2611.h
3 *
4 * Register and other defines for Radisys ENP-2611
5 *
6 * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The
7 * original version carries the following notices:
8 *
9 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
10 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
11 *
12 * Copyright (C) 2002 Intel Corp.
13 * Copyright (C) 2003-2004 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifndef __ENP2611_H
22#define __ENP2611_H
23
24#define ENP2611_CALEB_PHYS_BASE 0xc5000000
25#define ENP2611_CALEB_VIRT_BASE 0xfe000000
26#define ENP2611_CALEB_SIZE 0x00100000
27
28#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000
29#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000
30#define ENP2611_PM3386_0_SIZE 0x00100000
31
32#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000
33#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000
34#define ENP2611_PM3386_1_SIZE 0x00100000
35
36#define ENP2611_GPIO_SCL 7
37#define ENP2611_GPIO_SDA 6
38
39#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4
40#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3
41#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2
42#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1
43#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0
44
45
46#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
new file mode 100644
index 00000000000..5850ffc8c75
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
@@ -0,0 +1,60 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IXP2000-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/irqs.h>
11
12 .macro disable_fiq
13 .endm
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22
23 mov \irqnr, #0x0 @clear out irqnr as default
24 mov \base, #0xfe000000
25 orr \base, \base, #0x00e00000
26 orr \base, \base, #0x08
27 ldr \irqstat, [\base] @ get interrupts
28
29 cmp \irqstat, #0
30 beq 1001f
31
32 clz \irqnr, \irqstat
33 mov \base, #31
34 subs \irqnr, \base, \irqnr
35
36 /*
37 * We handle PCIA and PCIB here so we don't have an
38 * extra layer of code just to check these two bits.
39 */
40 cmp \irqnr, #IRQ_IXP2000_PCI
41 bne 1001f
42
43 mov \base, #0xfe000000
44 orr \base, \base, #0x00c00000
45 orr \base, \base, #0x00000100
46 orr \base, \base, #0x00000058
47 ldr \irqstat, [\base]
48
49 mov \tmp, #(1<<26)
50 tst \irqstat, \tmp
51 movne \irqnr, #IRQ_IXP2000_PCIA
52 bne 1001f
53
54 mov \tmp, #(1<<27)
55 tst \irqstat, \tmp
56 movne \irqnr, #IRQ_IXP2000_PCIB
57
581001:
59 .endm
60
diff --git a/arch/arm/mach-ixp2000/include/mach/gpio.h b/arch/arm/mach-ixp2000/include/mach/gpio.h
new file mode 100644
index 00000000000..4a88d2c33da
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/gpio.h
@@ -0,0 +1,48 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/gpio.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software, you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * IXP2000 GPIO in/out, edge/level detection for IRQs:
13 * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
14 * or both Falling-edge and Rising-edge.
15 * This must be called *before* the corresponding IRQ is registerd.
16 * Use this instead of directly setting the GPIO registers.
17 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
18 */
19#ifndef __ASM_ARCH_GPIO_H
20#define __ASM_ARCH_GPIO_H
21
22#ifndef __ASSEMBLY__
23
24#define GPIO_IN 0
25#define GPIO_OUT 1
26
27#define IXP2000_GPIO_LOW 0
28#define IXP2000_GPIO_HIGH 1
29
30extern void gpio_line_config(int line, int direction);
31
32static inline int gpio_line_get(int line)
33{
34 return (((*IXP2000_GPIO_PLR) >> line) & 1);
35}
36
37static inline void gpio_line_set(int line, int value)
38{
39 if (value == IXP2000_GPIO_HIGH) {
40 ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
41 } else if (value == IXP2000_GPIO_LOW) {
42 ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
43 }
44}
45
46#endif /* !__ASSEMBLY__ */
47
48#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
new file mode 100644
index 00000000000..cdaf1db8400
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/hardware.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/hardware.h
3 *
4 * Hardware definitions for IXP2400/2800 based systems
5 *
6 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@mvista.com>
9 *
10 * Copyright (C) 2001-2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#ifndef __ASM_ARCH_HARDWARE_H__
20#define __ASM_ARCH_HARDWARE_H__
21
22#include "ixp2000-regs.h" /* Chipset Registers */
23
24/*
25 * Platform helper functions
26 */
27#include "platform.h"
28
29/*
30 * Platform-specific bits
31 */
32#include "enp2611.h" /* ENP-2611 */
33#include "ixdp2x00.h" /* IXDP2400/2800 */
34#include "ixdp2x01.h" /* IXDP2401/2801 */
35
36#endif /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
new file mode 100644
index 00000000000..859e584914d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -0,0 +1,134 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H
17
18#include <mach/hardware.h>
19
20#define IO_SPACE_LIMIT 0xffffffff
21#define __mem_pci(a) (a)
22
23/*
24 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
25 * transactions the other way round (MEM transactions don't have this
26 * issue), so if we want to support those models, we need to override
27 * the standard I/O functions.
28 *
29 * B0 and later have a bit that can be set to 1 to get the proper
30 * behavior for I/O transactions, which then allows us to use the
31 * standard I/O functions. This is what we do if the user does not
32 * explicitly ask for support for pre-B0.
33 */
34#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
35#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
36
37#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
38#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
39
40#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
41#define outw(v,p) __raw_writew((v),alignw(___io(p)))
42#define outl(v,p) __raw_writel((v),___io(p))
43
44#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
45#define inw(p) \
46 ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
47#define inl(p) \
48 ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
49
50#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
51#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
52#define outsl(p,d,l) __raw_writesl(___io(p),d,l)
53
54#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
55#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
56#define insl(p,d,l) __raw_readsl(___io(p),d,l)
57
58#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
59
60#define ioread8(p) \
61 ({ \
62 unsigned int __v; \
63 \
64 if (__is_io_address(p)) { \
65 __v = __raw_readb(alignb(p)); \
66 } else { \
67 __v = __raw_readb(p); \
68 } \
69 \
70 __v; \
71 }) \
72
73#define ioread16(p) \
74 ({ \
75 unsigned int __v; \
76 \
77 if (__is_io_address(p)) { \
78 __v = __raw_readw(alignw(p)); \
79 } else { \
80 __v = le16_to_cpu(__raw_readw(p)); \
81 } \
82 \
83 __v; \
84 })
85
86#define ioread32(p) \
87 ({ \
88 unsigned int __v; \
89 \
90 if (__is_io_address(p)) { \
91 __v = __raw_readl(p); \
92 } else { \
93 __v = le32_to_cpu(__raw_readl(p)); \
94 } \
95 \
96 __v; \
97 })
98
99#define iowrite8(v,p) \
100 ({ \
101 if (__is_io_address(p)) { \
102 __raw_writeb((v), alignb(p)); \
103 } else { \
104 __raw_writeb((v), p); \
105 } \
106 })
107
108#define iowrite16(v,p) \
109 ({ \
110 if (__is_io_address(p)) { \
111 __raw_writew((v), alignw(p)); \
112 } else { \
113 __raw_writew(cpu_to_le16(v), p); \
114 } \
115 })
116
117#define iowrite32(v,p) \
118 ({ \
119 if (__is_io_address(p)) { \
120 __raw_writel((v), p); \
121 } else { \
122 __raw_writel(cpu_to_le32(v), p); \
123 } \
124 })
125
126#define ioport_map(port, nr) ___io(port)
127
128#define ioport_unmap(addr)
129#else
130#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
131#endif
132
133
134#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h
new file mode 100644
index 00000000000..bee96bcafdc
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/irqs.h
@@ -0,0 +1,207 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/irqs.h
3 *
4 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IRQS_H
16#define _IRQS_H
17
18/*
19 * Do NOT add #ifdef MACHINE_FOO in here.
20 * Simpy add your machine IRQs here and increase NR_IRQS if needed to
21 * hold your machine's IRQ table.
22 */
23
24/*
25 * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
26 * register has those bit reserved. We just mark those interrupts
27 * as invalid and this allows us to do mask/unmask with a single
28 * shift operation instead of having to map the IRQ number to
29 * a HW IRQ number.
30 */
31#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */
32#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
33#define IRQ_IXP2000_UART 2
34#define IRQ_IXP2000_GPIO 3
35#define IRQ_IXP2000_TIMER1 4
36#define IRQ_IXP2000_TIMER2 5
37#define IRQ_IXP2000_TIMER3 6
38#define IRQ_IXP2000_TIMER4 7
39#define IRQ_IXP2000_PMU 8
40#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
41#define IRQ_IXP2000_DMA1 10
42#define IRQ_IXP2000_DMA2 11
43#define IRQ_IXP2000_DMA3 12
44#define IRQ_IXP2000_PCI_DOORBELL 13
45#define IRQ_IXP2000_ME_ATTN 14
46#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
47#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
48#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */
49#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
50#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */
51#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */
52#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */
53#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
54#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */
55
56/* define generic GPIOs */
57#define IRQ_IXP2000_GPIO0 32
58#define IRQ_IXP2000_GPIO1 33
59#define IRQ_IXP2000_GPIO2 34
60#define IRQ_IXP2000_GPIO3 35
61#define IRQ_IXP2000_GPIO4 36
62#define IRQ_IXP2000_GPIO5 37
63#define IRQ_IXP2000_GPIO6 38
64#define IRQ_IXP2000_GPIO7 39
65
66/* split off the 2 PCI sources */
67#define IRQ_IXP2000_PCIA 40
68#define IRQ_IXP2000_PCIB 41
69
70/* Int sources from IRQ_ERROR_STATUS */
71#define IRQ_IXP2000_DRAM0_MIN_ERR 42
72#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
73#define IRQ_IXP2000_DRAM1_MIN_ERR 44
74#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
75#define IRQ_IXP2000_DRAM2_MIN_ERR 46
76#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
77/* 48-57 reserved */
78#define IRQ_IXP2000_SRAM0_ERR 58
79#define IRQ_IXP2000_SRAM1_ERR 59
80#define IRQ_IXP2000_SRAM2_ERR 60
81#define IRQ_IXP2000_SRAM3_ERR 61
82/* 62-65 reserved */
83#define IRQ_IXP2000_MEDIA_ERR 66
84#define IRQ_IXP2000_PCI_ERR 67
85#define IRQ_IXP2000_SP_INT 68
86
87#define NR_IXP2000_IRQS 69
88
89#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
90
91#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
92
93#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
94#define IXP2000_VALID_ERR_IRQ_MASK (\
95 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
96 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
97 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
98 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
99 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
100 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
101 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
102 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
103 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
104 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
105 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
106 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
107 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
108
109/*
110 * This allows for all the on-chip sources plus up to 32 CPLD based
111 * IRQs. Should be more than enough.
112 */
113#define IXP2000_BOARD_IRQS 32
114#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
115
116
117/*
118 * IXDP2400 specific IRQs
119 */
120#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
121#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
122#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
123#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
124#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
125#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
126#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
127#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
128
129#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
130#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
131
132/* IXDP2800 specific IRQs */
133#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
134#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
135#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
136#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
137#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
138#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
139
140#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
141#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
142
143/*
144 * IRQs on both IXDP2x01 boards
145 */
146#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
147#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
148#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
149#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
150#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
151#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
152#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
153#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
154#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
155#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
156#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
157#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
158#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
159#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
160#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
161#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
162
163#define IXDP2X01_VALID_IRQ_MASK ( \
164 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
165 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
166 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
167 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
168 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
169 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
170 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
171 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
172 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
173 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
174 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
175 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
176 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
177 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
178 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
179 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
180
181/*
182 * IXDP2401 specific IRQs
183 */
184#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
185#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
186
187#define IXDP2401_VALID_IRQ_MASK ( \
188 IXDP2X01_VALID_IRQ_MASK | \
189 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
190 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
191
192/*
193 * IXDP2801-specific IRQs
194 */
195#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
196#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
197#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
198
199#define IXDP2801_VALID_IRQ_MASK ( \
200 IXDP2X01_VALID_IRQ_MASK | \
201 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
202 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
203 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
204
205#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
206
207#endif /*_IRQS_H*/
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
new file mode 100644
index 00000000000..5df8479d948
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
@@ -0,0 +1,92 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
3 *
4 * Register and other defines for IXDP2[48]00 platforms
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#ifndef _IXDP2X00_H_
18#define _IXDP2X00_H_
19
20/*
21 * On board CPLD memory map
22 */
23#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
24#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000
25#define IXDP2X00_CPLD_SIZE 0x00100000
26
27
28#define IXDP2X00_CPLD_REG(x) \
29 (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
30
31/*
32 * IXDP2400 CPLD registers
33 */
34#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0)
35#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4)
36#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8)
37#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc)
38#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10)
39#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14)
40#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18)
41#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48)
42
43/*
44 * IXDP2800 CPLD registers
45 */
46#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0)
47#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140)
48
49
50#define IXDP2X00_GPIO_I2C_ENABLE 0x02
51#define IXDP2X00_GPIO_SCL 0x07
52#define IXDP2X00_GPIO_SDA 0x06
53
54/*
55 * PCI devfns for on-board devices. We need these to be able to
56 * properly translate IRQs and for device removal.
57 */
58#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */
59#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */
60#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */
61#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
62
63#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */
64#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */
65#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */
66
67#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */
68#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */
69#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */
70#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */
71#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */
72
73#ifndef __ASSEMBLY__
74/*
75 * The master NPU is always PCI master.
76 */
77static inline unsigned int ixdp2x00_master_npu(void)
78{
79 return !!ixp2000_is_pcimaster();
80}
81
82/*
83 * Helper functions used by ixdp2400 and ixdp2800 specific code
84 */
85void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
86void ixdp2x00_slave_pci_postinit(void);
87void ixdp2x00_init_machine(void);
88void ixdp2x00_map_io(void);
89
90#endif
91
92#endif /*_IXDP2X00_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
new file mode 100644
index 00000000000..4c1f04083e5
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
@@ -0,0 +1,57 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
3 *
4 * Platform definitions for IXDP2X01 && IXDP2801 systems
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * Based on original code Copyright (c) 2002-2003 Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __IXDP2X01_H__
18#define __IXDP2X01_H__
19
20#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
21#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000
22#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
23
24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
25#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
26
27#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
28#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
29
30#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60)
31#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60)
32
33#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80)
34#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16)
35
36#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00)
37#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08)
38#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C)
39#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10)
40#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG
41#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14)
42
43#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20)
44
45#define IXDP2X01_CPLD_FLASH_INTERN 0x8000
46#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF
47#define IXDP2X01_FLASH_WINDOW_BITS 25
48#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS)
49#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1)
50
51#define IXDP2X01_UART_CLK 1843200
52
53#define IXDP2X01_GPIO_I2C_ENABLE 0x02
54#define IXDP2X01_GPIO_SCL 0x07
55#define IXDP2X01_GPIO_SDA 0x06
56
57#endif /* __IXDP2x01_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
new file mode 100644
index 00000000000..822f63f2f4a
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
@@ -0,0 +1,451 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
3 *
4 * Chipset register definitions for IXP2400/2800 based systems.
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
9 *
10 * Copyright (C) 2002 Intel Corp.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _IXP2000_REGS_H_
19#define _IXP2000_REGS_H_
20
21/*
22 * IXP2000 linux memory map:
23 *
24 * virt phys size
25 * fb000000 db000000 16M PCI CFG1
26 * fc000000 da000000 16M PCI CFG0
27 * fd000000 d8000000 16M PCI I/O
28 * fe[0-7]00000 8M per-platform mappings
29 * fe900000 80000000 1M SRAM #0 (first MB)
30 * fea00000 cb400000 1M SCRATCH ring get/put
31 * feb00000 c8000000 1M MSF
32 * fec00000 df000000 1M PCI CSRs
33 * fed00000 de000000 1M PCI CREG
34 * fee00000 d6000000 1M INTCTL
35 * fef00000 c0000000 1M CAP
36 */
37
38/*
39 * Static I/O regions.
40 *
41 * Most of the registers are clumped in 4K regions spread throughout
42 * the 0xc0000000 -> 0xc0100000 address range, but we just map in
43 * the whole range using a single 1 MB section instead of small
44 * 4K pages.
45 *
46 * CAP stands for CSR Access Proxy.
47 *
48 * If you change the virtual address of this mapping, please propagate
49 * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
50 * address of the UART located in this region.
51 */
52
53#define IXP2000_CAP_PHYS_BASE 0xc0000000
54#define IXP2000_CAP_VIRT_BASE 0xfef00000
55#define IXP2000_CAP_SIZE 0x00100000
56
57/*
58 * Addresses for specific on-chip peripherals.
59 */
60#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
61#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
62#define IXP2000_UART_PHYS_BASE 0xc0030000
63#define IXP2000_UART_VIRT_BASE 0xfef30000
64#define IXP2000_TIMER_VIRT_BASE 0xfef20000
65#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
66#define IXP2000_GPIO_VIRT_BASE 0xfef10000
67
68/*
69 * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
70 * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
71 * entry-macro.S, so if you ever change these please propagate
72 * the change.
73 */
74#define IXP2000_INTCTL_PHYS_BASE 0xd6000000
75#define IXP2000_INTCTL_VIRT_BASE 0xfee00000
76#define IXP2000_INTCTL_SIZE 0x00100000
77
78#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
79#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000
80#define IXP2000_PCI_CREG_SIZE 0x00100000
81
82#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
83#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
84#define IXP2000_PCI_CSR_SIZE 0x00100000
85
86#define IXP2000_MSF_PHYS_BASE 0xc8000000
87#define IXP2000_MSF_VIRT_BASE 0xfeb00000
88#define IXP2000_MSF_SIZE 0x00100000
89
90#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
91#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
92#define IXP2000_SCRATCH_RING_SIZE 0x00100000
93
94#define IXP2000_SRAM0_PHYS_BASE 0x80000000
95#define IXP2000_SRAM0_VIRT_BASE 0xfe900000
96#define IXP2000_SRAM0_SIZE 0x00100000
97
98#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
99#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
100#define IXP2000_PCI_IO_SIZE 0x01000000
101
102#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
103#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
104#define IXP2000_PCI_CFG0_SIZE 0x01000000
105
106#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
107#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
108#define IXP2000_PCI_CFG1_SIZE 0x01000000
109
110/*
111 * Timers
112 */
113#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
114/* Timer control */
115#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
116#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
117#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
118#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
119/* Store initial value */
120#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
121#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
122#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
123#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
124/* Read current value */
125#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
126#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
127#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
128#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
129/* Clear associated timer interrupt */
130#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
131#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
132#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
133#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
134/* Timer watchdog enable for T4 */
135#define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
136
137#define WDT_ENABLE 0x00000001
138#define TIMER_DIVIDER_256 0x00000008
139#define TIMER_ENABLE 0x00000080
140#define IRQ_MASK_TIMER1 (1 << 4)
141
142/*
143 * Interrupt controller registers
144 */
145#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
146#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
147#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
148#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
149#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
150#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
151#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
152#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
153#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
154#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
155#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60)
156#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64)
157#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68)
158#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c)
159#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80)
160#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84)
161#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88)
162#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c)
163#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0)
164#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4)
165#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8)
166#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec)
167#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100)
168#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104)
169#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108)
170#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c)
171#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160)
172#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164)
173#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168)
174#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c)
175#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180)
176#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184)
177#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188)
178#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c)
179#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0)
180#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4)
181#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8)
182#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec)
183#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200)
184#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204)
185#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208)
186#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c)
187
188/*
189 * Mask of valid IRQs in the 32-bit IRQ register. We use
190 * this to mark certain IRQs as being invalid.
191 */
192#define IXP2000_VALID_IRQ_MASK 0x0f0fffff
193
194/*
195 * PCI config register access from core
196 */
197#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
198#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
199#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
200#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
201#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
202
203/*
204 * PCI CSRs
205 */
206#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
207
208/*
209 * PCI outbound interrupts
210 */
211#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
212#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
213/*
214 * PCI communications
215 */
216#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
217#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
218#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
219#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
220#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
221#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
222#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
223#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
224
225/*
226 * DMA engines
227 */
228#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
229#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
230#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
231#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
232#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
233#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
234#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
235#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
236#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
237#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
238#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
239#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
240#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
241#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
242#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
243#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
244#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
245#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
246#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
247/*
248 * Size masks for BARs
249 */
250#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
251#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
252/*
253 * Control and uEngine related
254 */
255#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
256#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
257#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
258#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
259#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
260#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
261/*
262 * Inbound PCI interrupt control
263 */
264#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
265#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
266
267#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
268#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */
269#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
270
271/* These are from the IRQ register in the PCI ISR register */
272#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
273#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
274#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
275#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
276#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
277
278#define IXP2000_PCI_RST_REL (1 << 2)
279#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
280#define CFG_PCI_BOOT_HOST (1 << 2)
281#define CFG_BOOT_PROM (1 << 1)
282
283/*
284 * SlowPort CSRs
285 *
286 * The slowport is used to access things like flash, SONET framer control
287 * ports, slave microprocessors, CPLDs, and others of chip memory mapped
288 * peripherals.
289 */
290#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
291
292#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
293#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
294#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
295#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
296#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
297#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
298#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
299#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
300#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
301#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
302#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
303
304/*
305 * CCR values.
306 * The CCR configures the clock division for the slowport interface.
307 */
308#define SLOWPORT_CCR_DIV_1 0x00
309#define SLOWPORT_CCR_DIV_2 0x01
310#define SLOWPORT_CCR_DIV_4 0x02
311#define SLOWPORT_CCR_DIV_6 0x03
312#define SLOWPORT_CCR_DIV_8 0x04
313#define SLOWPORT_CCR_DIV_10 0x05
314#define SLOWPORT_CCR_DIV_12 0x06
315#define SLOWPORT_CCR_DIV_14 0x07
316#define SLOWPORT_CCR_DIV_16 0x08
317#define SLOWPORT_CCR_DIV_18 0x09
318#define SLOWPORT_CCR_DIV_20 0x0a
319#define SLOWPORT_CCR_DIV_22 0x0b
320#define SLOWPORT_CCR_DIV_24 0x0c
321#define SLOWPORT_CCR_DIV_26 0x0d
322#define SLOWPORT_CCR_DIV_28 0x0e
323#define SLOWPORT_CCR_DIV_30 0x0f
324
325/*
326 * PCR values. PCR configure the mode of the interface.
327 */
328#define SLOWPORT_MODE_FLASH 0x00
329#define SLOWPORT_MODE_LUCENT 0x01
330#define SLOWPORT_MODE_PMC_SIERRA 0x02
331#define SLOWPORT_MODE_INTEL_UP 0x03
332#define SLOWPORT_MODE_MOTOROLA_UP 0x04
333
334/*
335 * ADC values. Defines data and address bus widths.
336 */
337#define SLOWPORT_ADDR_WIDTH_8 0x00
338#define SLOWPORT_ADDR_WIDTH_16 0x01
339#define SLOWPORT_ADDR_WIDTH_24 0x02
340#define SLOWPORT_ADDR_WIDTH_32 0x03
341#define SLOWPORT_DATA_WIDTH_8 0x00
342#define SLOWPORT_DATA_WIDTH_16 0x10
343#define SLOWPORT_DATA_WIDTH_24 0x20
344#define SLOWPORT_DATA_WIDTH_32 0x30
345
346/*
347 * Masks and shifts for various fields in the WTC and RTC registers.
348 */
349#define SLOWPORT_WRTC_MASK_HD 0x0003
350#define SLOWPORT_WRTC_MASK_PW 0x003c
351#define SLOWPORT_WRTC_MASK_SU 0x03c0
352
353#define SLOWPORT_WRTC_SHIFT_HD 0x00
354#define SLOWPORT_WRTC_SHIFT_SU 0x02
355#define SLOWPORT_WRTC_SHFIT_PW 0x06
356
357
358/*
359 * GPIO registers & GPIO interface.
360 */
361#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
362#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
363#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
364#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
365#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
366#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
367#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
368#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
369#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
370#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
371#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
372#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
373#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
374#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
375#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
376#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
377#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
378#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
379
380/*
381 * "Global" registers...whatever that's supposed to mean.
382 */
383#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
384#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
385
386#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
387#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
388#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
389#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
390#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
391#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
392#define IXP2000_MAJ_REV_MASK 0x000000F0
393#define IXP2000_MIN_REV_MASK 0x0000000F
394#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
395
396#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00)
397#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
398#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
399#define IXP2000_RESET0 GLOBAL_REG(0x0c)
400#define IXP2000_RESET1 GLOBAL_REG(0x10)
401#define IXP2000_CCR GLOBAL_REG(0x14)
402#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
403
404#define RSTALL (1 << 16)
405#define WDT_RESET_ENABLE 0x01000000
406
407
408/*
409 * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
410 * units, but the registers that differ between the two don't overlap,
411 * so we can have one register list for both.
412 */
413#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
414#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
415#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
416#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
417#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
418#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
419#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
420#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
421#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
422#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
423#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
424#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
425#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
426#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
427#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
428#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
429#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
430#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
431#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
432#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
433#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
434#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
435#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
436#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
437#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
438#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
439#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
440#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
441#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
442#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
443#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
444#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
445#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
446#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
447#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
448#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
449
450
451#endif /* _IXP2000_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
new file mode 100644
index 00000000000..5f0c4fd4076
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/memory.h
@@ -0,0 +1,31 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/memory.h
3 *
4 * Copyright (c) 2002 Intel Corp.
5 * Copyright (c) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x00000000)
17
18#include <mach/ixp2000-regs.h>
19
20#define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)
21
22#define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
23#define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
24
25#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
26#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
27#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
28#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
29
30#endif
31
diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h
new file mode 100644
index 00000000000..42182c79ed9
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/platform.h
@@ -0,0 +1,152 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15
16#ifndef __ASSEMBLY__
17
18static inline unsigned long ixp2000_reg_read(volatile void *reg)
19{
20 return *((volatile unsigned long *)reg);
21}
22
23static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
24{
25 *((volatile unsigned long *)reg) = val;
26}
27
28/*
29 * On the IXP2400, we can't use XCB=000 due to chip bugs. We use
30 * XCB=101 instead, but that makes all I/O accesses bufferable. This
31 * is not a problem in general, but we do have to be slightly more
32 * careful because I/O writes are no longer automatically flushed out
33 * of the write buffer.
34 *
35 * In cases where we want to make sure that a write has been flushed
36 * out of the write buffer before we proceed, for example when masking
37 * a device interrupt before re-enabling IRQs in CPSR, we can use this
38 * function, ixp2000_reg_wrb, which performs a write, a readback, and
39 * issues a dummy instruction dependent on the value of the readback
40 * (mov rX, rX) to make sure that the readback has completed before we
41 * continue.
42 */
43static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
44{
45 unsigned long dummy;
46
47 *((volatile unsigned long *)reg) = val;
48
49 dummy = *((volatile unsigned long *)reg);
50 __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
51}
52
53/*
54 * Boards may multiplex different devices on the 2nd channel of
55 * the slowport interface that each need different configuration
56 * settings. For example, the IXDP2400 uses channel 2 on the interface
57 * to access the CPLD, the switch fabric card, and the media card. Each
58 * one needs a different mode so drivers must save/restore the mode
59 * before and after each operation.
60 *
61 * acquire_slowport(&your_config);
62 * ...
63 * do slowport operations
64 * ...
65 * release_slowport();
66 *
67 * Note that while you have the slowport, you are holding a spinlock,
68 * so your code should be written as if you explicitly acquired a lock.
69 *
70 * The configuration only affects device 2 on the slowport, so the
71 * MTD map driver does not acquire/release the slowport.
72 */
73struct slowport_cfg {
74 unsigned long CCR; /* Clock divide */
75 unsigned long WTC; /* Write Timing Control */
76 unsigned long RTC; /* Read Timing Control */
77 unsigned long PCR; /* Protocol Control Register */
78 unsigned long ADC; /* Address/Data Width Control */
79};
80
81
82void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
83void ixp2000_release_slowport(struct slowport_cfg *);
84
85/*
86 * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires
87 * tweaking of addresses in the MTD driver.
88 */
89static inline unsigned ixp2000_has_broken_slowport(void)
90{
91 unsigned long id = *IXP2000_PRODUCT_ID;
92 unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
93 IXP2000_MIN_PROD_TYPE_MASK);
94 return (((id_prod ==
95 /* fixed in IXP2400-B0 */
96 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
97 IXP2000_MIN_PROD_TYPE_IXP2400)) &&
98 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
99 ((id_prod ==
100 /* fixed in IXP2800-B0 */
101 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
102 IXP2000_MIN_PROD_TYPE_IXP2800)) &&
103 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
104 ((id_prod ==
105 /* fixed in IXP2850-B0 */
106 (IXP2000_MAJ_PROD_TYPE_IXP2000 |
107 IXP2000_MIN_PROD_TYPE_IXP2850)) &&
108 ((id & IXP2000_MAJ_REV_MASK) == 0)));
109}
110
111static inline unsigned int ixp2000_has_flash(void)
112{
113 return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
114}
115
116static inline unsigned int ixp2000_is_pcimaster(void)
117{
118 return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
119}
120
121void ixp2000_map_io(void);
122void ixp2000_uart_init(void);
123void ixp2000_init_irq(void);
124void ixp2000_init_time(unsigned long);
125unsigned long ixp2000_gettimeoffset(void);
126
127struct pci_sys_data;
128
129u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
130void ixp2000_pci_preinit(void);
131int ixp2000_pci_setup(int, struct pci_sys_data*);
132struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
133int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
134int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
135
136/*
137 * Several of the IXP2000 systems have banked flash so we need to extend the
138 * flash_platform_data structure with some private pointers
139 */
140struct ixp2000_flash_data {
141 struct flash_platform_data *platform_data;
142 int nr_banks;
143 unsigned long (*bank_setup)(unsigned long);
144};
145
146struct ixp2000_i2c_pins {
147 unsigned long sda_pin;
148 unsigned long scl_pin;
149};
150
151
152#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
new file mode 100644
index 00000000000..de370992c84
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/system.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/system.h
3 *
4 * Copyright (C) 2002 Intel Corp.
5 * Copyricht (C) 2003-2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <mach/hardware.h>
13#include <asm/mach-types.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode, const char *cmd)
21{
22 local_irq_disable();
23
24 /*
25 * Reset flash banking register so that we are pointing at
26 * RedBoot bank.
27 */
28 if (machine_is_ixdp2401()) {
29 ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
30 ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
31 | IXDP2X01_CPLD_FLASH_INTERN));
32 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
33 }
34
35 /*
36 * On IXDP2801 we need to write this magic sequence to the CPLD
37 * to cause a complete reset of the CPU and all external devices
38 * and move the flash bank register back to 0.
39 */
40 if (machine_is_ixdp2801() || machine_is_ixdp28x5()) {
41 unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
42
43 reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
44 ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
45 ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
46 }
47
48 ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
49}
diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h
new file mode 100644
index 00000000000..835e659f93d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/timex.h
@@ -0,0 +1,13 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/timex.h
3 *
4 * IXP2000 architecture timex specifications
5 */
6
7
8/*
9 * Default clock is 50MHz APB, but platform code can override this
10 */
11#define CLOCK_TICK_RATE 50000000
12
13
diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h
new file mode 100644
index 00000000000..ce363087df7
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/uncompress.h
3 *
4 *
5 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <linux/serial_reg.h>
18
19#define UART_BASE 0xc0030000
20
21#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x))
22
23#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */
24#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/
25#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/
26#define UARTIER PHYS(0x04) /* Interrupt enable reg */
27#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/
28#define UARTLCR PHYS(0x0c) /* Control reg */
29#define UARTSR PHYS(0x14) /* Status reg */
30
31
32static inline void putc(int c)
33{
34 int j = 0x1000;
35
36 while (--j && !(*UARTSR & UART_LSR_THRE))
37 barrier();
38
39 *UARTDR = c;
40}
41
42static inline void flush(void)
43{
44}
45
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
new file mode 100644
index 00000000000..61c8dae24f9
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/mach-ixp2000/include/mach/vmalloc.h
3 *
4 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 *
6 * Copyright 2002 Intel Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Just any arbitrary offset to the start of the vmalloc VM area: the
14 * current 8MB value just means that there will be a 8MB "hole" after the
15 * physical memory until the kernel virtual memory starts. That means that
16 * any out-of-bounds memory accesses will hopefully be caught.
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;)
19 */
20#define VMALLOC_END 0xfb000000UL
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
new file mode 100644
index 00000000000..5bad1a8419b
--- /dev/null
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2400.c
3 *
4 * IXDP2400 platform support
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/device.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <asm/system.h>
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35
36#include <asm/mach/pci.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39#include <asm/mach/time.h>
40#include <asm/mach/flash.h>
41#include <asm/mach/arch.h>
42
43/*************************************************************************
44 * IXDP2400 timer tick
45 *************************************************************************/
46static void __init ixdp2400_timer_init(void)
47{
48 int numerator, denominator;
49 int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8};
50
51 numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2;
52 denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)];
53
54 ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2);
55}
56
57static struct sys_timer ixdp2400_timer = {
58 .init = ixdp2400_timer_init,
59 .offset = ixp2000_gettimeoffset,
60};
61
62/*************************************************************************
63 * IXDP2400 PCI
64 *************************************************************************/
65void __init ixdp2400_pci_preinit(void)
66{
67 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
68 ixp2000_pci_preinit();
69 pcibios_setup("firmware");
70}
71
72int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys)
73{
74 sys->mem_offset = 0xe0000000;
75
76 ixp2000_pci_setup(nr, sys);
77
78 return 1;
79}
80
81static int __init ixdp2400_pci_map_irq(const struct pci_dev *dev, u8 slot,
82 u8 pin)
83{
84 if (ixdp2x00_master_npu()) {
85
86 /*
87 * Root bus devices. Slave NPU is only one with interrupt.
88 * Everything else, we just return -1 b/c nothing else
89 * on the root bus has interrupts.
90 */
91 if(!dev->bus->self) {
92 if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
93 return IRQ_IXDP2400_INGRESS_NPU;
94
95 return -1;
96 }
97
98 /*
99 * Bridge behind the PMC slot.
100 * NOTE: Only INTA from the PMC slot is routed. VERY BAD.
101 */
102 if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
103 dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
104 !dev->bus->parent->self->bus->parent)
105 return IRQ_IXDP2400_PMC;
106
107 /*
108 * Device behind the first bridge
109 */
110 if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
111 switch(dev->devfn) {
112 case IXDP2400_MASTER_ENET_DEVFN:
113 return IRQ_IXDP2400_ENET;
114
115 case IXDP2400_MEDIA_DEVFN:
116 return IRQ_IXDP2400_MEDIA_PCI;
117
118 case IXDP2400_SWITCH_FABRIC_DEVFN:
119 return IRQ_IXDP2400_SF_PCI;
120
121 case IXDP2X00_PMC_DEVFN:
122 return IRQ_IXDP2400_PMC;
123 }
124 }
125
126 return -1;
127 } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
128}
129
130
131static void ixdp2400_pci_postinit(void)
132{
133 struct pci_dev *dev;
134
135 if (ixdp2x00_master_npu()) {
136 dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN);
137 pci_remove_bus_device(dev);
138 pci_dev_put(dev);
139 } else {
140 dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN);
141 pci_remove_bus_device(dev);
142 pci_dev_put(dev);
143
144 ixdp2x00_slave_pci_postinit();
145 }
146}
147
148static struct hw_pci ixdp2400_pci __initdata = {
149 .nr_controllers = 1,
150 .setup = ixdp2400_pci_setup,
151 .preinit = ixdp2400_pci_preinit,
152 .postinit = ixdp2400_pci_postinit,
153 .scan = ixp2000_pci_scan_bus,
154 .map_irq = ixdp2400_pci_map_irq,
155};
156
157int __init ixdp2400_pci_init(void)
158{
159 if (machine_is_ixdp2400())
160 pci_common_init(&ixdp2400_pci);
161
162 return 0;
163}
164
165subsys_initcall(ixdp2400_pci_init);
166
167void __init ixdp2400_init_irq(void)
168{
169 ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS);
170}
171
172MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
173 /* Maintainer: MontaVista Software, Inc. */
174 .boot_params = 0x00000100,
175 .map_io = ixdp2x00_map_io,
176 .init_irq = ixdp2400_init_irq,
177 .timer = &ixdp2400_timer,
178 .init_machine = ixdp2x00_init_machine,
179MACHINE_END
180
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
new file mode 100644
index 00000000000..3d3cef87646
--- /dev/null
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -0,0 +1,295 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2800.c
3 *
4 * IXDP2800 platform support
5 *
6 * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/device.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <asm/system.h>
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35
36#include <asm/mach/pci.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39#include <asm/mach/time.h>
40#include <asm/mach/flash.h>
41#include <asm/mach/arch.h>
42
43/*************************************************************************
44 * IXDP2800 timer tick
45 *************************************************************************/
46
47static void __init ixdp2800_timer_init(void)
48{
49 ixp2000_init_time(50000000);
50}
51
52static struct sys_timer ixdp2800_timer = {
53 .init = ixdp2800_timer_init,
54 .offset = ixp2000_gettimeoffset,
55};
56
57/*************************************************************************
58 * IXDP2800 PCI
59 *************************************************************************/
60static void __init ixdp2800_slave_disable_pci_master(void)
61{
62 *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
63}
64
65static void __init ixdp2800_master_wait_for_slave(void)
66{
67 volatile u32 *addr;
68
69 printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
70 "its BAR sizes\n");
71
72 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
73 PCI_BASE_ADDRESS_1);
74 do {
75 *addr = 0xffffffff;
76 cpu_relax();
77 } while (*addr != 0xfe000008);
78
79 addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
80 PCI_BASE_ADDRESS_2);
81 do {
82 *addr = 0xffffffff;
83 cpu_relax();
84 } while (*addr != 0xc0000008);
85
86 /*
87 * Configure the slave's SDRAM BAR by hand.
88 */
89 *addr = 0x40000008;
90}
91
92static void __init ixdp2800_slave_wait_for_master_enable(void)
93{
94 printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
95
96 while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
97 cpu_relax();
98}
99
100void __init ixdp2800_pci_preinit(void)
101{
102 printk("ixdp2x00_pci_preinit called\n");
103
104 *IXP2000_PCI_ADDR_EXT = 0x0001e000;
105
106 if (!ixdp2x00_master_npu())
107 ixdp2800_slave_disable_pci_master();
108
109 *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
110 *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
111
112 ixp2000_pci_preinit();
113
114 if (ixdp2x00_master_npu()) {
115 /*
116 * Wait until the slave set its SRAM/SDRAM BAR sizes
117 * correctly before we proceed to scan and enumerate
118 * the bus.
119 */
120 ixdp2800_master_wait_for_slave();
121
122 /*
123 * We configure the SDRAM BARs by hand because they
124 * are 1G and fall outside of the regular allocated
125 * PCI address space.
126 */
127 *IXP2000_PCI_SDRAM_BAR = 0x00000008;
128 } else {
129 /*
130 * Wait for the master to complete scanning the bus
131 * and assigning resources before we proceed to scan
132 * the bus ourselves. Set pci=firmware to honor the
133 * master's resource assignment.
134 */
135 ixdp2800_slave_wait_for_master_enable();
136 pcibios_setup("firmware");
137 }
138}
139
140/*
141 * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
142 * of the regular PCI window, because there's only 512M of outbound PCI
143 * memory window on each IXP, while we need 1G for each of the BARs.
144 */
145static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
146{
147 if (machine_is_ixdp2800()) {
148 dev->resource[2].start = 0;
149 dev->resource[2].end = 0;
150 dev->resource[2].flags = 0;
151 }
152}
153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
154
155static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
156{
157 sys->mem_offset = 0x00000000;
158
159 ixp2000_pci_setup(nr, sys);
160
161 return 1;
162}
163
164static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot,
165 u8 pin)
166{
167 if (ixdp2x00_master_npu()) {
168
169 /*
170 * Root bus devices. Slave NPU is only one with interrupt.
171 * Everything else, we just return -1 which is invalid.
172 */
173 if(!dev->bus->self) {
174 if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
175 return IRQ_IXDP2800_INGRESS_NPU;
176
177 return -1;
178 }
179
180 /*
181 * Bridge behind the PMC slot.
182 */
183 if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
184 dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
185 !dev->bus->parent->self->bus->parent)
186 return IRQ_IXDP2800_PMC;
187
188 /*
189 * Device behind the first bridge
190 */
191 if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
192 switch(dev->devfn) {
193 case IXDP2X00_PMC_DEVFN:
194 return IRQ_IXDP2800_PMC;
195
196 case IXDP2800_MASTER_ENET_DEVFN:
197 return IRQ_IXDP2800_EGRESS_ENET;
198
199 case IXDP2800_SWITCH_FABRIC_DEVFN:
200 return IRQ_IXDP2800_FABRIC;
201 }
202 }
203
204 return -1;
205 } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
206}
207
208static void __init ixdp2800_master_enable_slave(void)
209{
210 volatile u32 *addr;
211
212 printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
213
214 addr = (volatile u32 *)ixp2000_pci_config_addr(0,
215 IXDP2X00_SLAVE_NPU_DEVFN,
216 PCI_COMMAND);
217
218 *addr |= PCI_COMMAND_MASTER;
219}
220
221static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
222{
223 volatile u32 *addr;
224
225 printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
226
227 addr = (volatile u32 *)ixp2000_pci_config_addr(0,
228 IXDP2X00_SLAVE_NPU_DEVFN,
229 PCI_COMMAND);
230 while ((*addr & PCI_COMMAND_MEMORY) == 0)
231 cpu_relax();
232}
233
234static void __init ixdp2800_slave_signal_bus_scan_completion(void)
235{
236 printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
237 *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
238}
239
240static void __init ixdp2800_pci_postinit(void)
241{
242 if (!ixdp2x00_master_npu()) {
243 ixdp2x00_slave_pci_postinit();
244 ixdp2800_slave_signal_bus_scan_completion();
245 }
246}
247
248struct __initdata hw_pci ixdp2800_pci __initdata = {
249 .nr_controllers = 1,
250 .setup = ixdp2800_pci_setup,
251 .preinit = ixdp2800_pci_preinit,
252 .postinit = ixdp2800_pci_postinit,
253 .scan = ixp2000_pci_scan_bus,
254 .map_irq = ixdp2800_pci_map_irq,
255};
256
257int __init ixdp2800_pci_init(void)
258{
259 if (machine_is_ixdp2800()) {
260 struct pci_dev *dev;
261
262 pci_common_init(&ixdp2800_pci);
263 if (ixdp2x00_master_npu()) {
264 dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
265 pci_remove_bus_device(dev);
266 pci_dev_put(dev);
267
268 ixdp2800_master_enable_slave();
269 ixdp2800_master_wait_for_slave_bus_scan();
270 } else {
271 dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
272 pci_remove_bus_device(dev);
273 pci_dev_put(dev);
274 }
275 }
276
277 return 0;
278}
279
280subsys_initcall(ixdp2800_pci_init);
281
282void __init ixdp2800_init_irq(void)
283{
284 ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
285}
286
287MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
288 /* Maintainer: MontaVista Software, Inc. */
289 .boot_params = 0x00000100,
290 .map_io = ixdp2x00_map_io,
291 .init_irq = ixdp2800_init_irq,
292 .timer = &ixdp2800_timer,
293 .init_machine = ixdp2x00_init_machine,
294MACHINE_END
295
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
new file mode 100644
index 00000000000..235638f800e
--- /dev/null
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -0,0 +1,307 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2x00.c
3 *
4 * Code common to IXDP2400 and IXDP2800 platforms.
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/irq.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <asm/system.h>
33#include <mach/hardware.h>
34#include <asm/mach-types.h>
35
36#include <asm/mach/pci.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39#include <asm/mach/time.h>
40#include <asm/mach/flash.h>
41#include <asm/mach/arch.h>
42
43#include <mach/gpio.h>
44
45
46/*************************************************************************
47 * IXDP2x00 IRQ Initialization
48 *************************************************************************/
49static volatile unsigned long *board_irq_mask;
50static volatile unsigned long *board_irq_stat;
51static unsigned long board_irq_count;
52
53#ifdef CONFIG_ARCH_IXDP2400
54/*
55 * Slowport configuration for accessing CPLD registers on IXDP2x00
56 */
57static struct slowport_cfg slowport_cpld_cfg = {
58 .CCR = SLOWPORT_CCR_DIV_2,
59 .WTC = 0x00000070,
60 .RTC = 0x00000070,
61 .PCR = SLOWPORT_MODE_FLASH,
62 .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8
63};
64#endif
65
66static void ixdp2x00_irq_mask(struct irq_data *d)
67{
68 unsigned long dummy;
69 static struct slowport_cfg old_cfg;
70
71 /*
72 * This is ugly in common code but really don't know
73 * of a better way to handle it. :(
74 */
75#ifdef CONFIG_ARCH_IXDP2400
76 if (machine_is_ixdp2400())
77 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
78#endif
79
80 dummy = *board_irq_mask;
81 dummy |= IXP2000_BOARD_IRQ_MASK(d->irq);
82 ixp2000_reg_wrb(board_irq_mask, dummy);
83
84#ifdef CONFIG_ARCH_IXDP2400
85 if (machine_is_ixdp2400())
86 ixp2000_release_slowport(&old_cfg);
87#endif
88}
89
90static void ixdp2x00_irq_unmask(struct irq_data *d)
91{
92 unsigned long dummy;
93 static struct slowport_cfg old_cfg;
94
95#ifdef CONFIG_ARCH_IXDP2400
96 if (machine_is_ixdp2400())
97 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
98#endif
99
100 dummy = *board_irq_mask;
101 dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq);
102 ixp2000_reg_wrb(board_irq_mask, dummy);
103
104 if (machine_is_ixdp2400())
105 ixp2000_release_slowport(&old_cfg);
106}
107
108static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
109{
110 volatile u32 ex_interrupt = 0;
111 static struct slowport_cfg old_cfg;
112 int i;
113
114 desc->irq_data.chip->irq_mask(&desc->irq_data);
115
116#ifdef CONFIG_ARCH_IXDP2400
117 if (machine_is_ixdp2400())
118 ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
119#endif
120 ex_interrupt = *board_irq_stat & 0xff;
121 if (machine_is_ixdp2400())
122 ixp2000_release_slowport(&old_cfg);
123
124 if(!ex_interrupt) {
125 printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n");
126 return;
127 }
128
129 for(i = 0; i < board_irq_count; i++) {
130 if(ex_interrupt & (1 << i)) {
131 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
132 generic_handle_irq(cpld_irq);
133 }
134 }
135
136 desc->irq_data.chip->irq_unmask(&desc->irq_data);
137}
138
139static struct irq_chip ixdp2x00_cpld_irq_chip = {
140 .irq_ack = ixdp2x00_irq_mask,
141 .irq_mask = ixdp2x00_irq_mask,
142 .irq_unmask = ixdp2x00_irq_unmask
143};
144
145void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
146{
147 unsigned int irq;
148
149 ixp2000_init_irq();
150
151 if (!ixdp2x00_master_npu())
152 return;
153
154 board_irq_stat = stat_reg;
155 board_irq_mask = mask_reg;
156 board_irq_count = nr_of_irqs;
157
158 *board_irq_mask = 0xffffffff;
159
160 for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
161 irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
162 handle_level_irq);
163 set_irq_flags(irq, IRQF_VALID);
164 }
165
166 /* Hook into PCI interrupt */
167 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
168}
169
170/*************************************************************************
171 * IXDP2x00 memory map
172 *************************************************************************/
173static struct map_desc ixdp2x00_io_desc __initdata = {
174 .virtual = IXDP2X00_VIRT_CPLD_BASE,
175 .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE),
176 .length = IXDP2X00_CPLD_SIZE,
177 .type = MT_DEVICE
178};
179
180void __init ixdp2x00_map_io(void)
181{
182 ixp2000_map_io();
183
184 iotable_init(&ixdp2x00_io_desc, 1);
185}
186
187/*************************************************************************
188 * IXDP2x00-common PCI init
189 *
190 * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board
191 * contains two NPUs (ingress and egress) connected over PCI, both running
192 * instances of the kernel. So far so good. Peers on the PCI bus running
193 * Linux is a common design in telecom systems. The problem is that instead
194 * of all the devices being controlled by a single host, different
195 * devices are controlled by different NPUs on the same bus, leading to
196 * multiple hosts on the bus. The exact bus layout looks like:
197 *
198 * Bus 0
199 * Master NPU <-------------------+-------------------> Slave NPU
200 * |
201 * |
202 * P2P
203 * |
204 *
205 * Bus 1 |
206 * <--+------+---------+---------+------+-->
207 * | | | | |
208 * | | | | |
209 * ... Dev PMC Media Eth0 Eth1 ...
210 *
211 * The master controls all but Eth1, which is controlled by the
212 * slave. What this means is that the both the master and the slave
213 * have to scan the bus, but only one of them can enumerate the bus.
214 * In addition, after the bus is scanned, each kernel must remove
215 * the device(s) it does not control from the PCI dev list otherwise
216 * a driver on each NPU will try to manage it and we will have horrible
217 * conflicts. Oh..and the slave NPU needs to see the master NPU
218 * for Intel's drivers to work properly. Closed source drivers...
219 *
220 * The way we deal with this is fairly simple but ugly:
221 *
222 * 1) Let master scan and enumerate the bus completely.
223 * 2) Master deletes Eth1 from device list.
224 * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave)
225 * from device list.
226 * 4) Find HW designers and LART them.
227 *
228 * The boards also do not do normal PCI IRQ routing, or any sort of
229 * sensical swizzling, so we just need to check where on the bus a
230 * device sits and figure out to which CPLD pin the interrupt is routed.
231 * See ixdp2[48]00.c files.
232 *
233 *************************************************************************/
234void ixdp2x00_slave_pci_postinit(void)
235{
236 struct pci_dev *dev;
237
238 /*
239 * Remove PMC device is there is one
240 */
241 if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
242 pci_remove_bus_device(dev);
243 pci_dev_put(dev);
244 }
245
246 dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
247 pci_remove_bus_device(dev);
248 pci_dev_put(dev);
249}
250
251/**************************************************************************
252 * IXDP2x00 Machine Setup
253 *************************************************************************/
254static struct flash_platform_data ixdp2x00_platform_data = {
255 .map_name = "cfi_probe",
256 .width = 1,
257};
258
259static struct ixp2000_flash_data ixdp2x00_flash_data = {
260 .platform_data = &ixdp2x00_platform_data,
261 .nr_banks = 1
262};
263
264static struct resource ixdp2x00_flash_resource = {
265 .start = 0xc4000000,
266 .end = 0xc4000000 + 0x00ffffff,
267 .flags = IORESOURCE_MEM,
268};
269
270static struct platform_device ixdp2x00_flash = {
271 .name = "IXP2000-Flash",
272 .id = 0,
273 .dev = {
274 .platform_data = &ixdp2x00_flash_data,
275 },
276 .num_resources = 1,
277 .resource = &ixdp2x00_flash_resource,
278};
279
280static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = {
281 .sda_pin = IXDP2X00_GPIO_SDA,
282 .scl_pin = IXDP2X00_GPIO_SCL,
283};
284
285static struct platform_device ixdp2x00_i2c_controller = {
286 .name = "IXP2000-I2C",
287 .id = 0,
288 .dev = {
289 .platform_data = &ixdp2x00_i2c_gpio_pins,
290 },
291 .num_resources = 0
292};
293
294static struct platform_device *ixdp2x00_devices[] __initdata = {
295 &ixdp2x00_flash,
296 &ixdp2x00_i2c_controller
297};
298
299void __init ixdp2x00_init_machine(void)
300{
301 gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1);
302 gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
303
304 platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));
305 ixp2000_uart_init();
306}
307
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
new file mode 100644
index 00000000000..be2a254f137
--- /dev/null
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -0,0 +1,452 @@
1/*
2 * arch/arm/mach-ixp2000/ixdp2x01.c
3 *
4 * Code common to Intel IXDP2401 and IXDP2801 platforms
5 *
6 * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
7 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright (C) 2002-2003 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/bitops.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/serial.h>
28#include <linux/tty.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/serial_8250.h>
32#include <linux/io.h>
33
34#include <asm/irq.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/system.h>
38#include <mach/hardware.h>
39#include <asm/mach-types.h>
40
41#include <asm/mach/pci.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/time.h>
45#include <asm/mach/arch.h>
46#include <asm/mach/flash.h>
47
48/*************************************************************************
49 * IXDP2x01 IRQ Handling
50 *************************************************************************/
51static void ixdp2x01_irq_mask(struct irq_data *d)
52{
53 ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
54 IXP2000_BOARD_IRQ_MASK(d->irq));
55}
56
57static void ixdp2x01_irq_unmask(struct irq_data *d)
58{
59 ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
60 IXP2000_BOARD_IRQ_MASK(d->irq));
61}
62
63static u32 valid_irq_mask;
64
65static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
66{
67 u32 ex_interrupt;
68 int i;
69
70 desc->irq_data.chip->irq_mask(&desc->irq_data);
71
72 ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
73
74 if (!ex_interrupt) {
75 printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
76 return;
77 }
78
79 for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
80 if (ex_interrupt & (1 << i)) {
81 int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
82 generic_handle_irq(cpld_irq);
83 }
84 }
85
86 desc->irq_data.chip->irq_unmask(&desc->irq_data);
87}
88
89static struct irq_chip ixdp2x01_irq_chip = {
90 .irq_mask = ixdp2x01_irq_mask,
91 .irq_ack = ixdp2x01_irq_mask,
92 .irq_unmask = ixdp2x01_irq_unmask
93};
94
95/*
96 * We only do anything if we are the master NPU on the board.
97 * The slave NPU only has the ethernet chip going directly to
98 * the PCIB interrupt input.
99 */
100void __init ixdp2x01_init_irq(void)
101{
102 int irq = 0;
103
104 /* initialize chip specific interrupts */
105 ixp2000_init_irq();
106
107 if (machine_is_ixdp2401())
108 valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
109 else
110 valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
111
112 /* Mask all interrupts from CPLD, disable simulation */
113 ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
114 ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
115
116 for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
117 if (irq & valid_irq_mask) {
118 irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
119 handle_level_irq);
120 set_irq_flags(irq, IRQF_VALID);
121 } else {
122 set_irq_flags(irq, 0);
123 }
124 }
125
126 /* Hook into PCI interrupts */
127 irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
128}
129
130
131/*************************************************************************
132 * IXDP2x01 memory map
133 *************************************************************************/
134static struct map_desc ixdp2x01_io_desc __initdata = {
135 .virtual = IXDP2X01_VIRT_CPLD_BASE,
136 .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
137 .length = IXDP2X01_CPLD_REGION_SIZE,
138 .type = MT_DEVICE
139};
140
141static void __init ixdp2x01_map_io(void)
142{
143 ixp2000_map_io();
144 iotable_init(&ixdp2x01_io_desc, 1);
145}
146
147
148/*************************************************************************
149 * IXDP2x01 serial ports
150 *************************************************************************/
151static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
152 {
153 .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
154 .membase = (char *)IXDP2X01_UART1_VIRT_BASE,
155 .irq = IRQ_IXDP2X01_UART1,
156 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
157 .iotype = UPIO_MEM32,
158 .regshift = 2,
159 .uartclk = IXDP2X01_UART_CLK,
160 },
161 { }
162};
163
164static struct resource ixdp2x01_uart_resource1 = {
165 .start = IXDP2X01_UART1_PHYS_BASE,
166 .end = IXDP2X01_UART1_PHYS_BASE + 0xffff,
167 .flags = IORESOURCE_MEM,
168};
169
170static struct platform_device ixdp2x01_serial_device1 = {
171 .name = "serial8250",
172 .id = PLAT8250_DEV_PLATFORM1,
173 .dev = {
174 .platform_data = ixdp2x01_serial_port1,
175 },
176 .num_resources = 1,
177 .resource = &ixdp2x01_uart_resource1,
178};
179
180static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
181 {
182 .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
183 .membase = (char *)IXDP2X01_UART2_VIRT_BASE,
184 .irq = IRQ_IXDP2X01_UART2,
185 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
186 .iotype = UPIO_MEM32,
187 .regshift = 2,
188 .uartclk = IXDP2X01_UART_CLK,
189 },
190 { }
191};
192
193static struct resource ixdp2x01_uart_resource2 = {
194 .start = IXDP2X01_UART2_PHYS_BASE,
195 .end = IXDP2X01_UART2_PHYS_BASE + 0xffff,
196 .flags = IORESOURCE_MEM,
197};
198
199static struct platform_device ixdp2x01_serial_device2 = {
200 .name = "serial8250",
201 .id = PLAT8250_DEV_PLATFORM2,
202 .dev = {
203 .platform_data = ixdp2x01_serial_port2,
204 },
205 .num_resources = 1,
206 .resource = &ixdp2x01_uart_resource2,
207};
208
209static void ixdp2x01_uart_init(void)
210{
211 platform_device_register(&ixdp2x01_serial_device1);
212 platform_device_register(&ixdp2x01_serial_device2);
213}
214
215
216/*************************************************************************
217 * IXDP2x01 timer tick configuration
218 *************************************************************************/
219static unsigned int ixdp2x01_clock;
220
221static int __init ixdp2x01_clock_setup(char *str)
222{
223 ixdp2x01_clock = simple_strtoul(str, NULL, 10);
224
225 return 1;
226}
227
228__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
229
230static void __init ixdp2x01_timer_init(void)
231{
232 if (!ixdp2x01_clock)
233 ixdp2x01_clock = 50000000;
234
235 ixp2000_init_time(ixdp2x01_clock);
236}
237
238static struct sys_timer ixdp2x01_timer = {
239 .init = ixdp2x01_timer_init,
240 .offset = ixp2000_gettimeoffset,
241};
242
243/*************************************************************************
244 * IXDP2x01 PCI
245 *************************************************************************/
246void __init ixdp2x01_pci_preinit(void)
247{
248 ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
249 ixp2000_pci_preinit();
250 pcibios_setup("firmware");
251}
252
253#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
254
255static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
256 u8 pin)
257{
258 u8 bus = dev->bus->number;
259 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
260 struct pci_bus *tmp_bus = dev->bus;
261
262 /* Primary bus, no interrupts here */
263 if (bus == 0) {
264 return -1;
265 }
266
267 /* Lookup first leaf in bus tree */
268 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
269 tmp_bus = tmp_bus->parent;
270 }
271
272 /* Select between known bridges */
273 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
274 /* Device is located after first MB bridge */
275 case 0x0008:
276 if (tmp_bus == dev->bus) {
277 /* Device is located directly after first MB bridge */
278 switch (devpin) {
279 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
280 if (machine_is_ixdp2401())
281 return IRQ_IXDP2401_INTA_82546;
282 return -1;
283 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
284 if (machine_is_ixdp2401())
285 return IRQ_IXDP2401_INTB_82546;
286 return -1;
287 case DEVPIN(0, 1): /* PMC INTA# */
288 return IRQ_IXDP2X01_SPCI_PMC_INTA;
289 case DEVPIN(0, 2): /* PMC INTB# */
290 return IRQ_IXDP2X01_SPCI_PMC_INTB;
291 case DEVPIN(0, 3): /* PMC INTC# */
292 return IRQ_IXDP2X01_SPCI_PMC_INTC;
293 case DEVPIN(0, 4): /* PMC INTD# */
294 return IRQ_IXDP2X01_SPCI_PMC_INTD;
295 }
296 }
297 break;
298 case 0x0010:
299 if (tmp_bus == dev->bus) {
300 /* Device is located directly after second MB bridge */
301 /* Secondary bus of second bridge */
302 switch (devpin) {
303 case DEVPIN(0, 1): /* DB#0 */
304 return IRQ_IXDP2X01_SPCI_DB_0;
305 case DEVPIN(1, 1): /* DB#1 */
306 return IRQ_IXDP2X01_SPCI_DB_1;
307 }
308 } else {
309 /* Device is located indirectly after second MB bridge */
310 /* Not supported now */
311 }
312 break;
313 }
314
315 return -1;
316}
317
318
319static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
320{
321 sys->mem_offset = 0xe0000000;
322
323 if (machine_is_ixdp2801() || machine_is_ixdp28x5())
324 sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
325
326 return ixp2000_pci_setup(nr, sys);
327}
328
329struct hw_pci ixdp2x01_pci __initdata = {
330 .nr_controllers = 1,
331 .setup = ixdp2x01_pci_setup,
332 .preinit = ixdp2x01_pci_preinit,
333 .scan = ixp2000_pci_scan_bus,
334 .map_irq = ixdp2x01_pci_map_irq,
335};
336
337int __init ixdp2x01_pci_init(void)
338{
339 if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
340 machine_is_ixdp28x5())
341 pci_common_init(&ixdp2x01_pci);
342
343 return 0;
344}
345
346subsys_initcall(ixdp2x01_pci_init);
347
348/*************************************************************************
349 * IXDP2x01 Machine Initialization
350 *************************************************************************/
351static struct flash_platform_data ixdp2x01_flash_platform_data = {
352 .map_name = "cfi_probe",
353 .width = 1,
354};
355
356static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
357{
358 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
359 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
360 return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
361}
362
363static struct ixp2000_flash_data ixdp2x01_flash_data = {
364 .platform_data = &ixdp2x01_flash_platform_data,
365 .bank_setup = ixdp2x01_flash_bank_setup
366};
367
368static struct resource ixdp2x01_flash_resource = {
369 .start = 0xc4000000,
370 .end = 0xc4000000 + 0x01ffffff,
371 .flags = IORESOURCE_MEM,
372};
373
374static struct platform_device ixdp2x01_flash = {
375 .name = "IXP2000-Flash",
376 .id = 0,
377 .dev = {
378 .platform_data = &ixdp2x01_flash_data,
379 },
380 .num_resources = 1,
381 .resource = &ixdp2x01_flash_resource,
382};
383
384static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
385 .sda_pin = IXDP2X01_GPIO_SDA,
386 .scl_pin = IXDP2X01_GPIO_SCL,
387};
388
389static struct platform_device ixdp2x01_i2c_controller = {
390 .name = "IXP2000-I2C",
391 .id = 0,
392 .dev = {
393 .platform_data = &ixdp2x01_i2c_gpio_pins,
394 },
395 .num_resources = 0
396};
397
398static struct platform_device *ixdp2x01_devices[] __initdata = {
399 &ixdp2x01_flash,
400 &ixdp2x01_i2c_controller
401};
402
403static void __init ixdp2x01_init_machine(void)
404{
405 ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
406 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
407
408 ixdp2x01_flash_data.nr_banks =
409 ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
410
411 platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
412 ixp2000_uart_init();
413 ixdp2x01_uart_init();
414}
415
416
417#ifdef CONFIG_ARCH_IXDP2401
418MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
419 /* Maintainer: MontaVista Software, Inc. */
420 .boot_params = 0x00000100,
421 .map_io = ixdp2x01_map_io,
422 .init_irq = ixdp2x01_init_irq,
423 .timer = &ixdp2x01_timer,
424 .init_machine = ixdp2x01_init_machine,
425MACHINE_END
426#endif
427
428#ifdef CONFIG_ARCH_IXDP2801
429MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
430 /* Maintainer: MontaVista Software, Inc. */
431 .boot_params = 0x00000100,
432 .map_io = ixdp2x01_map_io,
433 .init_irq = ixdp2x01_init_irq,
434 .timer = &ixdp2x01_timer,
435 .init_machine = ixdp2x01_init_machine,
436MACHINE_END
437
438/*
439 * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
440 * changed the machine ID in the bootloader
441 */
442MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
443 /* Maintainer: MontaVista Software, Inc. */
444 .boot_params = 0x00000100,
445 .map_io = ixdp2x01_map_io,
446 .init_irq = ixdp2x01_init_irq,
447 .timer = &ixdp2x01_timer,
448 .init_machine = ixdp2x01_init_machine,
449MACHINE_END
450#endif
451
452
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
new file mode 100644
index 00000000000..f5098b306fd
--- /dev/null
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -0,0 +1,251 @@
1/*
2 * arch/arm/mach-ixp2000/pci.c
3 *
4 * PCI routines for IXDP2400/IXDP2800 boards
5 *
6 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 * Maintained by: Deepak Saxena <dsaxena@plexity.net>
8 *
9 * Copyright 2002 Intel Corp.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/interrupt.h>
22#include <linux/mm.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27
28#include <asm/irq.h>
29#include <asm/system.h>
30#include <mach/hardware.h>
31
32#include <asm/mach/pci.h>
33
34static volatile int pci_master_aborts = 0;
35
36static int clear_master_aborts(void);
37
38u32 *
39ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
40{
41 u32 *paddress;
42
43 if (PCI_SLOT(devfn) > 7)
44 return 0;
45
46 /* Must be dword aligned */
47 where &= ~3;
48
49 /*
50 * For top bus, generate type 0, else type 1
51 */
52 if (!bus_nr) {
53 /* only bits[23:16] are used for IDSEL */
54 paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE
55 | (1 << (PCI_SLOT(devfn) + 16))
56 | (PCI_FUNC(devfn) << 8) | where);
57 } else {
58 paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE
59 | (bus_nr << 16)
60 | (PCI_SLOT(devfn) << 11)
61 | (PCI_FUNC(devfn) << 8) | where);
62 }
63
64 return paddress;
65}
66
67/*
68 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
69 * 0 and 3 are not valid indexes...
70 */
71static u32 bytemask[] = {
72 /*0*/ 0,
73 /*1*/ 0xff,
74 /*2*/ 0xffff,
75 /*3*/ 0,
76 /*4*/ 0xffffffff,
77};
78
79
80int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
81 int size, u32 *value)
82{
83 u32 n;
84 u32 *addr;
85
86 n = where % 4;
87
88 addr = ixp2000_pci_config_addr(bus->number, devfn, where);
89 if (!addr)
90 return PCIBIOS_DEVICE_NOT_FOUND;
91
92 pci_master_aborts = 0;
93 *value = (*addr >> (8*n)) & bytemask[size];
94 if (pci_master_aborts) {
95 pci_master_aborts = 0;
96 *value = 0xffffffff;
97 return PCIBIOS_DEVICE_NOT_FOUND;
98 }
99
100 return PCIBIOS_SUCCESSFUL;
101}
102
103/*
104 * We don't do error checks by calling clear_master_aborts() b/c the
105 * assumption is that the caller did a read first to make sure a device
106 * exists.
107 */
108int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
109 int size, u32 value)
110{
111 u32 mask;
112 u32 *addr;
113 u32 temp;
114
115 mask = ~(bytemask[size] << ((where % 0x4) * 8));
116 addr = ixp2000_pci_config_addr(bus->number, devfn, where);
117 if (!addr)
118 return PCIBIOS_DEVICE_NOT_FOUND;
119 temp = (u32) (value) << ((where % 0x4) * 8);
120 *addr = (*addr & mask) | temp;
121
122 clear_master_aborts();
123
124 return PCIBIOS_SUCCESSFUL;
125}
126
127
128static struct pci_ops ixp2000_pci_ops = {
129 .read = ixp2000_pci_read_config,
130 .write = ixp2000_pci_write_config
131};
132
133struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
134{
135 return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata);
136}
137
138
139int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
140{
141
142 volatile u32 temp;
143 unsigned long flags;
144
145 pci_master_aborts = 1;
146
147 local_irq_save(flags);
148 temp = *(IXP2000_PCI_CONTROL);
149 if (temp & ((1 << 8) | (1 << 5))) {
150 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
151 }
152
153 temp = *(IXP2000_PCI_CMDSTAT);
154 if (temp & (1 << 29)) {
155 while (temp & (1 << 29)) {
156 ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
157 temp = *(IXP2000_PCI_CMDSTAT);
158 }
159 }
160 local_irq_restore(flags);
161
162 /*
163 * If it was an imprecise abort, then we need to correct the
164 * return address to be _after_ the instruction.
165 */
166 if (fsr & (1 << 10))
167 regs->ARM_pc += 4;
168
169 return 0;
170}
171
172int
173clear_master_aborts(void)
174{
175 volatile u32 temp;
176 unsigned long flags;
177
178 local_irq_save(flags);
179 temp = *(IXP2000_PCI_CONTROL);
180 if (temp & ((1 << 8) | (1 << 5))) {
181 ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
182 }
183
184 temp = *(IXP2000_PCI_CMDSTAT);
185 if (temp & (1 << 29)) {
186 while (temp & (1 << 29)) {
187 ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
188 temp = *(IXP2000_PCI_CMDSTAT);
189 }
190 }
191 local_irq_restore(flags);
192
193 return 0;
194}
195
196void __init
197ixp2000_pci_preinit(void)
198{
199 pci_set_flags(0);
200
201 pcibios_min_io = 0;
202 pcibios_min_mem = 0;
203
204#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
205 /*
206 * Configure the PCI unit to properly byteswap I/O transactions,
207 * and verify that it worked.
208 */
209 ixp2000_reg_write(IXP2000_PCI_CONTROL,
210 (*IXP2000_PCI_CONTROL | PCI_CONTROL_IEE));
211
212 if ((*IXP2000_PCI_CONTROL & PCI_CONTROL_IEE) == 0)
213 panic("IXP2000: PCI I/O is broken on this ixp model, and "
214 "the needed workaround has not been configured in");
215#endif
216
217 hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
218 "PCI config cycle to non-existent device");
219}
220
221
222/*
223 * IXP2000 systems often have large resource requirements, so we just
224 * use our own resource space.
225 */
226static struct resource ixp2000_pci_mem_space = {
227 .start = 0xe0000000,
228 .end = 0xffffffff,
229 .flags = IORESOURCE_MEM,
230 .name = "PCI Mem Space"
231};
232
233static struct resource ixp2000_pci_io_space = {
234 .start = 0x00010000,
235 .end = 0x0001ffff,
236 .flags = IORESOURCE_IO,
237 .name = "PCI I/O Space"
238};
239
240int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
241{
242 if (nr >= 1)
243 return 0;
244
245 sys->resource[0] = &ixp2000_pci_io_space;
246 sys->resource[1] = &ixp2000_pci_mem_space;
247 sys->resource[2] = NULL;
248
249 return 1;
250}
251
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 11:18:35 -0400