diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-17 11:20:56 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-05-02 04:35:36 -0400 |
commit | 6be4826e37122b25cb10b215fc84c3a0b1fe1402 (patch) | |
tree | 4aad2c701f4b516e3bb75d23c11e0f4380d760cb /arch/arm/mach-integrator/core.c | |
parent | 5a46334ac688fb538b335599e1ff3b6cfaf769e9 (diff) |
ARM: Integrator: move 16-bit timer support to Integrator/AP
Only Integrator/AP has 16-bit timers, so move the support into the
Integrator/AP specific support files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-integrator/core.c')
-rw-r--r-- | arch/arm/mach-integrator/core.c | 157 |
1 files changed, 0 insertions, 157 deletions
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index ac2b0c5c991..b02cfc06e0a 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
@@ -19,8 +19,6 @@ | |||
19 | #include <linux/termios.h> | 19 | #include <linux/termios.h> |
20 | #include <linux/amba/bus.h> | 20 | #include <linux/amba/bus.h> |
21 | #include <linux/amba/serial.h> | 21 | #include <linux/amba/serial.h> |
22 | #include <linux/clocksource.h> | ||
23 | #include <linux/clockchips.h> | ||
24 | #include <linux/io.h> | 22 | #include <linux/io.h> |
25 | 23 | ||
26 | #include <asm/clkdev.h> | 24 | #include <asm/clkdev.h> |
@@ -28,14 +26,11 @@ | |||
28 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
29 | #include <mach/platform.h> | 27 | #include <mach/platform.h> |
30 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
31 | #include <asm/hardware/arm_timer.h> | ||
32 | #include <mach/cm.h> | 29 | #include <mach/cm.h> |
33 | #include <asm/system.h> | 30 | #include <asm/system.h> |
34 | #include <asm/leds.h> | 31 | #include <asm/leds.h> |
35 | #include <asm/mach/time.h> | 32 | #include <asm/mach/time.h> |
36 | 33 | ||
37 | #include "common.h" | ||
38 | |||
39 | static struct amba_pl010_data integrator_uart_data; | 34 | static struct amba_pl010_data integrator_uart_data; |
40 | 35 | ||
41 | static struct amba_device rtc_device = { | 36 | static struct amba_device rtc_device = { |
@@ -220,155 +215,3 @@ void cm_control(u32 mask, u32 set) | |||
220 | } | 215 | } |
221 | 216 | ||
222 | EXPORT_SYMBOL(cm_control); | 217 | EXPORT_SYMBOL(cm_control); |
223 | |||
224 | /* | ||
225 | * Where is the timer (VA)? | ||
226 | */ | ||
227 | #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) | ||
228 | #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) | ||
229 | #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) | ||
230 | |||
231 | /* | ||
232 | * How long is the timer interval? | ||
233 | */ | ||
234 | #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) | ||
235 | #if TIMER_INTERVAL >= 0x100000 | ||
236 | #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) | ||
237 | #elif TIMER_INTERVAL >= 0x10000 | ||
238 | #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) | ||
239 | #else | ||
240 | #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) | ||
241 | #endif | ||
242 | |||
243 | static unsigned long timer_reload; | ||
244 | |||
245 | static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE; | ||
246 | |||
247 | static cycle_t timersp_read(struct clocksource *cs) | ||
248 | { | ||
249 | return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff); | ||
250 | } | ||
251 | |||
252 | static struct clocksource clocksource_timersp = { | ||
253 | .name = "timer2", | ||
254 | .rating = 200, | ||
255 | .read = timersp_read, | ||
256 | .mask = CLOCKSOURCE_MASK(16), | ||
257 | .shift = 16, | ||
258 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
259 | }; | ||
260 | |||
261 | static void integrator_clocksource_init(u32 khz) | ||
262 | { | ||
263 | struct clocksource *cs = &clocksource_timersp; | ||
264 | void __iomem *base = clksrc_base; | ||
265 | u32 ctrl = TIMER_CTRL_ENABLE; | ||
266 | |||
267 | if (khz >= 1500) { | ||
268 | khz /= 16; | ||
269 | ctrl = TIMER_CTRL_DIV16; | ||
270 | } | ||
271 | |||
272 | writel(ctrl, base + TIMER_CTRL); | ||
273 | writel(0xffff, base + TIMER_LOAD); | ||
274 | |||
275 | cs->mult = clocksource_khz2mult(khz, cs->shift); | ||
276 | clocksource_register(cs); | ||
277 | } | ||
278 | |||
279 | static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; | ||
280 | |||
281 | /* | ||
282 | * IRQ handler for the timer | ||
283 | */ | ||
284 | static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id) | ||
285 | { | ||
286 | struct clock_event_device *evt = dev_id; | ||
287 | |||
288 | /* clear the interrupt */ | ||
289 | writel(1, clkevt_base + TIMER_INTCLR); | ||
290 | |||
291 | evt->event_handler(evt); | ||
292 | |||
293 | return IRQ_HANDLED; | ||
294 | } | ||
295 | |||
296 | static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) | ||
297 | { | ||
298 | u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; | ||
299 | |||
300 | BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT); | ||
301 | |||
302 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | ||
303 | writel(ctrl, clkevt_base + TIMER_CTRL); | ||
304 | writel(timer_reload, clkevt_base + TIMER_LOAD); | ||
305 | ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; | ||
306 | } | ||
307 | |||
308 | writel(ctrl, clkevt_base + TIMER_CTRL); | ||
309 | } | ||
310 | |||
311 | static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt) | ||
312 | { | ||
313 | unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); | ||
314 | |||
315 | writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | ||
316 | writel(next, clkevt_base + TIMER_LOAD); | ||
317 | writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); | ||
318 | |||
319 | return 0; | ||
320 | } | ||
321 | |||
322 | static struct clock_event_device integrator_clockevent = { | ||
323 | .name = "timer1", | ||
324 | .shift = 34, | ||
325 | .features = CLOCK_EVT_FEAT_PERIODIC, | ||
326 | .set_mode = clkevt_set_mode, | ||
327 | .set_next_event = clkevt_set_next_event, | ||
328 | .rating = 300, | ||
329 | .cpumask = cpu_all_mask, | ||
330 | }; | ||
331 | |||
332 | static struct irqaction integrator_timer_irq = { | ||
333 | .name = "timer", | ||
334 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
335 | .handler = integrator_timer_interrupt, | ||
336 | .dev_id = &integrator_clockevent, | ||
337 | }; | ||
338 | |||
339 | static void integrator_clockevent_init(u32 khz, unsigned int ctrl) | ||
340 | { | ||
341 | struct clock_event_device *evt = &integrator_clockevent; | ||
342 | |||
343 | if (khz * 1000 > 0x100000 * HZ) { | ||
344 | khz /= 256; | ||
345 | ctrl |= TIMER_CTRL_DIV256; | ||
346 | } else if (khz * 1000 > 0x10000 * HZ) { | ||
347 | khz /= 16; | ||
348 | ctrl |= TIMER_CTRL_DIV16; | ||
349 | } | ||
350 | |||
351 | timer_reload = khz * 1000 / HZ; | ||
352 | writel(ctrl, clkevt_base + TIMER_CTRL); | ||
353 | |||
354 | evt->irq = IRQ_TIMERINT1; | ||
355 | evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift); | ||
356 | evt->max_delta_ns = clockevent_delta2ns(0xffff, evt); | ||
357 | evt->min_delta_ns = clockevent_delta2ns(0xf, evt); | ||
358 | |||
359 | setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); | ||
360 | clockevents_register_device(evt); | ||
361 | } | ||
362 | |||
363 | /* | ||
364 | * Set up timer(s). | ||
365 | */ | ||
366 | void __init integrator_time_init(u32 khz, unsigned int ctrl) | ||
367 | { | ||
368 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | ||
369 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
370 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | ||
371 | |||
372 | integrator_clocksource_init(khz); | ||
373 | integrator_clockevent_init(khz, ctrl); | ||
374 | } | ||