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authorJiri Kosina <jkosina@suse.cz>2011-09-15 09:08:05 -0400
committerJiri Kosina <jkosina@suse.cz>2011-09-15 09:08:18 -0400
commite060c38434b2caa78efe7cedaff4191040b65a15 (patch)
tree407361230bf6733f63d8e788e4b5e6566ee04818 /arch/arm/mach-imx/clock-imx25.c
parent10e4ac572eeffe5317019bd7330b6058a400dfc2 (diff)
parentcc39c6a9bbdebfcf1a7dee64d83bf302bc38d941 (diff)
Merge branch 'master' into for-next
Fast-forward merge with Linus to be able to merge patches based on more recent version of the tree.
Diffstat (limited to 'arch/arm/mach-imx/clock-imx25.c')
-rw-r--r--arch/arm/mach-imx/clock-imx25.c23
1 files changed, 14 insertions, 9 deletions
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index af1c580b06b..e63e23504fe 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -272,11 +272,12 @@ DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
272 }, 272 },
273 273
274static struct clk_lookup lookups[] = { 274static struct clk_lookup lookups[] = {
275 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) 275 /* i.mx25 has the i.mx21 type uart */
276 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) 276 _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
277 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 277 _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
278 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) 278 _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
279 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) 279 _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
280 _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
280 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk) 281 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
281 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) 282 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
282 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) 283 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
@@ -295,19 +296,20 @@ static struct clk_lookup lookups[] = {
295 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 296 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
296 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) 297 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
297 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) 298 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
298 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 299 _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
299 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) 300 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
300 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 301 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
301 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk) 302 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
302 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 303 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
303 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 304 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
304 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 305 _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
305 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 306 _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
306 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) 307 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
307 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 308 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
308 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) 309 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
309 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) 310 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
310 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) 311 /* i.mx25 has the i.mx35 type sdma */
312 _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
311}; 313};
312 314
313int __init mx25_clocks_init(void) 315int __init mx25_clocks_init(void)
@@ -329,6 +331,9 @@ int __init mx25_clocks_init(void)
329 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), 331 __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
330 CRM_BASE + 0x64); 332 CRM_BASE + 0x64);
331 333
334 /* Clock source for gpt is ahb_div */
335 __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
336
332 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 337 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
333 338
334 return 0; 339 return 0;