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authorSachin Kamat <sachin.kamat@linaro.org>2012-11-07 19:24:08 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-11-07 19:24:08 -0500
commitcbd40b38f739a2db956bf2bdd663fed3ec86277e (patch)
tree6403e91983506fa04747ae36b45a429dc7c2364a /arch/arm/mach-exynos
parent96046ea38e8f6caee12e44bd9c4f699ae2832080 (diff)
ARM: EXYNOS: Add missing static storage class specifiers in clock-exynos5.c
Fixes the following warnings: arch/arm/mach-exynos/clock-exynos5.c:300:19: warning: symbol 'exynos5_clk_mout_mpll' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:475:12: warning: symbol 'exynos5_clkset_aclk_top_list' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:480:23: warning: symbol 'exynos5_clkset_aclk' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:494:12: warning: symbol 'exynos5_clkset_aclk_333_166_list' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:499:23: warning: symbol 'exynos5_clkset_aclk_333_166' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:989:12: warning: symbol 'exynos5_clkset_group_list' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:1002:23: warning: symbol 'exynos5_clkset_group' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:1218:19: warning: symbol 'exynos5_clk_sclk_fimd1' was not declared. Should it be static? arch/arm/mach-exynos/clock-exynos5.c:1499:20: warning: symbol 'exynos5_clock_syscore_ops' was not declared. Should it be static? Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index c44ca1ee1b8..4478757b930 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -292,7 +292,7 @@ static struct clksrc_sources exynos5_clk_src_mpll = {
292 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list), 292 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
293}; 293};
294 294
295struct clksrc_clk exynos5_clk_mout_mpll = { 295static struct clksrc_clk exynos5_clk_mout_mpll = {
296 .clk = { 296 .clk = {
297 .name = "mout_mpll", 297 .name = "mout_mpll",
298 }, 298 },
@@ -467,12 +467,12 @@ static struct clksrc_clk exynos5_clk_pclk_acp = {
467 467
468/* Core list of CMU_TOP side */ 468/* Core list of CMU_TOP side */
469 469
470struct clk *exynos5_clkset_aclk_top_list[] = { 470static struct clk *exynos5_clkset_aclk_top_list[] = {
471 [0] = &exynos5_clk_mout_mpll_user.clk, 471 [0] = &exynos5_clk_mout_mpll_user.clk,
472 [1] = &exynos5_clk_mout_bpll_user.clk, 472 [1] = &exynos5_clk_mout_bpll_user.clk,
473}; 473};
474 474
475struct clksrc_sources exynos5_clkset_aclk = { 475static struct clksrc_sources exynos5_clkset_aclk = {
476 .sources = exynos5_clkset_aclk_top_list, 476 .sources = exynos5_clkset_aclk_top_list,
477 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list), 477 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
478}; 478};
@@ -486,12 +486,12 @@ static struct clksrc_clk exynos5_clk_aclk_400 = {
486 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 }, 486 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
487}; 487};
488 488
489struct clk *exynos5_clkset_aclk_333_166_list[] = { 489static struct clk *exynos5_clkset_aclk_333_166_list[] = {
490 [0] = &exynos5_clk_mout_cpll.clk, 490 [0] = &exynos5_clk_mout_cpll.clk,
491 [1] = &exynos5_clk_mout_mpll_user.clk, 491 [1] = &exynos5_clk_mout_mpll_user.clk,
492}; 492};
493 493
494struct clksrc_sources exynos5_clkset_aclk_333_166 = { 494static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
495 .sources = exynos5_clkset_aclk_333_166_list, 495 .sources = exynos5_clkset_aclk_333_166_list,
496 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list), 496 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
497}; 497};
@@ -966,7 +966,7 @@ static struct clk exynos5_clk_fimd1 = {
966 .ctrlbit = (1 << 0), 966 .ctrlbit = (1 << 0),
967}; 967};
968 968
969struct clk *exynos5_clkset_group_list[] = { 969static struct clk *exynos5_clkset_group_list[] = {
970 [0] = &clk_ext_xtal_mux, 970 [0] = &clk_ext_xtal_mux,
971 [1] = NULL, 971 [1] = NULL,
972 [2] = &exynos5_clk_sclk_hdmi24m, 972 [2] = &exynos5_clk_sclk_hdmi24m,
@@ -979,7 +979,7 @@ struct clk *exynos5_clkset_group_list[] = {
979 [9] = &exynos5_clk_mout_cpll.clk, 979 [9] = &exynos5_clk_mout_cpll.clk,
980}; 980};
981 981
982struct clksrc_sources exynos5_clkset_group = { 982static struct clksrc_sources exynos5_clkset_group = {
983 .sources = exynos5_clkset_group_list, 983 .sources = exynos5_clkset_group_list,
984 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list), 984 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
985}; 985};
@@ -1195,7 +1195,7 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1195 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, 1195 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1196}; 1196};
1197 1197
1198struct clksrc_clk exynos5_clk_sclk_fimd1 = { 1198static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1199 .clk = { 1199 .clk = {
1200 .name = "sclk_fimd", 1200 .name = "sclk_fimd",
1201 .devname = "exynos5-fb.1", 1201 .devname = "exynos5-fb.1",
@@ -1476,7 +1476,7 @@ static void exynos5_clock_resume(void)
1476#define exynos5_clock_resume NULL 1476#define exynos5_clock_resume NULL
1477#endif 1477#endif
1478 1478
1479struct syscore_ops exynos5_clock_syscore_ops = { 1479static struct syscore_ops exynos5_clock_syscore_ops = {
1480 .suspend = exynos5_clock_suspend, 1480 .suspend = exynos5_clock_suspend,
1481 .resume = exynos5_clock_resume, 1481 .resume = exynos5_clock_resume,
1482}; 1482};