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authorKukjin Kim <kgene.kim@samsung.com>2011-10-04 07:14:11 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 07:14:11 -0400
commitc9477f38cba225870862fd9e08868ae3d4abdfe0 (patch)
tree01c7575a1e8e3197d072890f48944f1232a885c6 /arch/arm/mach-exynos4
parentc37b25046289e857918d25fd96aa441ea7929ad5 (diff)
parent2520123382e97271e932377c83bca010c265be55 (diff)
Merge branch 'next-samsung-board' into next-samsung-devel-2
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r--arch/arm/mach-exynos4/Kconfig40
-rw-r--r--arch/arm/mach-exynos4/Makefile9
-rw-r--r--arch/arm/mach-exynos4/clock-exynos4210.c139
-rw-r--r--arch/arm/mach-exynos4/clock-exynos4212.c118
-rw-r--r--arch/arm/mach-exynos4/clock.c218
-rw-r--r--arch/arm/mach-exynos4/cpu.c40
-rw-r--r--arch/arm/mach-exynos4/include/mach/exynos4-clock.h43
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h54
-rw-r--r--arch/arm/mach-exynos4/mach-origen.c108
-rw-r--r--arch/arm/mach-exynos4/mach-smdk4212.c292
-rw-r--r--arch/arm/mach-exynos4/platsmp.c8
-rw-r--r--arch/arm/mach-exynos4/pm.c79
13 files changed, 978 insertions, 173 deletions
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index bee8f77de2a..c595bb03f41 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -15,6 +15,11 @@ config CPU_EXYNOS4210
15 help 15 help
16 Enable EXYNOS4210 CPU support 16 Enable EXYNOS4210 CPU support
17 17
18config SOC_EXYNOS4212
19 bool
20 help
21 Enable EXYNOS4212 SoC support
22
18config EXYNOS4_MCT 23config EXYNOS4_MCT
19 bool 24 bool
20 default y 25 default y
@@ -111,6 +116,8 @@ config EXYNOS4_SETUP_USB_PHY
111 116
112menu "EXYNOS4 Machines" 117menu "EXYNOS4 Machines"
113 118
119comment "EXYNOS4210 Boards"
120
114config MACH_SMDKC210 121config MACH_SMDKC210
115 bool "SMDKC210" 122 bool "SMDKC210"
116 select MACH_SMDKV310 123 select MACH_SMDKV310
@@ -203,6 +210,39 @@ config MACH_NURI
203 help 210 help
204 Machine support for Samsung Mobile NURI Board. 211 Machine support for Samsung Mobile NURI Board.
205 212
213config MACH_ORIGEN
214 bool "ORIGEN"
215 select CPU_EXYNOS4210
216 select S3C_DEV_RTC
217 select S3C_DEV_WDT
218 select S3C_DEV_HSMMC2
219 select EXYNOS4_SETUP_SDHCI
220 help
221 Machine support for ORIGEN based on Samsung EXYNOS4210
222
223comment "EXYNOS4212 Boards"
224
225config MACH_SMDK4212
226 bool "SMDK4212"
227 select SOC_EXYNOS4212
228 select S3C_DEV_HSMMC2
229 select S3C_DEV_HSMMC3
230 select S3C_DEV_I2C1
231 select S3C_DEV_I2C3
232 select S3C_DEV_I2C7
233 select S3C_DEV_RTC
234 select S3C_DEV_WDT
235 select SAMSUNG_DEV_BACKLIGHT
236 select SAMSUNG_DEV_KEYPAD
237 select SAMSUNG_DEV_PWM
238 select EXYNOS4_SETUP_I2C1
239 select EXYNOS4_SETUP_I2C3
240 select EXYNOS4_SETUP_I2C7
241 select EXYNOS4_SETUP_KEYPAD
242 select EXYNOS4_SETUP_SDHCI
243 help
244 Machine support for Samsung SMDK4212
245
206endmenu 246endmenu
207 247
208comment "Configuration for HSMMC bus width" 248comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e3e93ea4138..e19cd12d264 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,8 +12,10 @@ obj- :=
12 12
13# Core support for EXYNOS4 system 13# Core support for EXYNOS4 system
14 14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o 16obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
17obj-$(CONFIG_PM) += pm.o sleep.o 19obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
19 21
@@ -30,6 +32,9 @@ obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
30obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o 32obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
31obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o 33obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
32obj-$(CONFIG_MACH_NURI) += mach-nuri.o 34obj-$(CONFIG_MACH_NURI) += mach-nuri.o
35obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
36
37obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o
33 38
34# device support 39# device support
35 40
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
new file mode 100644
index 00000000000..b9d5ef670eb
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -0,0 +1,139 @@
1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4210.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS4210 - Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <plat/cpu-freq.h>
21#include <plat/clock.h>
22#include <plat/cpu.h>
23#include <plat/pll.h>
24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h>
33
34static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKDIV_LCD1),
39 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
40 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
41 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
42 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
43};
44
45static struct clksrc_clk *sysclks[] = {
46 /* nothing here yet */
47};
48
49static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
52}
53
54static struct clksrc_clk clksrcs[] = {
55 {
56 .clk = {
57 .name = "sclk_sata",
58 .id = -1,
59 .enable = exynos4_clksrc_mask_fsys_ctrl,
60 .ctrlbit = (1 << 24),
61 },
62 .sources = &clkset_mout_corebus,
63 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
64 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
65 }, {
66 .clk = {
67 .name = "sclk_fimd",
68 .devname = "exynos4-fb.1",
69 .enable = exynos4_clksrc_mask_lcd1_ctrl,
70 .ctrlbit = (1 << 0),
71 },
72 .sources = &clkset_group,
73 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
74 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
75 },
76};
77
78static struct clk init_clocks_off[] = {
79 {
80 .name = "sataphy",
81 .id = -1,
82 .parent = &clk_aclk_133.clk,
83 .enable = exynos4_clk_ip_fsys_ctrl,
84 .ctrlbit = (1 << 3),
85 }, {
86 .name = "sata",
87 .id = -1,
88 .parent = &clk_aclk_133.clk,
89 .enable = exynos4_clk_ip_fsys_ctrl,
90 .ctrlbit = (1 << 10),
91 }, {
92 .name = "fimd",
93 .devname = "exynos4-fb.1",
94 .enable = exynos4_clk_ip_lcd1_ctrl,
95 .ctrlbit = (1 << 0),
96 },
97};
98
99#ifdef CONFIG_PM_SLEEP
100static int exynos4210_clock_suspend(void)
101{
102 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
103
104 return 0;
105}
106
107static void exynos4210_clock_resume(void)
108{
109 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
110}
111
112#else
113#define exynos4210_clock_suspend NULL
114#define exynos4210_clock_resume NULL
115#endif
116
117struct syscore_ops exynos4210_clock_syscore_ops = {
118 .suspend = exynos4210_clock_suspend,
119 .resume = exynos4210_clock_resume,
120};
121
122void __init exynos4210_register_clocks(void)
123{
124 int ptr;
125
126 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
127 clk_mout_mpll.reg_src.shift = 8;
128 clk_mout_mpll.reg_src.size = 1;
129
130 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
131 s3c_register_clksrc(sysclks[ptr], 1);
132
133 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
134
135 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
136 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
137
138 register_syscore_ops(&exynos4210_clock_syscore_ops);
139}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
new file mode 100644
index 00000000000..77d5decb34f
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -0,0 +1,118 @@
1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4212.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS4212 - Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <plat/cpu-freq.h>
21#include <plat/clock.h>
22#include <plat/cpu.h>
23#include <plat/pll.h>
24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h>
33
34static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKDIV_IMAGE),
37 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
38 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
39};
40
41static struct clk *clk_src_mpll_user_list[] = {
42 [0] = &clk_fin_mpll,
43 [1] = &clk_mout_mpll.clk,
44};
45
46static struct clksrc_sources clk_src_mpll_user = {
47 .sources = clk_src_mpll_user_list,
48 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
49};
50
51static struct clksrc_clk clk_mout_mpll_user = {
52 .clk = {
53 .name = "mout_mpll_user",
54 },
55 .sources = &clk_src_mpll_user,
56 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
57};
58
59static struct clksrc_clk *sysclks[] = {
60 &clk_mout_mpll_user,
61};
62
63static struct clksrc_clk clksrcs[] = {
64 /* nothing here yet */
65};
66
67static struct clk init_clocks_off[] = {
68 /* nothing here yet */
69};
70
71#ifdef CONFIG_PM_SLEEP
72static int exynos4212_clock_suspend(void)
73{
74 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
75
76 return 0;
77}
78
79static void exynos4212_clock_resume(void)
80{
81 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
82}
83
84#else
85#define exynos4212_clock_suspend NULL
86#define exynos4212_clock_resume NULL
87#endif
88
89struct syscore_ops exynos4212_clock_syscore_ops = {
90 .suspend = exynos4212_clock_suspend,
91 .resume = exynos4212_clock_resume,
92};
93
94void __init exynos4212_register_clocks(void)
95{
96 int ptr;
97
98 /* usbphy1 is removed */
99 clkset_group_list[4] = NULL;
100
101 /* mout_mpll_user is used */
102 clkset_group_list[6] = &clk_mout_mpll_user.clk;
103 clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
104
105 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
106 clk_mout_mpll.reg_src.shift = 12;
107 clk_mout_mpll.reg_src.size = 1;
108
109 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
110 s3c_register_clksrc(sysclks[ptr], 1);
111
112 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
113
114 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
115 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
116
117 register_syscore_ops(&exynos4212_clock_syscore_ops);
118}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 86964d2e9e1..413c7cc8197 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/syscore_ops.h>
16 17
17#include <plat/cpu-freq.h> 18#include <plat/cpu-freq.h>
18#include <plat/clock.h> 19#include <plat/clock.h>
@@ -20,26 +21,93 @@
20#include <plat/pll.h> 21#include <plat/pll.h>
21#include <plat/s5p-clock.h> 22#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h> 23#include <plat/clock-clksrc.h>
24#include <plat/exynos4.h>
25#include <plat/pm.h>
23 26
24#include <mach/map.h> 27#include <mach/map.h>
25#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
26#include <mach/sysmmu.h> 29#include <mach/sysmmu.h>
27 30#include <mach/exynos4-clock.h>
28static struct clk clk_sclk_hdmi27m = { 31
32static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKSRC_TOP0),
38 SAVE_ITEM(S5P_CLKSRC_TOP1),
39 SAVE_ITEM(S5P_CLKSRC_CAM),
40 SAVE_ITEM(S5P_CLKSRC_TV),
41 SAVE_ITEM(S5P_CLKSRC_MFC),
42 SAVE_ITEM(S5P_CLKSRC_G3D),
43 SAVE_ITEM(S5P_CLKSRC_LCD0),
44 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45 SAVE_ITEM(S5P_CLKSRC_FSYS),
46 SAVE_ITEM(S5P_CLKSRC_PERIL0),
47 SAVE_ITEM(S5P_CLKSRC_PERIL1),
48 SAVE_ITEM(S5P_CLKDIV_CAM),
49 SAVE_ITEM(S5P_CLKDIV_TV),
50 SAVE_ITEM(S5P_CLKDIV_MFC),
51 SAVE_ITEM(S5P_CLKDIV_G3D),
52 SAVE_ITEM(S5P_CLKDIV_LCD0),
53 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54 SAVE_ITEM(S5P_CLKDIV_FSYS0),
55 SAVE_ITEM(S5P_CLKDIV_FSYS1),
56 SAVE_ITEM(S5P_CLKDIV_FSYS2),
57 SAVE_ITEM(S5P_CLKDIV_FSYS3),
58 SAVE_ITEM(S5P_CLKDIV_PERIL0),
59 SAVE_ITEM(S5P_CLKDIV_PERIL1),
60 SAVE_ITEM(S5P_CLKDIV_PERIL2),
61 SAVE_ITEM(S5P_CLKDIV_PERIL3),
62 SAVE_ITEM(S5P_CLKDIV_PERIL4),
63 SAVE_ITEM(S5P_CLKDIV_PERIL5),
64 SAVE_ITEM(S5P_CLKDIV_TOP),
65 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(S5P_CLKDIV2_RATIO),
74 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_TV),
77 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83 SAVE_ITEM(S5P_CLKGATE_BLOCK),
84 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85 SAVE_ITEM(S5P_CLKSRC_DMC),
86 SAVE_ITEM(S5P_CLKDIV_DMC0),
87 SAVE_ITEM(S5P_CLKDIV_DMC1),
88 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89 SAVE_ITEM(S5P_CLKSRC_CPU),
90 SAVE_ITEM(S5P_CLKDIV_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
94};
95
96struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m", 97 .name = "sclk_hdmi27m",
30 .rate = 27000000, 98 .rate = 27000000,
31}; 99};
32 100
33static struct clk clk_sclk_hdmiphy = { 101struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy", 102 .name = "sclk_hdmiphy",
35}; 103};
36 104
37static struct clk clk_sclk_usbphy0 = { 105struct clk clk_sclk_usbphy0 = {
38 .name = "sclk_usbphy0", 106 .name = "sclk_usbphy0",
39 .rate = 27000000, 107 .rate = 27000000,
40}; 108};
41 109
42static struct clk clk_sclk_usbphy1 = { 110struct clk clk_sclk_usbphy1 = {
43 .name = "sclk_usbphy1", 111 .name = "sclk_usbphy1",
44}; 112};
45 113
@@ -58,12 +126,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
58 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); 126 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
59} 127}
60 128
61static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 129int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
62{
63 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
64}
65
66static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
67{ 130{
68 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); 131 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
69} 132}
@@ -103,12 +166,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
103 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); 166 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
104} 167}
105 168
106static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) 169int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
107{ 170{
108 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); 171 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
109} 172}
110 173
111static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) 174int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
112{ 175{
113 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); 176 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
114} 177}
@@ -133,7 +196,7 @@ static struct clksrc_clk clk_mout_apll = {
133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 196 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
134}; 197};
135 198
136static struct clksrc_clk clk_sclk_apll = { 199struct clksrc_clk clk_sclk_apll = {
137 .clk = { 200 .clk = {
138 .name = "sclk_apll", 201 .name = "sclk_apll",
139 .parent = &clk_mout_apll.clk, 202 .parent = &clk_mout_apll.clk,
@@ -141,7 +204,7 @@ static struct clksrc_clk clk_sclk_apll = {
141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 204 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
142}; 205};
143 206
144static struct clksrc_clk clk_mout_epll = { 207struct clksrc_clk clk_mout_epll = {
145 .clk = { 208 .clk = {
146 .name = "mout_epll", 209 .name = "mout_epll",
147 }, 210 },
@@ -149,12 +212,13 @@ static struct clksrc_clk clk_mout_epll = {
149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 212 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
150}; 213};
151 214
152static struct clksrc_clk clk_mout_mpll = { 215struct clksrc_clk clk_mout_mpll = {
153 .clk = { 216 .clk = {
154 .name = "mout_mpll", 217 .name = "mout_mpll",
155 }, 218 },
156 .sources = &clk_src_mpll, 219 .sources = &clk_src_mpll,
157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, 220
221 /* reg_src will be added in each SoCs' clock */
158}; 222};
159 223
160static struct clk *clkset_moutcore_list[] = { 224static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +288,12 @@ static struct clksrc_clk clk_periphclk = {
224 288
225/* Core list of CMU_CORE side */ 289/* Core list of CMU_CORE side */
226 290
227static struct clk *clkset_corebus_list[] = { 291struct clk *clkset_corebus_list[] = {
228 [0] = &clk_mout_mpll.clk, 292 [0] = &clk_mout_mpll.clk,
229 [1] = &clk_sclk_apll.clk, 293 [1] = &clk_sclk_apll.clk,
230}; 294};
231 295
232static struct clksrc_sources clkset_mout_corebus = { 296struct clksrc_sources clkset_mout_corebus = {
233 .sources = clkset_corebus_list, 297 .sources = clkset_corebus_list,
234 .nr_sources = ARRAY_SIZE(clkset_corebus_list), 298 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
235}; 299};
@@ -284,12 +348,12 @@ static struct clksrc_clk clk_pclk_acp = {
284 348
285/* Core list of CMU_TOP side */ 349/* Core list of CMU_TOP side */
286 350
287static struct clk *clkset_aclk_top_list[] = { 351struct clk *clkset_aclk_top_list[] = {
288 [0] = &clk_mout_mpll.clk, 352 [0] = &clk_mout_mpll.clk,
289 [1] = &clk_sclk_apll.clk, 353 [1] = &clk_sclk_apll.clk,
290}; 354};
291 355
292static struct clksrc_sources clkset_aclk = { 356struct clksrc_sources clkset_aclk = {
293 .sources = clkset_aclk_top_list, 357 .sources = clkset_aclk_top_list,
294 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), 358 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
295}; 359};
@@ -321,7 +385,7 @@ static struct clksrc_clk clk_aclk_160 = {
321 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, 385 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
322}; 386};
323 387
324static struct clksrc_clk clk_aclk_133 = { 388struct clksrc_clk clk_aclk_133 = {
325 .clk = { 389 .clk = {
326 .name = "aclk_133", 390 .name = "aclk_133",
327 }, 391 },
@@ -360,7 +424,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
360 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), 424 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
361}; 425};
362 426
363static struct clksrc_clk clk_sclk_vpll = { 427struct clksrc_clk clk_sclk_vpll = {
364 .clk = { 428 .clk = {
365 .name = "sclk_vpll", 429 .name = "sclk_vpll",
366 }, 430 },
@@ -410,16 +474,6 @@ static struct clk init_clocks_off[] = {
410 .enable = exynos4_clk_ip_lcd0_ctrl, 474 .enable = exynos4_clk_ip_lcd0_ctrl,
411 .ctrlbit = (1 << 0), 475 .ctrlbit = (1 << 0),
412 }, { 476 }, {
413 .name = "fimd",
414 .devname = "exynos4-fb.1",
415 .enable = exynos4_clk_ip_lcd1_ctrl,
416 .ctrlbit = (1 << 0),
417 }, {
418 .name = "sataphy",
419 .parent = &clk_aclk_133.clk,
420 .enable = exynos4_clk_ip_fsys_ctrl,
421 .ctrlbit = (1 << 3),
422 }, {
423 .name = "hsmmc", 477 .name = "hsmmc",
424 .devname = "s3c-sdhci.0", 478 .devname = "s3c-sdhci.0",
425 .parent = &clk_aclk_133.clk, 479 .parent = &clk_aclk_133.clk,
@@ -449,11 +503,6 @@ static struct clk init_clocks_off[] = {
449 .enable = exynos4_clk_ip_fsys_ctrl, 503 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 9), 504 .ctrlbit = (1 << 9),
451 }, { 505 }, {
452 .name = "sata",
453 .parent = &clk_aclk_133.clk,
454 .enable = exynos4_clk_ip_fsys_ctrl,
455 .ctrlbit = (1 << 10),
456 }, {
457 .name = "pdma", 506 .name = "pdma",
458 .devname = "s3c-pl330.0", 507 .devname = "s3c-pl330.0",
459 .enable = exynos4_clk_ip_fsys_ctrl, 508 .enable = exynos4_clk_ip_fsys_ctrl,
@@ -673,7 +722,7 @@ static struct clk init_clocks[] = {
673 } 722 }
674}; 723};
675 724
676static struct clk *clkset_group_list[] = { 725struct clk *clkset_group_list[] = {
677 [0] = &clk_ext_xtal_mux, 726 [0] = &clk_ext_xtal_mux,
678 [1] = &clk_xusbxti, 727 [1] = &clk_xusbxti,
679 [2] = &clk_sclk_hdmi27m, 728 [2] = &clk_sclk_hdmi27m,
@@ -685,7 +734,7 @@ static struct clk *clkset_group_list[] = {
685 [8] = &clk_sclk_vpll.clk, 734 [8] = &clk_sclk_vpll.clk,
686}; 735};
687 736
688static struct clksrc_sources clkset_group = { 737struct clksrc_sources clkset_group = {
689 .sources = clkset_group_list, 738 .sources = clkset_group_list,
690 .nr_sources = ARRAY_SIZE(clkset_group_list), 739 .nr_sources = ARRAY_SIZE(clkset_group_list),
691}; 740};
@@ -967,25 +1016,6 @@ static struct clksrc_clk clksrcs[] = {
967 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, 1016 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
968 }, { 1017 }, {
969 .clk = { 1018 .clk = {
970 .name = "sclk_fimd",
971 .devname = "exynos4-fb.1",
972 .enable = exynos4_clksrc_mask_lcd1_ctrl,
973 .ctrlbit = (1 << 0),
974 },
975 .sources = &clkset_group,
976 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
977 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
978 }, {
979 .clk = {
980 .name = "sclk_sata",
981 .enable = exynos4_clksrc_mask_fsys_ctrl,
982 .ctrlbit = (1 << 24),
983 },
984 .sources = &clkset_mout_corebus,
985 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
986 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
987 }, {
988 .clk = {
989 .name = "sclk_spi", 1019 .name = "sclk_spi",
990 .devname = "s3c64xx-spi.0", 1020 .devname = "s3c64xx-spi.0",
991 .enable = exynos4_clksrc_mask_peril1_ctrl, 1021 .enable = exynos4_clksrc_mask_peril1_ctrl,
@@ -1114,7 +1144,13 @@ static int xtal_rate;
1114 1144
1115static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 1145static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1116{ 1146{
1117 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); 1147 if (soc_is_exynos4210())
1148 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1149 pll_4508);
1150 else if (soc_is_exynos4212())
1151 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1152 else
1153 return 0;
1118} 1154}
1119 1155
1120static struct clk_ops exynos4_fout_apll_ops = { 1156static struct clk_ops exynos4_fout_apll_ops = {
@@ -1124,10 +1160,10 @@ static struct clk_ops exynos4_fout_apll_ops = {
1124void __init_or_cpufreq exynos4_setup_clocks(void) 1160void __init_or_cpufreq exynos4_setup_clocks(void)
1125{ 1161{
1126 struct clk *xtal_clk; 1162 struct clk *xtal_clk;
1127 unsigned long apll; 1163 unsigned long apll = 0;
1128 unsigned long mpll; 1164 unsigned long mpll = 0;
1129 unsigned long epll; 1165 unsigned long epll = 0;
1130 unsigned long vpll; 1166 unsigned long vpll = 0;
1131 unsigned long vpllsrc; 1167 unsigned long vpllsrc;
1132 unsigned long xtal; 1168 unsigned long xtal;
1133 unsigned long armclk; 1169 unsigned long armclk;
@@ -1151,14 +1187,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1151 1187
1152 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1188 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1153 1189
1154 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); 1190 if (soc_is_exynos4210()) {
1155 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); 1191 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1156 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), 1192 pll_4508);
1157 __raw_readl(S5P_EPLL_CON1), pll_4600); 1193 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1158 1194 pll_4508);
1159 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1195 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1160 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1196 __raw_readl(S5P_EPLL_CON1), pll_4600);
1161 __raw_readl(S5P_VPLL_CON1), pll_4650c); 1197
1198 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1199 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1200 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1201 } else if (soc_is_exynos4212()) {
1202 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1203 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1204 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1205 __raw_readl(S5P_EPLL_CON1));
1206
1207 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1208 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1209 __raw_readl(S5P_VPLL_CON1));
1210 } else {
1211 /* nothing */
1212 }
1162 1213
1163 clk_fout_apll.ops = &exynos4_fout_apll_ops; 1214 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1164 clk_fout_mpll.rate = mpll; 1215 clk_fout_mpll.rate = mpll;
@@ -1193,6 +1244,28 @@ static struct clk *clks[] __initdata = {
1193 /* Nothing here yet */ 1244 /* Nothing here yet */
1194}; 1245};
1195 1246
1247#ifdef CONFIG_PM_SLEEP
1248static int exynos4_clock_suspend(void)
1249{
1250 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1251 return 0;
1252}
1253
1254static void exynos4_clock_resume(void)
1255{
1256 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1257}
1258
1259#else
1260#define exynos4_clock_suspend NULL
1261#define exynos4_clock_resume NULL
1262#endif
1263
1264struct syscore_ops exynos4_clock_syscore_ops = {
1265 .suspend = exynos4_clock_suspend,
1266 .resume = exynos4_clock_resume,
1267};
1268
1196void __init exynos4_register_clocks(void) 1269void __init exynos4_register_clocks(void)
1197{ 1270{
1198 int ptr; 1271 int ptr;
@@ -1208,5 +1281,6 @@ void __init exynos4_register_clocks(void)
1208 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1209 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1210 1283
1284 register_syscore_ops(&exynos4_clock_syscore_ops);
1211 s3c_pwmclk_init(); 1285 s3c_pwmclk_init();
1212} 1286}
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 746d6fc6d39..02ec52a9927 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -44,11 +44,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
44 .length = SZ_4K, 44 .length = SZ_4K,
45 .type = MT_DEVICE, 45 .type = MT_DEVICE,
46 }, { 46 }, {
47 .virtual = (unsigned long)S5P_VA_SYSRAM,
48 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
49 .length = SZ_4K,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = (unsigned long)S5P_VA_CMU, 47 .virtual = (unsigned long)S5P_VA_CMU,
53 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 48 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
54 .length = SZ_128K, 49 .length = SZ_128K,
@@ -121,6 +116,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
121 }, 116 },
122}; 117};
123 118
119static struct map_desc exynos4_iodesc0[] __initdata = {
120 {
121 .virtual = (unsigned long)S5P_VA_SYSRAM,
122 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
123 .length = SZ_4K,
124 .type = MT_DEVICE,
125 },
126};
127
128static struct map_desc exynos4_iodesc1[] __initdata = {
129 {
130 .virtual = (unsigned long)S5P_VA_SYSRAM,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 },
135};
136
124static void exynos4_idle(void) 137static void exynos4_idle(void)
125{ 138{
126 if (!need_resched()) 139 if (!need_resched())
@@ -143,6 +156,11 @@ void __init exynos4_map_io(void)
143{ 156{
144 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 157 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
145 158
159 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
160 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
161 else
162 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
163
146 /* initialize device information early */ 164 /* initialize device information early */
147 exynos4_default_sdhci0(); 165 exynos4_default_sdhci0();
148 exynos4_default_sdhci1(); 166 exynos4_default_sdhci1();
@@ -170,6 +188,12 @@ void __init exynos4_init_clocks(int xtal)
170 188
171 s3c24xx_register_baseclocks(xtal); 189 s3c24xx_register_baseclocks(xtal);
172 s5p_register_clocks(xtal); 190 s5p_register_clocks(xtal);
191
192 if (soc_is_exynos4210())
193 exynos4210_register_clocks();
194 else if (soc_is_exynos4212())
195 exynos4212_register_clocks();
196
173 exynos4_register_clocks(); 197 exynos4_register_clocks();
174 exynos4_setup_clocks(); 198 exynos4_setup_clocks();
175} 199}
@@ -223,7 +247,11 @@ static int __init exynos4_l2x0_cache_init(void)
223{ 247{
224 /* TAG, Data Latency Control: 2cycle */ 248 /* TAG, Data Latency Control: 2cycle */
225 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 249 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
226 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 250
251 if (soc_is_exynos4210())
252 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
253 else if (soc_is_exynos4212())
254 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
227 255
228 /* L2X0 Prefetch Control */ 256 /* L2X0 Prefetch Control */
229 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); 257 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
new file mode 100644
index 00000000000..a07fcbf5525
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
1/*
2 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Header file for exynos4 clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_CLOCK_H
15#define __ASM_ARCH_CLOCK_H __FILE__
16
17#include <linux/clk.h>
18
19extern struct clk clk_sclk_hdmi27m;
20extern struct clk clk_sclk_usbphy0;
21extern struct clk clk_sclk_usbphy1;
22extern struct clk clk_sclk_hdmiphy;
23
24extern struct clksrc_clk clk_sclk_apll;
25extern struct clksrc_clk clk_mout_mpll;
26extern struct clksrc_clk clk_aclk_133;
27extern struct clksrc_clk clk_mout_epll;
28extern struct clksrc_clk clk_sclk_vpll;
29
30extern struct clk *clkset_corebus_list[];
31extern struct clksrc_sources clkset_mout_corebus;
32
33extern struct clk *clkset_aclk_top_list[];
34extern struct clksrc_sources clkset_aclk;
35
36extern struct clk *clkset_group_list[];
37extern struct clksrc_sources clkset_group;
38
39extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
40extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
41extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
42
43#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index d32296dc65e..7073ac73085 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -23,7 +23,8 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define EXYNOS4_PA_SYSRAM 0x02020000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
27 28
28#define EXYNOS4_PA_FIMC0 0x11800000 29#define EXYNOS4_PA_FIMC0 0x11800000
29#define EXYNOS4_PA_FIMC1 0x11810000 30#define EXYNOS4_PA_FIMC1 0x11810000
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb422f..6c37ebe9482 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -13,6 +13,7 @@
13#ifndef __ASM_ARCH_REGS_CLOCK_H 13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__ 14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15 15
16#include <plat/cpu.h>
16#include <mach/map.h> 17#include <mach/map.h>
17 18
18#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) 19#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
@@ -41,12 +42,20 @@
41#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) 42#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
42#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 43#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
43#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 44#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
44#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) 45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) 46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) 48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
49 49
50#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
51#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
52#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
53#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
54#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
55#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
56#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
57#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
58
50#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 59#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
51#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) 60#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
52#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) 61#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
@@ -54,7 +63,6 @@
54#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) 63#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
55#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) 64#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
56#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) 65#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
57#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
58#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) 66#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
59#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) 67#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
60#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) 68#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
@@ -68,16 +76,6 @@
68#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 76#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
69#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) 77#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
70 78
71#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
72#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
73#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
74#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
75#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
76#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
77#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
78#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
79#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
80
81#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) 79#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
82 80
83#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) 81#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
@@ -85,13 +83,20 @@
85#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) 83#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
86#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) 84#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
87#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) 85#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
88#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) 86#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
87 S5P_CLKREG(0x0C930) : \
88 S5P_CLKREG(0x04930))
89#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
90#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
89#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 91#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
90#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
91#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) 92#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
92#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) 93#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
93#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 94#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
94#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) 95#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
96 S5P_CLKREG(0x0C960) : \
97 S5P_CLKREG(0x08960))
98#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
99#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
95#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) 100#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
96 101
97#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) 102#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
@@ -102,11 +107,17 @@
102#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) 107#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
103 108
104#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 109#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
105#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) 110#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
111 S5P_CLKREG(0x14004) : \
112 S5P_CLKREG(0x10008))
106#define S5P_APLL_CON0 S5P_CLKREG(0x14100) 113#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
107#define S5P_APLL_CON1 S5P_CLKREG(0x14104) 114#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
108#define S5P_MPLL_CON0 S5P_CLKREG(0x14108) 115#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
109#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) 116 S5P_CLKREG(0x14108) : \
117 S5P_CLKREG(0x10108))
118#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
119 S5P_CLKREG(0x1410C) : \
120 S5P_CLKREG(0x1010C))
110 121
111#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) 122#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
112#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) 123#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
@@ -183,6 +194,13 @@
183#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) 194#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
184#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) 195#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
185 196
197/* Only for EXYNOS4210 */
198
199#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
200#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
201#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
202#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
203
186/* Compatibility defines and inclusion */ 204/* Compatibility defines and inclusion */
187 205
188#include <mach/regs-pmu.h> 206#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
new file mode 100644
index 00000000000..ed59f86001a
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -0,0 +1,108 @@
1/* linux/arch/arm/mach-exynos4/mach-origen.c
2 *
3 * Copyright (c) 2011 Insignal Co., Ltd.
4 * http://www.insignal.co.kr/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/input.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/regs-serial.h>
22#include <plat/exynos4.h>
23#include <plat/cpu.h>
24#include <plat/devs.h>
25#include <plat/sdhci.h>
26#include <plat/iic.h>
27
28#include <mach/map.h>
29
30/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
32 S3C2410_UCON_RXILEVEL | \
33 S3C2410_UCON_TXIRQMODE | \
34 S3C2410_UCON_RXIRQMODE | \
35 S3C2410_UCON_RXFIFO_TOI | \
36 S3C2443_UCON_RXERR_IRQEN)
37
38#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8
39
40#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
41 S5PV210_UFCON_TXTRIG4 | \
42 S5PV210_UFCON_RXTRIG4)
43
44static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = ORIGEN_UCON_DEFAULT,
49 .ulcon = ORIGEN_ULCON_DEFAULT,
50 .ufcon = ORIGEN_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = ORIGEN_UCON_DEFAULT,
56 .ulcon = ORIGEN_ULCON_DEFAULT,
57 .ufcon = ORIGEN_UFCON_DEFAULT,
58 },
59 [2] = {
60 .hwport = 2,
61 .flags = 0,
62 .ucon = ORIGEN_UCON_DEFAULT,
63 .ulcon = ORIGEN_ULCON_DEFAULT,
64 .ufcon = ORIGEN_UFCON_DEFAULT,
65 },
66 [3] = {
67 .hwport = 3,
68 .flags = 0,
69 .ucon = ORIGEN_UCON_DEFAULT,
70 .ulcon = ORIGEN_ULCON_DEFAULT,
71 .ufcon = ORIGEN_UFCON_DEFAULT,
72 },
73};
74
75static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
76 .cd_type = S3C_SDHCI_CD_GPIO,
77 .ext_cd_gpio = EXYNOS4_GPK2(2),
78 .ext_cd_gpio_invert = 1,
79 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
80};
81
82static struct platform_device *origen_devices[] __initdata = {
83 &s3c_device_hsmmc2,
84 &s3c_device_rtc,
85 &s3c_device_wdt,
86};
87
88static void __init origen_map_io(void)
89{
90 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
91 s3c24xx_init_clocks(24000000);
92 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
93}
94
95static void __init origen_machine_init(void)
96{
97 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
98 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
99}
100
101MACHINE_START(ORIGEN, "ORIGEN")
102 /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
103 .boot_params = S5P_PA_SDRAM + 0x100,
104 .init_irq = exynos4_init_irq,
105 .map_io = origen_map_io,
106 .init_machine = origen_machine_init,
107 .timer = &exynos4_timer,
108MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c
new file mode 100644
index 00000000000..3479a933a6d
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdk4212.c
@@ -0,0 +1,292 @@
1/*
2 * linux/arch/arm/mach-exynos4/mach-smdk4212.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/gpio.h>
13#include <linux/i2c.h>
14#include <linux/input.h>
15#include <linux/io.h>
16#include <linux/mfd/max8997.h>
17#include <linux/mmc/host.h>
18#include <linux/platform_device.h>
19#include <linux/pwm_backlight.h>
20#include <linux/regulator/machine.h>
21#include <linux/serial_core.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach-types.h>
25
26#include <plat/backlight.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/devs.h>
30#include <plat/exynos4.h>
31#include <plat/gpio-cfg.h>
32#include <plat/iic.h>
33#include <plat/keypad.h>
34#include <plat/regs-serial.h>
35#include <plat/sdhci.h>
36
37#include <mach/map.h>
38
39/* Following are default values for UCON, ULCON and UFCON UART registers */
40#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
41 S3C2410_UCON_RXILEVEL | \
42 S3C2410_UCON_TXIRQMODE | \
43 S3C2410_UCON_RXIRQMODE | \
44 S3C2410_UCON_RXFIFO_TOI | \
45 S3C2443_UCON_RXERR_IRQEN)
46
47#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8
48
49#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
50 S5PV210_UFCON_TXTRIG4 | \
51 S5PV210_UFCON_RXTRIG4)
52
53static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = {
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = SMDK4212_UCON_DEFAULT,
58 .ulcon = SMDK4212_ULCON_DEFAULT,
59 .ufcon = SMDK4212_UFCON_DEFAULT,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = SMDK4212_UCON_DEFAULT,
65 .ulcon = SMDK4212_ULCON_DEFAULT,
66 .ufcon = SMDK4212_UFCON_DEFAULT,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = SMDK4212_UCON_DEFAULT,
72 .ulcon = SMDK4212_ULCON_DEFAULT,
73 .ufcon = SMDK4212_UFCON_DEFAULT,
74 },
75 [3] = {
76 .hwport = 3,
77 .flags = 0,
78 .ucon = SMDK4212_UCON_DEFAULT,
79 .ulcon = SMDK4212_ULCON_DEFAULT,
80 .ufcon = SMDK4212_UFCON_DEFAULT,
81 },
82};
83
84static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = {
85 .cd_type = S3C_SDHCI_CD_INTERNAL,
86 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
87#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
88 .max_width = 8,
89 .host_caps = MMC_CAP_8_BIT_DATA,
90#endif
91};
92
93static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_INTERNAL,
95 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
96};
97
98static struct regulator_consumer_supply max8997_buck1 =
99 REGULATOR_SUPPLY("vdd_arm", NULL);
100
101static struct regulator_consumer_supply max8997_buck2 =
102 REGULATOR_SUPPLY("vdd_int", NULL);
103
104static struct regulator_consumer_supply max8997_buck3 =
105 REGULATOR_SUPPLY("vdd_g3d", NULL);
106
107static struct regulator_init_data max8997_buck1_data = {
108 .constraints = {
109 .name = "VDD_ARM_SMDK4212",
110 .min_uV = 925000,
111 .max_uV = 1350000,
112 .always_on = 1,
113 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
114 .state_mem = {
115 .disabled = 1,
116 },
117 },
118 .num_consumer_supplies = 1,
119 .consumer_supplies = &max8997_buck1,
120};
121
122static struct regulator_init_data max8997_buck2_data = {
123 .constraints = {
124 .name = "VDD_INT_SMDK4212",
125 .min_uV = 950000,
126 .max_uV = 1150000,
127 .always_on = 1,
128 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
129 .state_mem = {
130 .disabled = 1,
131 },
132 },
133 .num_consumer_supplies = 1,
134 .consumer_supplies = &max8997_buck2,
135};
136
137static struct regulator_init_data max8997_buck3_data = {
138 .constraints = {
139 .name = "VDD_G3D_SMDK4212",
140 .min_uV = 950000,
141 .max_uV = 1150000,
142 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
143 REGULATOR_CHANGE_STATUS,
144 .state_mem = {
145 .disabled = 1,
146 },
147 },
148 .num_consumer_supplies = 1,
149 .consumer_supplies = &max8997_buck3,
150};
151
152static struct max8997_regulator_data smdk4212_max8997_regulators[] = {
153 { MAX8997_BUCK1, &max8997_buck1_data },
154 { MAX8997_BUCK2, &max8997_buck2_data },
155 { MAX8997_BUCK3, &max8997_buck3_data },
156};
157
158static struct max8997_platform_data smdk4212_max8997_pdata = {
159 .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators),
160 .regulators = smdk4212_max8997_regulators,
161
162 .buck1_voltage[0] = 1100000, /* 1.1V */
163 .buck1_voltage[1] = 1100000, /* 1.1V */
164 .buck1_voltage[2] = 1100000, /* 1.1V */
165 .buck1_voltage[3] = 1100000, /* 1.1V */
166 .buck1_voltage[4] = 1100000, /* 1.1V */
167 .buck1_voltage[5] = 1100000, /* 1.1V */
168 .buck1_voltage[6] = 1000000, /* 1.0V */
169 .buck1_voltage[7] = 950000, /* 0.95V */
170
171 .buck2_voltage[0] = 1100000, /* 1.1V */
172 .buck2_voltage[1] = 1000000, /* 1.0V */
173 .buck2_voltage[2] = 950000, /* 0.95V */
174 .buck2_voltage[3] = 900000, /* 0.9V */
175 .buck2_voltage[4] = 1100000, /* 1.1V */
176 .buck2_voltage[5] = 1000000, /* 1.0V */
177 .buck2_voltage[6] = 950000, /* 0.95V */
178 .buck2_voltage[7] = 900000, /* 0.9V */
179
180 .buck5_voltage[0] = 1100000, /* 1.1V */
181 .buck5_voltage[1] = 1100000, /* 1.1V */
182 .buck5_voltage[2] = 1100000, /* 1.1V */
183 .buck5_voltage[3] = 1100000, /* 1.1V */
184 .buck5_voltage[4] = 1100000, /* 1.1V */
185 .buck5_voltage[5] = 1100000, /* 1.1V */
186 .buck5_voltage[6] = 1100000, /* 1.1V */
187 .buck5_voltage[7] = 1100000, /* 1.1V */
188};
189
190static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = {
191 {
192 I2C_BOARD_INFO("max8997", 0x66),
193 .platform_data = &smdk4212_max8997_pdata,
194 }
195};
196
197static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = {
198 { I2C_BOARD_INFO("wm8994", 0x1a), }
199};
200
201static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = {
202 /* nothing here yet */
203};
204
205static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = {
206 /* nothing here yet */
207};
208
209static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = {
210 .no = EXYNOS4_GPD0(1),
211 .func = S3C_GPIO_SFN(2),
212};
213
214static struct platform_pwm_backlight_data smdk4212_bl_data = {
215 .pwm_id = 1,
216 .pwm_period_ns = 1000,
217};
218
219static uint32_t smdk4212_keymap[] __initdata = {
220 /* KEY(row, col, keycode) */
221 KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
222 KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
223};
224
225static struct matrix_keymap_data smdk4212_keymap_data __initdata = {
226 .keymap = smdk4212_keymap,
227 .keymap_size = ARRAY_SIZE(smdk4212_keymap),
228};
229
230static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = {
231 .keymap_data = &smdk4212_keymap_data,
232 .rows = 2,
233 .cols = 5,
234};
235
236static struct platform_device *smdk4212_devices[] __initdata = {
237 &s3c_device_hsmmc2,
238 &s3c_device_hsmmc3,
239 &s3c_device_i2c0,
240 &s3c_device_i2c1,
241 &s3c_device_i2c3,
242 &s3c_device_i2c7,
243 &s3c_device_rtc,
244 &s3c_device_wdt,
245 &samsung_device_keypad,
246};
247
248static void __init smdk4212_map_io(void)
249{
250 clk_xusbxti.rate = 24000000;
251
252 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
253 s3c24xx_init_clocks(clk_xusbxti.rate);
254 s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs));
255}
256
257static void __init smdk4212_machine_init(void)
258{
259 s3c_i2c0_set_platdata(NULL);
260 i2c_register_board_info(0, smdk4212_i2c_devs0,
261 ARRAY_SIZE(smdk4212_i2c_devs0));
262
263 s3c_i2c1_set_platdata(NULL);
264 i2c_register_board_info(1, smdk4212_i2c_devs1,
265 ARRAY_SIZE(smdk4212_i2c_devs1));
266
267 s3c_i2c3_set_platdata(NULL);
268 i2c_register_board_info(3, smdk4212_i2c_devs3,
269 ARRAY_SIZE(smdk4212_i2c_devs3));
270
271 s3c_i2c7_set_platdata(NULL);
272 i2c_register_board_info(7, smdk4212_i2c_devs7,
273 ARRAY_SIZE(smdk4212_i2c_devs7));
274
275 samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data);
276
277 samsung_keypad_set_platdata(&smdk4212_keypad_data);
278
279 s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata);
280 s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata);
281
282 platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices));
283}
284
285MACHINE_START(SMDK4212, "SMDK4212")
286 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
287 .boot_params = S5P_PA_SDRAM + 0x100,
288 .init_irq = exynos4_init_irq,
289 .map_io = smdk4212_map_io,
290 .init_machine = smdk4212_machine_init,
291 .timer = &exynos4_timer,
292MACHINE_END
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index df6ef1b2f98..a3346e36d0a 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -30,9 +30,12 @@
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 31#include <mach/regs-pmu.h>
32 32
33#include <plat/cpu.h>
34
33extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
34 36
35#define CPU1_BOOT_REG S5P_VA_SYSRAM 37#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
38 S5P_INFORM5 : S5P_VA_SYSRAM)
36 39
37/* 40/*
38 * control for which core is the next to come out of the secondary 41 * control for which core is the next to come out of the secondary
@@ -218,5 +221,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
218 * until it receives a soft interrupt, and then the 221 * until it receives a soft interrupt, and then the
219 * secondary CPU branches to this address. 222 * secondary CPU branches to this address.
220 */ 223 */
221 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); 224 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
225 CPU1_BOOT_REG);
222} 226}
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca9482de..62e4f436300 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
41 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, 41 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, 42 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, 43 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
45 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, 44 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
46 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, 45 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
47 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, 46 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
49 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, 48 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
50}; 49};
51 50
51static struct sleep_save exynos4210_set_clksrc[] = {
52 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
53};
54
52static struct sleep_save exynos4_epll_save[] = { 55static struct sleep_save exynos4_epll_save[] = {
53 SAVE_ITEM(S5P_EPLL_CON0), 56 SAVE_ITEM(S5P_EPLL_CON0),
54 SAVE_ITEM(S5P_EPLL_CON1), 57 SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
60}; 63};
61 64
62static struct sleep_save exynos4_core_save[] = { 65static struct sleep_save exynos4_core_save[] = {
63 /* CMU side */
64 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
65 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
66 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
67 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
68 SAVE_ITEM(S5P_CLKSRC_TOP0),
69 SAVE_ITEM(S5P_CLKSRC_TOP1),
70 SAVE_ITEM(S5P_CLKSRC_CAM),
71 SAVE_ITEM(S5P_CLKSRC_TV),
72 SAVE_ITEM(S5P_CLKSRC_MFC),
73 SAVE_ITEM(S5P_CLKSRC_G3D),
74 SAVE_ITEM(S5P_CLKSRC_IMAGE),
75 SAVE_ITEM(S5P_CLKSRC_LCD0),
76 SAVE_ITEM(S5P_CLKSRC_LCD1),
77 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
78 SAVE_ITEM(S5P_CLKSRC_FSYS),
79 SAVE_ITEM(S5P_CLKSRC_PERIL0),
80 SAVE_ITEM(S5P_CLKSRC_PERIL1),
81 SAVE_ITEM(S5P_CLKDIV_CAM),
82 SAVE_ITEM(S5P_CLKDIV_TV),
83 SAVE_ITEM(S5P_CLKDIV_MFC),
84 SAVE_ITEM(S5P_CLKDIV_G3D),
85 SAVE_ITEM(S5P_CLKDIV_IMAGE),
86 SAVE_ITEM(S5P_CLKDIV_LCD0),
87 SAVE_ITEM(S5P_CLKDIV_LCD1),
88 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
89 SAVE_ITEM(S5P_CLKDIV_FSYS0),
90 SAVE_ITEM(S5P_CLKDIV_FSYS1),
91 SAVE_ITEM(S5P_CLKDIV_FSYS2),
92 SAVE_ITEM(S5P_CLKDIV_FSYS3),
93 SAVE_ITEM(S5P_CLKDIV_PERIL0),
94 SAVE_ITEM(S5P_CLKDIV_PERIL1),
95 SAVE_ITEM(S5P_CLKDIV_PERIL2),
96 SAVE_ITEM(S5P_CLKDIV_PERIL3),
97 SAVE_ITEM(S5P_CLKDIV_PERIL4),
98 SAVE_ITEM(S5P_CLKDIV_PERIL5),
99 SAVE_ITEM(S5P_CLKDIV_TOP),
100 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
101 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
102 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
103 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
104 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
105 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
106 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
107 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
108 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
109 SAVE_ITEM(S5P_CLKDIV2_RATIO),
110 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
111 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
112 SAVE_ITEM(S5P_CLKGATE_IP_TV),
113 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
114 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
115 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
116 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
117 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
118 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
119 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
120 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
121 SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
122 SAVE_ITEM(S5P_CLKGATE_BLOCK),
123 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
124 SAVE_ITEM(S5P_CLKSRC_DMC),
125 SAVE_ITEM(S5P_CLKDIV_DMC0),
126 SAVE_ITEM(S5P_CLKDIV_DMC1),
127 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
128 SAVE_ITEM(S5P_CLKSRC_CPU),
129 SAVE_ITEM(S5P_CLKDIV_CPU),
130 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
131 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
132 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
133
134 /* GIC side */ 66 /* GIC side */
135 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), 67 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
136 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), 68 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
268 200
269 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); 201 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
270 202
203 if (soc_is_exynos4210())
204 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
205
271} 206}
272 207
273static int exynos4_pm_add(struct sys_device *sysdev) 208static int exynos4_pm_add(struct sys_device *sysdev)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 07:55:10 -0500