ARM: EXYNOS4: Add support PM for EXYNOS4212

This patch moves regarding clock stuff of PM into clock
file to support PM on EXYNOS4210 and EXYNOS4212 with one
single kernel image. Because some clock registers are
different on each SoCs.

Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
[kgene.kim@samsung.com: use CONFIG_PM_SLEEP instead of CONFIG_PM]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 7 insertions, 72 deletions

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca9482de..62e4f436300 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
         { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
         { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
-        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
         { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
         { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
         { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
 };
 
+static struct sleep_save exynos4210_set_clksrc[] = {
+        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+};
+
 static struct sleep_save exynos4_epll_save[] = {
         SAVE_ITEM(S5P_EPLL_CON0),
         SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
 };
 
 static struct sleep_save exynos4_core_save[] = {
-        /* CMU side */
-        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKSRC_TOP0),
-        SAVE_ITEM(S5P_CLKSRC_TOP1),
-        SAVE_ITEM(S5P_CLKSRC_CAM),
-        SAVE_ITEM(S5P_CLKSRC_TV),
-        SAVE_ITEM(S5P_CLKSRC_MFC),
-        SAVE_ITEM(S5P_CLKSRC_G3D),
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_CAM),
-        SAVE_ITEM(S5P_CLKDIV_TV),
-        SAVE_ITEM(S5P_CLKDIV_MFC),
-        SAVE_ITEM(S5P_CLKDIV_G3D),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_LCD0),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-        SAVE_ITEM(S5P_CLKDIV_FSYS0),
-        SAVE_ITEM(S5P_CLKDIV_FSYS1),
-        SAVE_ITEM(S5P_CLKDIV_FSYS2),
-        SAVE_ITEM(S5P_CLKDIV_FSYS3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL0),
-        SAVE_ITEM(S5P_CLKDIV_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_PERIL2),
-        SAVE_ITEM(S5P_CLKDIV_PERIL3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL4),
-        SAVE_ITEM(S5P_CLKDIV_PERIL5),
-        SAVE_ITEM(S5P_CLKDIV_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV2_RATIO),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_TV),
-        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-        SAVE_ITEM(S5P_CLKSRC_DMC),
-        SAVE_ITEM(S5P_CLKDIV_DMC0),
-        SAVE_ITEM(S5P_CLKDIV_DMC1),
-        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-        SAVE_ITEM(S5P_CLKSRC_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-
         /* GIC side */
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
 
         s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 
+        if (soc_is_exynos4210())
+                s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+
 }
 
 static int exynos4_pm_add(struct sys_device *sysdev)