Added missing tegra files.HEAD master

author: Jonathan Herman <hermanjl@cs.unc.edu> 2013-01-22 10:38:37 -0500
committer: Jonathan Herman <hermanjl@cs.unc.edu> 2013-01-22 10:38:37 -0500
commit: fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
tree: a57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-exynos4/mct.c
parent: 8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
1 files changed, 429 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
new file mode 100644
index 00000000000..ddd86864fb8
--- /dev/null
+++ b/arch/arm/mach-exynos4/mct.c
@@ -0,0 +1,429 @@
+/* linux/arch/arm/mach-exynos4/mct.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 MCT(Multi-Core Timer) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/percpu.h>
+#include <mach/map.h>
+#include <mach/regs-mct.h>
+#include <asm/mach/time.h>
+static unsigned long clk_cnt_per_tick;
+static unsigned long clk_rate;
+struct mct_clock_event_device {
+        struct clock_event_device *evt;
+        void __iomem *base;
+};
+struct mct_clock_event_device mct_tick[2];
+static void exynos4_mct_write(unsigned int value, void *addr)
+{
+        void __iomem *stat_addr;
+        u32 mask;
+        u32 i;
+        __raw_writel(value, addr);
+        switch ((u32) addr) {
+        case (u32) EXYNOS4_MCT_G_TCON:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 16;         /* G_TCON write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_COMP0_L:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 0;          /* G_COMP0_L write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_COMP0_U:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 1;          /* G_COMP0_U write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                stat_addr = EXYNOS4_MCT_G_WSTAT;
+                mask = 1 << 2;          /* G_COMP0_ADD_INCR write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_CNT_L:
+                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                mask = 1 << 0;          /* G_CNT_L write status */
+                break;
+        case (u32) EXYNOS4_MCT_G_CNT_U:
+                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                mask = 1 << 1;          /* G_CNT_U write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
+                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 3;          /* L0_TCON write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
+                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 3;          /* L1_TCON write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 0;          /* L0_TCNTB write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 0;          /* L1_TCNTB write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 1;          /* L0_ICNTB write status */
+                break;
+        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
+                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
+                mask = 1 << 1;          /* L1_ICNTB write status */
+                break;
+        default:
+                return;
+        }
+        /* Wait maximum 1 ms until written values are applied */
+        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
+                if (__raw_readl(stat_addr) & mask) {
+                        __raw_writel(mask, stat_addr);
+                        return;
+                }
+        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+}
+/* Clocksource handling */
+static void exynos4_mct_frc_start(u32 hi, u32 lo)
+{
+        u32 reg;
+        exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
+        exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
+        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+        reg |= MCT_G_TCON_START;
+        exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
+}
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+        unsigned int lo, hi;
+        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+        do {
+                hi = hi2;
+                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
+                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+        } while (hi != hi2);
+        return ((cycle_t)hi << 32) | lo;
+}
+static void exynos4_frc_resume(struct clocksource *cs)
+{
+        exynos4_mct_frc_start(0, 0);
+}
+struct clocksource mct_frc = {
+        .name           = "mct-frc",
+        .rating         = 400,
+        .read           = exynos4_frc_read,
+        .mask           = CLOCKSOURCE_MASK(64),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+        .resume         = exynos4_frc_resume,
+};
+static void __init exynos4_clocksource_init(void)
+{
+        exynos4_mct_frc_start(0, 0);
+        if (clocksource_register_hz(&mct_frc, clk_rate))
+                panic("%s: can't register clocksource\n", mct_frc.name);
+}
+static void exynos4_mct_comp0_stop(void)
+{
+        unsigned int tcon;
+        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
+        exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
+        exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
+}
+static void exynos4_mct_comp0_start(enum clock_event_mode mode,
+                                    unsigned long cycles)
+{
+        unsigned int tcon;
+        cycle_t comp_cycle;
+        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        if (mode == CLOCK_EVT_MODE_PERIODIC) {
+                tcon |= MCT_G_TCON_COMP0_AUTO_INC;
+                exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
+        }
+        comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
+        exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
+        exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
+        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
+        tcon |= MCT_G_TCON_COMP0_ENABLE;
+        exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
+}
+static int exynos4_comp_set_next_event(unsigned long cycles,
+                                       struct clock_event_device *evt)
+{
+        exynos4_mct_comp0_start(evt->mode, cycles);
+        return 0;
+}
+static void exynos4_comp_set_mode(enum clock_event_mode mode,
+                                  struct clock_event_device *evt)
+{
+        exynos4_mct_comp0_stop();
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+static struct clock_event_device mct_comp_device = {
+        .name           = "mct-comp",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .rating         = 250,
+        .set_next_event = exynos4_comp_set_next_event,
+        .set_mode       = exynos4_comp_set_mode,
+};
+static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+static struct irqaction mct_comp_event_irq = {
+        .name           = "mct_comp_irq",
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = exynos4_mct_comp_isr,
+        .dev_id         = &mct_comp_device,
+};
+static void exynos4_clockevent_init(void)
+{
+        clk_cnt_per_tick = clk_rate / 2 / HZ;
+        clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
+        mct_comp_device.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &mct_comp_device);
+        mct_comp_device.min_delta_ns =
+                clockevent_delta2ns(0xf, &mct_comp_device);
+        mct_comp_device.cpumask = cpumask_of(0);
+        clockevents_register_device(&mct_comp_device);
+        setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+}
+#ifdef CONFIG_LOCAL_TIMERS
+/* Clock event handling */
+static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
+{
+        unsigned long tmp;
+        unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
+        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+        tmp = __raw_readl(addr);
+        if (tmp & mask) {
+                tmp &= ~mask;
+                exynos4_mct_write(tmp, addr);
+        }
+}
+static void exynos4_mct_tick_start(unsigned long cycles,
+                                   struct mct_clock_event_device *mevt)
+{
+        unsigned long tmp;
+        exynos4_mct_tick_stop(mevt);
+        tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
+        /* update interrupt count buffer */
+        exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
+        /* enable MCT tick interrupt */
+        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
+        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+        tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
+               MCT_L_TCON_INTERVAL_MODE;
+        exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
+}
+static int exynos4_tick_set_next_event(unsigned long cycles,
+                                       struct clock_event_device *evt)
+{
+        struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+        exynos4_mct_tick_start(cycles, mevt);
+        return 0;
+}
+static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
+                                         struct clock_event_device *evt)
+{
+        struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
+        exynos4_mct_tick_stop(mevt);
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+        struct mct_clock_event_device *mevt = dev_id;
+        struct clock_event_device *evt = mevt->evt;
+        /*
+         * This is for supporting oneshot mode.
+         * Mct would generate interrupt periodically
+         * without explicit stopping.
+         */
+        if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
+                exynos4_mct_tick_stop(mevt);
+        /* Clear the MCT tick interrupt */
+        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+static struct irqaction mct_tick0_event_irq = {
+        .name           = "mct_tick0_irq",
+        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
+        .handler        = exynos4_mct_tick_isr,
+};
+static struct irqaction mct_tick1_event_irq = {
+        .name           = "mct_tick1_irq",
+        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
+        .handler        = exynos4_mct_tick_isr,
+};
+static void exynos4_mct_tick_init(struct clock_event_device *evt)
+{
+        unsigned int cpu = smp_processor_id();
+        mct_tick[cpu].evt = evt;
+        if (cpu == 0) {
+                mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
+                evt->name = "mct_tick0";
+        } else {
+                mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
+                evt->name = "mct_tick1";
+        }
+        evt->cpumask = cpumask_of(cpu);
+        evt->set_next_event = exynos4_tick_set_next_event;
+        evt->set_mode = exynos4_tick_set_mode;
+        evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        evt->rating = 450;
+        clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
+        evt->max_delta_ns =
+                clockevent_delta2ns(0x7fffffff, evt);
+        evt->min_delta_ns =
+                clockevent_delta2ns(0xf, evt);
+        clockevents_register_device(evt);
+        exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
+        if (cpu == 0) {
+                mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+        } else {
+                mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+                irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+        }
+}
+/* Setup the local clock events for a CPU */
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        exynos4_mct_tick_init(evt);
+        return 0;
+}
+int local_timer_ack(void)
+{
+        return 0;
+}
+#endif /* CONFIG_LOCAL_TIMERS */
+static void __init exynos4_timer_resources(void)
+{
+        struct clk *mct_clk;
+        mct_clk = clk_get(NULL, "xtal");
+        clk_rate = clk_get_rate(mct_clk);
+}
+static void __init exynos4_timer_init(void)
+{
+        exynos4_timer_resources();
+        exynos4_clocksource_init();
+        exynos4_clockevent_init();
+}
+struct sys_timer exynos4_timer = {
+        .init           = exynos4_timer_init,
+};
author	Jonathan Herman <hermanjl@cs.unc.edu>	2013-01-22 10:38:37 -0500
committer	Jonathan Herman <hermanjl@cs.unc.edu>	2013-01-22 10:38:37 -0500
commit	fcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
tree	a57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-exynos4/mct.c
parent	8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)

diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c new file mode 100644 index 00000000000..ddd86864fb8 --- /dev/null +++ b/arch/arm/mach-exynos4/mct.c
@@ -0,0 +1,429 @@
	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/delay.h>
	21	#include <linux/percpu.h>
	22
	23	#include <mach/map.h>
	24	#include <mach/regs-mct.h>
	25	#include <asm/mach/time.h>
	26
	27	static unsigned long clk_cnt_per_tick;
	28	static unsigned long clk_rate;
	29
	30	struct mct_clock_event_device {
	31	struct clock_event_device *evt;
	32	void __iomem *base;
	33	};
	34
	35	struct mct_clock_event_device mct_tick[2];
	36
	37	static void exynos4_mct_write(unsigned int value, void *addr)
	38	{
	39	void __iomem *stat_addr;
	40	u32 mask;
	41	u32 i;
	42
	43	__raw_writel(value, addr);
	44
	45	switch ((u32) addr) {
	46	case (u32) EXYNOS4_MCT_G_TCON:
	47	stat_addr = EXYNOS4_MCT_G_WSTAT;
	48	mask = 1 << 16; /* G_TCON write status */
	49	break;
	50	case (u32) EXYNOS4_MCT_G_COMP0_L:
	51	stat_addr = EXYNOS4_MCT_G_WSTAT;
	52	mask = 1 << 0; /* G_COMP0_L write status */
	53	break;
	54	case (u32) EXYNOS4_MCT_G_COMP0_U:
	55	stat_addr = EXYNOS4_MCT_G_WSTAT;
	56	mask = 1 << 1; /* G_COMP0_U write status */
	57	break;
	58	case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
	59	stat_addr = EXYNOS4_MCT_G_WSTAT;
	60	mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
	61	break;
	62	case (u32) EXYNOS4_MCT_G_CNT_L:
	63	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	64	mask = 1 << 0; /* G_CNT_L write status */
	65	break;
	66	case (u32) EXYNOS4_MCT_G_CNT_U:
	67	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	68	mask = 1 << 1; /* G_CNT_U write status */
	69	break;
	70	case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
	71	stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
	72	mask = 1 << 3; /* L0_TCON write status */
	73	break;
	74	case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
	75	stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
	76	mask = 1 << 3; /* L1_TCON write status */
	77	break;
	78	case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
	79	stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
	80	mask = 1 << 0; /* L0_TCNTB write status */
	81	break;
	82	case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
	83	stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
	84	mask = 1 << 0; /* L1_TCNTB write status */
	85	break;
	86	case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
	87	stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
	88	mask = 1 << 1; /* L0_ICNTB write status */
	89	break;
	90	case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
	91	stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
	92	mask = 1 << 1; /* L1_ICNTB write status */
	93	break;
	94	default:
	95	return;
	96	}
	97
	98	/* Wait maximum 1 ms until written values are applied */
	99	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
	100	if (__raw_readl(stat_addr) & mask) {
	101	__raw_writel(mask, stat_addr);
	102	return;
	103	}
	104
	105	panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
	106	}
	107
	108	/* Clocksource handling */
	109	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	110	{
	111	u32 reg;
	112
	113	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	114	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	115
	116	reg = __raw_readl(EXYNOS4_MCT_G_TCON);
	117	reg \|= MCT_G_TCON_START;
	118	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	119	}
	120
	121	static cycle_t exynos4_frc_read(struct clocksource *cs)
	122	{
	123	unsigned int lo, hi;
	124	u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
	125
	126	do {
	127	hi = hi2;
	128	lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
	129	hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
	130	} while (hi != hi2);
	131
	132	return ((cycle_t)hi << 32) \| lo;
	133	}
	134
	135	static void exynos4_frc_resume(struct clocksource *cs)
	136	{
	137	exynos4_mct_frc_start(0, 0);
	138	}
	139
	140	struct clocksource mct_frc = {
	141	.name = "mct-frc",
	142	.rating = 400,
	143	.read = exynos4_frc_read,
	144	.mask = CLOCKSOURCE_MASK(64),
	145	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	146	.resume = exynos4_frc_resume,
	147	};
	148
	149	static void __init exynos4_clocksource_init(void)
	150	{
	151	exynos4_mct_frc_start(0, 0);
	152
	153	if (clocksource_register_hz(&mct_frc, clk_rate))
	154	panic("%s: can't register clocksource\n", mct_frc.name);
	155	}
	156
	157	static void exynos4_mct_comp0_stop(void)
	158	{
	159	unsigned int tcon;
	160
	161	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
	162	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	163
	164	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	165	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	166	}
	167
	168	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	169	unsigned long cycles)
	170	{
	171	unsigned int tcon;
	172	cycle_t comp_cycle;
	173
	174	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
	175
	176	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	177	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	178	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	179	}
	180
	181	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	182	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	183	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	184
	185	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	186
	187	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	188	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	189	}
	190
	191	static int exynos4_comp_set_next_event(unsigned long cycles,
	192	struct clock_event_device *evt)
	193	{
	194	exynos4_mct_comp0_start(evt->mode, cycles);
	195
	196	return 0;
	197	}
	198
	199	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	200	struct clock_event_device *evt)
	201	{
	202	exynos4_mct_comp0_stop();
	203
	204	switch (mode) {
	205	case CLOCK_EVT_MODE_PERIODIC:
	206	exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
	207	break;
	208
	209	case CLOCK_EVT_MODE_ONESHOT:
	210	case CLOCK_EVT_MODE_UNUSED:
	211	case CLOCK_EVT_MODE_SHUTDOWN:
	212	case CLOCK_EVT_MODE_RESUME:
	213	break;
	214	}
	215	}
	216
	217	static struct clock_event_device mct_comp_device = {
	218	.name = "mct-comp",
	219	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	220	.rating = 250,
	221	.set_next_event = exynos4_comp_set_next_event,
	222	.set_mode = exynos4_comp_set_mode,
	223	};
	224
	225	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	226	{
	227	struct clock_event_device *evt = dev_id;
	228
	229	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	230
	231	evt->event_handler(evt);
	232
	233	return IRQ_HANDLED;
	234	}
	235
	236	static struct irqaction mct_comp_event_irq = {
	237	.name = "mct_comp_irq",
	238	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	239	.handler = exynos4_mct_comp_isr,
	240	.dev_id = &mct_comp_device,
	241	};
	242
	243	static void exynos4_clockevent_init(void)
	244	{
	245	clk_cnt_per_tick = clk_rate / 2 / HZ;
	246
	247	clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
	248	mct_comp_device.max_delta_ns =
	249	clockevent_delta2ns(0xffffffff, &mct_comp_device);
	250	mct_comp_device.min_delta_ns =
	251	clockevent_delta2ns(0xf, &mct_comp_device);
	252	mct_comp_device.cpumask = cpumask_of(0);
	253	clockevents_register_device(&mct_comp_device);
	254
	255	setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
	256	}
	257
	258	#ifdef CONFIG_LOCAL_TIMERS
	259	/* Clock event handling */
	260	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	261	{
	262	unsigned long tmp;
	263	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
	264	void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
	265
	266	tmp = __raw_readl(addr);
	267	if (tmp & mask) {
	268	tmp &= ~mask;
	269	exynos4_mct_write(tmp, addr);
	270	}
	271	}
	272
	273	static void exynos4_mct_tick_start(unsigned long cycles,
	274	struct mct_clock_event_device *mevt)
	275	{
	276	unsigned long tmp;
	277
	278	exynos4_mct_tick_stop(mevt);
	279
	280	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	281
	282	/* update interrupt count buffer */
	283	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	284
	285	/* enable MCT tick interrupt */
	286	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
	287
	288	tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
	289	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	290	MCT_L_TCON_INTERVAL_MODE;
	291	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	292	}
	293
	294	static int exynos4_tick_set_next_event(unsigned long cycles,
	295	struct clock_event_device *evt)
	296	{
	297	struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
	298
	299	exynos4_mct_tick_start(cycles, mevt);
	300
	301	return 0;
	302	}
	303
	304	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	305	struct clock_event_device *evt)
	306	{
	307	struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
	308
	309	exynos4_mct_tick_stop(mevt);
	310
	311	switch (mode) {
	312	case CLOCK_EVT_MODE_PERIODIC:
	313	exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
	314	break;
	315
	316	case CLOCK_EVT_MODE_ONESHOT:
	317	case CLOCK_EVT_MODE_UNUSED:
	318	case CLOCK_EVT_MODE_SHUTDOWN:
	319	case CLOCK_EVT_MODE_RESUME:
	320	break;
	321	}
	322	}
	323
	324	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	325	{
	326	struct mct_clock_event_device *mevt = dev_id;
	327	struct clock_event_device *evt = mevt->evt;
	328
	329	/*
	330	* This is for supporting oneshot mode.
	331	* Mct would generate interrupt periodically
	332	* without explicit stopping.
	333	*/
	334	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	335	exynos4_mct_tick_stop(mevt);
	336
	337	/* Clear the MCT tick interrupt */
	338	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	339
	340	evt->event_handler(evt);
	341
	342	return IRQ_HANDLED;
	343	}
	344
	345	static struct irqaction mct_tick0_event_irq = {
	346	.name = "mct_tick0_irq",
	347	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	348	.handler = exynos4_mct_tick_isr,
	349	};
	350
	351	static struct irqaction mct_tick1_event_irq = {
	352	.name = "mct_tick1_irq",
	353	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	354	.handler = exynos4_mct_tick_isr,
	355	};
	356
	357	static void exynos4_mct_tick_init(struct clock_event_device *evt)
	358	{
	359	unsigned int cpu = smp_processor_id();
	360
	361	mct_tick[cpu].evt = evt;
	362
	363	if (cpu == 0) {
	364	mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
	365	evt->name = "mct_tick0";
	366	} else {
	367	mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
	368	evt->name = "mct_tick1";
	369	}
	370
	371	evt->cpumask = cpumask_of(cpu);
	372	evt->set_next_event = exynos4_tick_set_next_event;
	373	evt->set_mode = exynos4_tick_set_mode;
	374	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	375	evt->rating = 450;
	376
	377	clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
	378	evt->max_delta_ns =
	379	clockevent_delta2ns(0x7fffffff, evt);
	380	evt->min_delta_ns =
	381	clockevent_delta2ns(0xf, evt);
	382
	383	clockevents_register_device(evt);
	384
	385	exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
	386
	387	if (cpu == 0) {
	388	mct_tick0_event_irq.dev_id = &mct_tick[cpu];
	389	setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
	390	} else {
	391	mct_tick1_event_irq.dev_id = &mct_tick[cpu];
	392	setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
	393	irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
	394	}
	395	}
	396
	397	/* Setup the local clock events for a CPU */
	398	int __cpuinit local_timer_setup(struct clock_event_device *evt)
	399	{
	400	exynos4_mct_tick_init(evt);
	401
	402	return 0;
	403	}
	404
	405	int local_timer_ack(void)
	406	{
	407	return 0;
	408	}
	409
	410	#endif /* CONFIG_LOCAL_TIMERS */
	411
	412	static void __init exynos4_timer_resources(void)
	413	{
	414	struct clk *mct_clk;
	415	mct_clk = clk_get(NULL, "xtal");
	416
	417	clk_rate = clk_get_rate(mct_clk);
	418	}
	419
	420	static void __init exynos4_timer_init(void)
	421	{
	422	exynos4_timer_resources();
	423	exynos4_clocksource_init();
	424	exynos4_clockevent_init();
	425	}
	426
	427	struct sys_timer exynos4_timer = {
	428	.init = exynos4_timer_init,
	429	};