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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-exynos4/mach-universal_c210.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-exynos4/mach-universal_c210.c')
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c771
1 files changed, 771 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
new file mode 100644
index 00000000000..b3b5d891100
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -0,0 +1,771 @@
1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/mfd/max8998.h>
17#include <linux/regulator/machine.h>
18#include <linux/regulator/fixed.h>
19#include <linux/regulator/max8952.h>
20#include <linux/mmc/host.h>
21#include <linux/i2c-gpio.h>
22#include <linux/i2c/mcs.h>
23#include <linux/i2c/atmel_mxt_ts.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach-types.h>
27
28#include <plat/regs-serial.h>
29#include <plat/exynos4.h>
30#include <plat/cpu.h>
31#include <plat/devs.h>
32#include <plat/iic.h>
33#include <plat/gpio-cfg.h>
34#include <plat/mfc.h>
35#include <plat/sdhci.h>
36#include <plat/pd.h>
37
38#include <mach/map.h>
39
40/* Following are default values for UCON, ULCON and UFCON UART registers */
41#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
42 S3C2410_UCON_RXILEVEL | \
43 S3C2410_UCON_TXIRQMODE | \
44 S3C2410_UCON_RXIRQMODE | \
45 S3C2410_UCON_RXFIFO_TOI | \
46 S3C2443_UCON_RXERR_IRQEN)
47
48#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
49
50#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
51 S5PV210_UFCON_TXTRIG256 | \
52 S5PV210_UFCON_RXTRIG256)
53
54static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
55 [0] = {
56 .hwport = 0,
57 .ucon = UNIVERSAL_UCON_DEFAULT,
58 .ulcon = UNIVERSAL_ULCON_DEFAULT,
59 .ufcon = UNIVERSAL_UFCON_DEFAULT,
60 },
61 [1] = {
62 .hwport = 1,
63 .ucon = UNIVERSAL_UCON_DEFAULT,
64 .ulcon = UNIVERSAL_ULCON_DEFAULT,
65 .ufcon = UNIVERSAL_UFCON_DEFAULT,
66 },
67 [2] = {
68 .hwport = 2,
69 .ucon = UNIVERSAL_UCON_DEFAULT,
70 .ulcon = UNIVERSAL_ULCON_DEFAULT,
71 .ufcon = UNIVERSAL_UFCON_DEFAULT,
72 },
73 [3] = {
74 .hwport = 3,
75 .ucon = UNIVERSAL_UCON_DEFAULT,
76 .ulcon = UNIVERSAL_ULCON_DEFAULT,
77 .ufcon = UNIVERSAL_UFCON_DEFAULT,
78 },
79};
80
81static struct regulator_consumer_supply max8952_consumer =
82 REGULATOR_SUPPLY("vdd_arm", NULL);
83
84static struct max8952_platform_data universal_max8952_pdata __initdata = {
85 .gpio_vid0 = EXYNOS4_GPX0(3),
86 .gpio_vid1 = EXYNOS4_GPX0(4),
87 .gpio_en = -1, /* Not controllable, set "Always High" */
88 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
89 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
90 .sync_freq = 0, /* default: fastest */
91 .ramp_speed = 0, /* default: fastest */
92
93 .reg_data = {
94 .constraints = {
95 .name = "VARM_1.2V",
96 .min_uV = 770000,
97 .max_uV = 1400000,
98 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
99 .always_on = 1,
100 .boot_on = 1,
101 },
102 .num_consumer_supplies = 1,
103 .consumer_supplies = &max8952_consumer,
104 },
105};
106
107static struct regulator_consumer_supply lp3974_buck1_consumer =
108 REGULATOR_SUPPLY("vdd_int", NULL);
109
110static struct regulator_consumer_supply lp3974_buck2_consumer =
111 REGULATOR_SUPPLY("vddg3d", NULL);
112
113static struct regulator_init_data lp3974_buck1_data = {
114 .constraints = {
115 .name = "VINT_1.1V",
116 .min_uV = 750000,
117 .max_uV = 1500000,
118 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
119 REGULATOR_CHANGE_STATUS,
120 .boot_on = 1,
121 .state_mem = {
122 .disabled = 1,
123 },
124 },
125 .num_consumer_supplies = 1,
126 .consumer_supplies = &lp3974_buck1_consumer,
127};
128
129static struct regulator_init_data lp3974_buck2_data = {
130 .constraints = {
131 .name = "VG3D_1.1V",
132 .min_uV = 750000,
133 .max_uV = 1500000,
134 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
135 REGULATOR_CHANGE_STATUS,
136 .boot_on = 1,
137 .state_mem = {
138 .disabled = 1,
139 },
140 },
141 .num_consumer_supplies = 1,
142 .consumer_supplies = &lp3974_buck2_consumer,
143};
144
145static struct regulator_init_data lp3974_buck3_data = {
146 .constraints = {
147 .name = "VCC_1.8V",
148 .min_uV = 1800000,
149 .max_uV = 1800000,
150 .apply_uV = 1,
151 .always_on = 1,
152 .state_mem = {
153 .enabled = 1,
154 },
155 },
156};
157
158static struct regulator_init_data lp3974_buck4_data = {
159 .constraints = {
160 .name = "VMEM_1.2V",
161 .min_uV = 1200000,
162 .max_uV = 1200000,
163 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
164 .apply_uV = 1,
165 .state_mem = {
166 .disabled = 1,
167 },
168 },
169};
170
171static struct regulator_init_data lp3974_ldo2_data = {
172 .constraints = {
173 .name = "VALIVE_1.2V",
174 .min_uV = 1200000,
175 .max_uV = 1200000,
176 .apply_uV = 1,
177 .always_on = 1,
178 .state_mem = {
179 .enabled = 1,
180 },
181 },
182};
183
184static struct regulator_init_data lp3974_ldo3_data = {
185 .constraints = {
186 .name = "VUSB+MIPI_1.1V",
187 .min_uV = 1100000,
188 .max_uV = 1100000,
189 .apply_uV = 1,
190 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
191 .state_mem = {
192 .disabled = 1,
193 },
194 },
195};
196
197static struct regulator_init_data lp3974_ldo4_data = {
198 .constraints = {
199 .name = "VADC_3.3V",
200 .min_uV = 3300000,
201 .max_uV = 3300000,
202 .apply_uV = 1,
203 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
204 .state_mem = {
205 .disabled = 1,
206 },
207 },
208};
209
210static struct regulator_init_data lp3974_ldo5_data = {
211 .constraints = {
212 .name = "VTF_2.8V",
213 .min_uV = 2800000,
214 .max_uV = 2800000,
215 .apply_uV = 1,
216 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
217 .state_mem = {
218 .disabled = 1,
219 },
220 },
221};
222
223static struct regulator_init_data lp3974_ldo6_data = {
224 .constraints = {
225 .name = "LDO6",
226 .min_uV = 2000000,
227 .max_uV = 2000000,
228 .apply_uV = 1,
229 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
230 .state_mem = {
231 .disabled = 1,
232 },
233 },
234};
235
236static struct regulator_init_data lp3974_ldo7_data = {
237 .constraints = {
238 .name = "VLCD+VMIPI_1.8V",
239 .min_uV = 1800000,
240 .max_uV = 1800000,
241 .apply_uV = 1,
242 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
243 .state_mem = {
244 .disabled = 1,
245 },
246 },
247};
248
249static struct regulator_init_data lp3974_ldo8_data = {
250 .constraints = {
251 .name = "VUSB+VDAC_3.3V",
252 .min_uV = 3300000,
253 .max_uV = 3300000,
254 .apply_uV = 1,
255 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
256 .state_mem = {
257 .disabled = 1,
258 },
259 },
260};
261
262static struct regulator_init_data lp3974_ldo9_data = {
263 .constraints = {
264 .name = "VCC_2.8V",
265 .min_uV = 2800000,
266 .max_uV = 2800000,
267 .apply_uV = 1,
268 .always_on = 1,
269 .state_mem = {
270 .enabled = 1,
271 },
272 },
273};
274
275static struct regulator_init_data lp3974_ldo10_data = {
276 .constraints = {
277 .name = "VPLL_1.1V",
278 .min_uV = 1100000,
279 .max_uV = 1100000,
280 .boot_on = 1,
281 .apply_uV = 1,
282 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
283 .state_mem = {
284 .disabled = 1,
285 },
286 },
287};
288
289static struct regulator_init_data lp3974_ldo11_data = {
290 .constraints = {
291 .name = "CAM_AF_3.3V",
292 .min_uV = 3300000,
293 .max_uV = 3300000,
294 .apply_uV = 1,
295 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
296 .state_mem = {
297 .disabled = 1,
298 },
299 },
300};
301
302static struct regulator_init_data lp3974_ldo12_data = {
303 .constraints = {
304 .name = "PS_2.8V",
305 .min_uV = 2800000,
306 .max_uV = 2800000,
307 .apply_uV = 1,
308 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
309 .state_mem = {
310 .disabled = 1,
311 },
312 },
313};
314
315static struct regulator_init_data lp3974_ldo13_data = {
316 .constraints = {
317 .name = "VHIC_1.2V",
318 .min_uV = 1200000,
319 .max_uV = 1200000,
320 .apply_uV = 1,
321 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
322 .state_mem = {
323 .disabled = 1,
324 },
325 },
326};
327
328static struct regulator_init_data lp3974_ldo14_data = {
329 .constraints = {
330 .name = "CAM_I_HOST_1.8V",
331 .min_uV = 1800000,
332 .max_uV = 1800000,
333 .apply_uV = 1,
334 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
335 .state_mem = {
336 .disabled = 1,
337 },
338 },
339};
340
341static struct regulator_init_data lp3974_ldo15_data = {
342 .constraints = {
343 .name = "CAM_S_DIG+FM33_CORE_1.2V",
344 .min_uV = 1200000,
345 .max_uV = 1200000,
346 .apply_uV = 1,
347 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
348 .state_mem = {
349 .disabled = 1,
350 },
351 },
352};
353
354static struct regulator_init_data lp3974_ldo16_data = {
355 .constraints = {
356 .name = "CAM_S_ANA_2.8V",
357 .min_uV = 2800000,
358 .max_uV = 2800000,
359 .apply_uV = 1,
360 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
361 .state_mem = {
362 .disabled = 1,
363 },
364 },
365};
366
367static struct regulator_init_data lp3974_ldo17_data = {
368 .constraints = {
369 .name = "VCC_3.0V_LCD",
370 .min_uV = 3000000,
371 .max_uV = 3000000,
372 .apply_uV = 1,
373 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
374 .boot_on = 1,
375 .state_mem = {
376 .disabled = 1,
377 },
378 },
379};
380
381static struct regulator_init_data lp3974_32khz_ap_data = {
382 .constraints = {
383 .name = "32KHz AP",
384 .always_on = 1,
385 .state_mem = {
386 .enabled = 1,
387 },
388 },
389};
390
391static struct regulator_init_data lp3974_32khz_cp_data = {
392 .constraints = {
393 .name = "32KHz CP",
394 .state_mem = {
395 .disabled = 1,
396 },
397 },
398};
399
400static struct regulator_init_data lp3974_vichg_data = {
401 .constraints = {
402 .name = "VICHG",
403 .state_mem = {
404 .disabled = 1,
405 },
406 },
407};
408
409static struct regulator_init_data lp3974_esafeout1_data = {
410 .constraints = {
411 .name = "SAFEOUT1",
412 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
413 .state_mem = {
414 .enabled = 1,
415 },
416 },
417};
418
419static struct regulator_init_data lp3974_esafeout2_data = {
420 .constraints = {
421 .name = "SAFEOUT2",
422 .boot_on = 1,
423 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
424 .state_mem = {
425 .enabled = 1,
426 },
427 },
428};
429
430static struct max8998_regulator_data lp3974_regulators[] = {
431 { MAX8998_LDO2, &lp3974_ldo2_data },
432 { MAX8998_LDO3, &lp3974_ldo3_data },
433 { MAX8998_LDO4, &lp3974_ldo4_data },
434 { MAX8998_LDO5, &lp3974_ldo5_data },
435 { MAX8998_LDO6, &lp3974_ldo6_data },
436 { MAX8998_LDO7, &lp3974_ldo7_data },
437 { MAX8998_LDO8, &lp3974_ldo8_data },
438 { MAX8998_LDO9, &lp3974_ldo9_data },
439 { MAX8998_LDO10, &lp3974_ldo10_data },
440 { MAX8998_LDO11, &lp3974_ldo11_data },
441 { MAX8998_LDO12, &lp3974_ldo12_data },
442 { MAX8998_LDO13, &lp3974_ldo13_data },
443 { MAX8998_LDO14, &lp3974_ldo14_data },
444 { MAX8998_LDO15, &lp3974_ldo15_data },
445 { MAX8998_LDO16, &lp3974_ldo16_data },
446 { MAX8998_LDO17, &lp3974_ldo17_data },
447 { MAX8998_BUCK1, &lp3974_buck1_data },
448 { MAX8998_BUCK2, &lp3974_buck2_data },
449 { MAX8998_BUCK3, &lp3974_buck3_data },
450 { MAX8998_BUCK4, &lp3974_buck4_data },
451 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
452 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
453 { MAX8998_ENVICHG, &lp3974_vichg_data },
454 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
455 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
456};
457
458static struct max8998_platform_data universal_lp3974_pdata = {
459 .num_regulators = ARRAY_SIZE(lp3974_regulators),
460 .regulators = lp3974_regulators,
461 .buck1_voltage1 = 1100000, /* INT */
462 .buck1_voltage2 = 1000000,
463 .buck1_voltage3 = 1100000,
464 .buck1_voltage4 = 1000000,
465 .buck1_set1 = EXYNOS4_GPX0(5),
466 .buck1_set2 = EXYNOS4_GPX0(6),
467 .buck2_voltage1 = 1200000, /* G3D */
468 .buck2_voltage2 = 1100000,
469 .buck1_default_idx = 0,
470 .buck2_set3 = EXYNOS4_GPE2(0),
471 .buck2_default_idx = 0,
472 .wakeup = true,
473};
474
475/* GPIO I2C 5 (PMIC) */
476static struct i2c_board_info i2c5_devs[] __initdata = {
477 {
478 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
479 .platform_data = &universal_max8952_pdata,
480 }, {
481 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
482 .platform_data = &universal_lp3974_pdata,
483 },
484};
485
486/* I2C3 (TSP) */
487static struct mxt_platform_data qt602240_platform_data = {
488 .x_line = 19,
489 .y_line = 11,
490 .x_size = 800,
491 .y_size = 480,
492 .blen = 0x11,
493 .threshold = 0x28,
494 .voltage = 2800000, /* 2.8V */
495 .orient = MXT_DIAGONAL,
496};
497
498static struct i2c_board_info i2c3_devs[] __initdata = {
499 {
500 I2C_BOARD_INFO("qt602240_ts", 0x4a),
501 .platform_data = &qt602240_platform_data,
502 },
503};
504
505static void __init universal_tsp_init(void)
506{
507 int gpio;
508
509 /* TSP_LDO_ON: XMDMADDR_11 */
510 gpio = EXYNOS4_GPE2(3);
511 gpio_request(gpio, "TSP_LDO_ON");
512 gpio_direction_output(gpio, 1);
513 gpio_export(gpio, 0);
514
515 /* TSP_INT: XMDMADDR_7 */
516 gpio = EXYNOS4_GPE1(7);
517 gpio_request(gpio, "TSP_INT");
518
519 s5p_register_gpio_interrupt(gpio);
520 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
521 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
522 i2c3_devs[0].irq = gpio_to_irq(gpio);
523}
524
525
526/* GPIO I2C 12 (3 Touchkey) */
527static uint32_t touchkey_keymap[] = {
528 /* MCS_KEY_MAP(value, keycode) */
529 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
530 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
531};
532
533static struct mcs_platform_data touchkey_data = {
534 .keymap = touchkey_keymap,
535 .keymap_size = ARRAY_SIZE(touchkey_keymap),
536 .key_maxval = 2,
537};
538
539/* GPIO I2C 3_TOUCH 2.8V */
540#define I2C_GPIO_BUS_12 12
541static struct i2c_gpio_platform_data i2c_gpio12_data = {
542 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
543 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
544};
545
546static struct platform_device i2c_gpio12 = {
547 .name = "i2c-gpio",
548 .id = I2C_GPIO_BUS_12,
549 .dev = {
550 .platform_data = &i2c_gpio12_data,
551 },
552};
553
554static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
555 {
556 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
557 .platform_data = &touchkey_data,
558 },
559};
560
561static void __init universal_touchkey_init(void)
562{
563 int gpio;
564
565 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
566 gpio_request(gpio, "3_TOUCH_INT");
567 s5p_register_gpio_interrupt(gpio);
568 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
569 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
570
571 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
572 gpio_request(gpio, "3_TOUCH_EN");
573 gpio_direction_output(gpio, 1);
574}
575
576/* GPIO KEYS */
577static struct gpio_keys_button universal_gpio_keys_tables[] = {
578 {
579 .code = KEY_VOLUMEUP,
580 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
581 .desc = "gpio-keys: KEY_VOLUMEUP",
582 .type = EV_KEY,
583 .active_low = 1,
584 .debounce_interval = 1,
585 }, {
586 .code = KEY_VOLUMEDOWN,
587 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
588 .desc = "gpio-keys: KEY_VOLUMEDOWN",
589 .type = EV_KEY,
590 .active_low = 1,
591 .debounce_interval = 1,
592 }, {
593 .code = KEY_CONFIG,
594 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
595 .desc = "gpio-keys: KEY_CONFIG",
596 .type = EV_KEY,
597 .active_low = 1,
598 .debounce_interval = 1,
599 }, {
600 .code = KEY_CAMERA,
601 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
602 .desc = "gpio-keys: KEY_CAMERA",
603 .type = EV_KEY,
604 .active_low = 1,
605 .debounce_interval = 1,
606 }, {
607 .code = KEY_OK,
608 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
609 .desc = "gpio-keys: KEY_OK",
610 .type = EV_KEY,
611 .active_low = 1,
612 .debounce_interval = 1,
613 },
614};
615
616static struct gpio_keys_platform_data universal_gpio_keys_data = {
617 .buttons = universal_gpio_keys_tables,
618 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
619};
620
621static struct platform_device universal_gpio_keys = {
622 .name = "gpio-keys",
623 .dev = {
624 .platform_data = &universal_gpio_keys_data,
625 },
626};
627
628/* eMMC */
629static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
630 .max_width = 8,
631 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
632 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
633 MMC_CAP_DISABLE),
634 .cd_type = S3C_SDHCI_CD_PERMANENT,
635 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
636};
637
638static struct regulator_consumer_supply mmc0_supplies[] = {
639 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
640};
641
642static struct regulator_init_data mmc0_fixed_voltage_init_data = {
643 .constraints = {
644 .name = "VMEM_VDD_2.8V",
645 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
646 },
647 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
648 .consumer_supplies = mmc0_supplies,
649};
650
651static struct fixed_voltage_config mmc0_fixed_voltage_config = {
652 .supply_name = "MASSMEMORY_EN",
653 .microvolts = 2800000,
654 .gpio = EXYNOS4_GPE1(3),
655 .enable_high = true,
656 .init_data = &mmc0_fixed_voltage_init_data,
657};
658
659static struct platform_device mmc0_fixed_voltage = {
660 .name = "reg-fixed-voltage",
661 .id = 0,
662 .dev = {
663 .platform_data = &mmc0_fixed_voltage_config,
664 },
665};
666
667/* SD */
668static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
669 .max_width = 4,
670 .host_caps = MMC_CAP_4_BIT_DATA |
671 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
672 MMC_CAP_DISABLE,
673 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
674 .ext_cd_gpio_invert = 1,
675 .cd_type = S3C_SDHCI_CD_GPIO,
676 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
677};
678
679/* WiFi */
680static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
681 .max_width = 4,
682 .host_caps = MMC_CAP_4_BIT_DATA |
683 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
684 MMC_CAP_DISABLE,
685 .cd_type = S3C_SDHCI_CD_EXTERNAL,
686};
687
688static void __init universal_sdhci_init(void)
689{
690 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
691 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
692 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
693}
694
695/* I2C0 */
696static struct i2c_board_info i2c0_devs[] __initdata = {
697 /* Camera, To be updated */
698};
699
700/* I2C1 */
701static struct i2c_board_info i2c1_devs[] __initdata = {
702 /* Gyro, To be updated */
703};
704
705static struct platform_device *universal_devices[] __initdata = {
706 /* Samsung Platform Devices */
707 &s5p_device_fimc0,
708 &s5p_device_fimc1,
709 &s5p_device_fimc2,
710 &s5p_device_fimc3,
711 &mmc0_fixed_voltage,
712 &s3c_device_hsmmc0,
713 &s3c_device_hsmmc2,
714 &s3c_device_hsmmc3,
715 &s3c_device_i2c3,
716 &s3c_device_i2c5,
717
718 /* Universal Devices */
719 &i2c_gpio12,
720 &universal_gpio_keys,
721 &s5p_device_onenand,
722 &s5p_device_mfc,
723 &s5p_device_mfc_l,
724 &s5p_device_mfc_r,
725 &exynos4_device_pd[PD_MFC],
726};
727
728static void __init universal_map_io(void)
729{
730 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
731 s3c24xx_init_clocks(24000000);
732 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
733}
734
735static void __init universal_reserve(void)
736{
737 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
738}
739
740static void __init universal_machine_init(void)
741{
742 universal_sdhci_init();
743
744 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
745 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
746
747 universal_tsp_init();
748 s3c_i2c3_set_platdata(NULL);
749 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
750
751 s3c_i2c5_set_platdata(NULL);
752 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
753
754 universal_touchkey_init();
755 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
756 ARRAY_SIZE(i2c_gpio12_devs));
757
758 /* Last */
759 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
760 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
761}
762
763MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
764 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
765 .boot_params = S5P_PA_SDRAM + 0x100,
766 .init_irq = exynos4_init_irq,
767 .map_io = universal_map_io,
768 .init_machine = universal_machine_init,
769 .timer = &exynos4_timer,
770 .reserve = &universal_reserve,
771MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 02:52:32 -0400