Patched in Tegra support.

6 files changed, 214 insertions, 128 deletions

diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
index af54e43132c..b25bc907636 100644
--- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  */
 #include <mach/ep93xx-regs.h>
 
-                .macro  addruart, rp, rv, tmp
+                .macro  addruart, rp, rv
                 ldr     \rp, =EP93XX_APB_PHYS_BASE      @ Physical base
                 ldr     \rv, =EP93XX_APB_VIRT_BASE      @ virtual base
                 orr     \rp, \rp, #0x000c0000
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c64d7424660..c4a7b84ef06 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,6 +6,40 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
+ * EP93xx Physical Memory Map:
+ *
+ * The ASDO pin is sampled at system reset to select a synchronous or
+ * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
+ * the synchronous boot mode is selected.  When ASDO is "0" (i.e
+ * pulled-down) the asynchronous boot mode is selected.
+ *
+ * In synchronous boot mode nSDCE3 is decoded starting at physical address
+ * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
+ * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
+ * decoded at 0xf0000000.
+ *
+ * There is known errata for the EP93xx dealing with External Memory
+ * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
+ * Guidelines" for more information.  This document can be found at:
+ *
+ *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
+ */
+
+#define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
+#define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
+#define EP93XX_CS1_PHYS_BASE            0x10000000
+#define EP93XX_CS2_PHYS_BASE            0x20000000
+#define EP93XX_CS3_PHYS_BASE            0x30000000
+#define EP93XX_PCMCIA_PHYS_BASE         0x40000000
+#define EP93XX_CS6_PHYS_BASE            0x60000000
+#define EP93XX_CS7_PHYS_BASE            0x70000000
+#define EP93XX_SDCE0_PHYS_BASE          0xc0000000
+#define EP93XX_SDCE1_PHYS_BASE          0xd0000000
+#define EP93XX_SDCE2_PHYS_BASE          0xe0000000
+#define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
+#define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
+
+/*
  * EP93xx linux memory map:
  *
  * virt         phys            size
@@ -28,7 +62,58 @@
 #define EP93XX_APB_PHYS(x)              (EP93XX_APB_PHYS_BASE + (x))
 #define EP93XX_APB_IOMEM(x)             IOMEM(EP93XX_APB_VIRT_BASE + (x))
 
-/* APB UARTs */
+
+/* AHB peripherals */
+#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
+
+#define EP93XX_ETHERNET_PHYS_BASE       EP93XX_AHB_PHYS(0x00010000)
+#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
+
+#define EP93XX_USB_PHYS_BASE            EP93XX_AHB_PHYS(0x00020000)
+#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
+
+#define EP93XX_RASTER_PHYS_BASE         EP93XX_AHB_PHYS(0x00030000)
+#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
+
+#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
+
+#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
+
+#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
+
+#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
+
+#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
+
+#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
+
+#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
+
+
+/* APB peripherals */
+#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
+
+#define EP93XX_I2S_PHYS_BASE            EP93XX_APB_PHYS(0x00020000)
+#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
+
+#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
+
+#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
+#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
+#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
+#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
+#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
+#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
+#define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
+
+#define EP93XX_AAC_PHYS_BASE            EP93XX_APB_PHYS(0x00080000)
+#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
+
+#define EP93XX_SPI_PHYS_BASE            EP93XX_APB_PHYS(0x000a0000)
+#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
+
+#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
+
 #define EP93XX_UART1_PHYS_BASE          EP93XX_APB_PHYS(0x000c0000)
 #define EP93XX_UART1_BASE               EP93XX_APB_IOMEM(0x000c0000)
 
@@ -38,4 +123,108 @@
 #define EP93XX_UART3_PHYS_BASE          EP93XX_APB_PHYS(0x000e0000)
 #define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
 
+#define EP93XX_KEY_MATRIX_PHYS_BASE     EP93XX_APB_PHYS(0x000f0000)
+#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
+
+#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
+
+#define EP93XX_PWM_PHYS_BASE            EP93XX_APB_PHYS(0x00110000)
+#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
+
+#define EP93XX_RTC_PHYS_BASE            EP93XX_APB_PHYS(0x00120000)
+#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
+
+#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
+#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
+#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
+#define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
+#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
+#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
+#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
+#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
+#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
+#define EP93XX_SYSCON_VIDCLKDIV         EP93XX_SYSCON_REG(0x84)
+#define EP93XX_SYSCON_CLKDIV_ENABLE     (1<<15)
+#define EP93XX_SYSCON_CLKDIV_ESEL       (1<<14)
+#define EP93XX_SYSCON_CLKDIV_PSEL       (1<<13)
+#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
+#define EP93XX_SYSCON_I2SCLKDIV         EP93XX_SYSCON_REG(0x8c)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA    (1<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL    (1<<19)
+#define EP93XX_I2SCLKDIV_SDIV           (1 << 16)
+#define EP93XX_I2SCLKDIV_LRDIV32        (0 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV64        (1 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV128       (2 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV_MASK     (3 << 17)
+#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_SYSCFG            EP93XX_SYSCON_REG(0x9c)
+#define EP93XX_SYSCON_SYSCFG_REV_MASK   (0xf0000000)
+#define EP93XX_SYSCON_SYSCFG_REV_SHIFT  (28)
+#define EP93XX_SYSCON_SYSCFG_SBOOT      (1<<8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7      (1<<7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6      (1<<6)
+#define EP93XX_SYSCON_SYSCFG_LASDO      (1<<5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA      (1<<4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK     (1<<3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2      (1<<1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1      (1<<0)
+#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
+
+#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
+
+
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
deleted file mode 100644
index 6d7c571a519..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* Include file for the EP93XX GPIO controller machine specifics */
-
-#ifndef __GPIO_EP93XX_H
-#define __GPIO_EP93XX_H
-
-#include <mach/ep93xx-regs.h>
-
-#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
-#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
-#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
-#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
-#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
-#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
-#define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
-
-/* GPIO port A.  */
-#define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
-#define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
-#define EP93XX_GPIO_LINE_EGPIO1         EP93XX_GPIO_LINE_A(1)
-#define EP93XX_GPIO_LINE_EGPIO2         EP93XX_GPIO_LINE_A(2)
-#define EP93XX_GPIO_LINE_EGPIO3         EP93XX_GPIO_LINE_A(3)
-#define EP93XX_GPIO_LINE_EGPIO4         EP93XX_GPIO_LINE_A(4)
-#define EP93XX_GPIO_LINE_EGPIO5         EP93XX_GPIO_LINE_A(5)
-#define EP93XX_GPIO_LINE_EGPIO6         EP93XX_GPIO_LINE_A(6)
-#define EP93XX_GPIO_LINE_EGPIO7         EP93XX_GPIO_LINE_A(7)
-
-/* GPIO port B.  */
-#define EP93XX_GPIO_LINE_B(x)           ((x) + 8)
-#define EP93XX_GPIO_LINE_EGPIO8         EP93XX_GPIO_LINE_B(0)
-#define EP93XX_GPIO_LINE_EGPIO9         EP93XX_GPIO_LINE_B(1)
-#define EP93XX_GPIO_LINE_EGPIO10        EP93XX_GPIO_LINE_B(2)
-#define EP93XX_GPIO_LINE_EGPIO11        EP93XX_GPIO_LINE_B(3)
-#define EP93XX_GPIO_LINE_EGPIO12        EP93XX_GPIO_LINE_B(4)
-#define EP93XX_GPIO_LINE_EGPIO13        EP93XX_GPIO_LINE_B(5)
-#define EP93XX_GPIO_LINE_EGPIO14        EP93XX_GPIO_LINE_B(6)
-#define EP93XX_GPIO_LINE_EGPIO15        EP93XX_GPIO_LINE_B(7)
-
-/* GPIO port C.  */
-#define EP93XX_GPIO_LINE_C(x)           ((x) + 40)
-#define EP93XX_GPIO_LINE_ROW0           EP93XX_GPIO_LINE_C(0)
-#define EP93XX_GPIO_LINE_ROW1           EP93XX_GPIO_LINE_C(1)
-#define EP93XX_GPIO_LINE_ROW2           EP93XX_GPIO_LINE_C(2)
-#define EP93XX_GPIO_LINE_ROW3           EP93XX_GPIO_LINE_C(3)
-#define EP93XX_GPIO_LINE_ROW4           EP93XX_GPIO_LINE_C(4)
-#define EP93XX_GPIO_LINE_ROW5           EP93XX_GPIO_LINE_C(5)
-#define EP93XX_GPIO_LINE_ROW6           EP93XX_GPIO_LINE_C(6)
-#define EP93XX_GPIO_LINE_ROW7           EP93XX_GPIO_LINE_C(7)
-
-/* GPIO port D.  */
-#define EP93XX_GPIO_LINE_D(x)           ((x) + 24)
-#define EP93XX_GPIO_LINE_COL0           EP93XX_GPIO_LINE_D(0)
-#define EP93XX_GPIO_LINE_COL1           EP93XX_GPIO_LINE_D(1)
-#define EP93XX_GPIO_LINE_COL2           EP93XX_GPIO_LINE_D(2)
-#define EP93XX_GPIO_LINE_COL3           EP93XX_GPIO_LINE_D(3)
-#define EP93XX_GPIO_LINE_COL4           EP93XX_GPIO_LINE_D(4)
-#define EP93XX_GPIO_LINE_COL5           EP93XX_GPIO_LINE_D(5)
-#define EP93XX_GPIO_LINE_COL6           EP93XX_GPIO_LINE_D(6)
-#define EP93XX_GPIO_LINE_COL7           EP93XX_GPIO_LINE_D(7)
-
-/* GPIO port E.  */
-#define EP93XX_GPIO_LINE_E(x)           ((x) + 32)
-#define EP93XX_GPIO_LINE_GRLED          EP93XX_GPIO_LINE_E(0)
-#define EP93XX_GPIO_LINE_RDLED          EP93XX_GPIO_LINE_E(1)
-#define EP93XX_GPIO_LINE_DIORn          EP93XX_GPIO_LINE_E(2)
-#define EP93XX_GPIO_LINE_IDECS1n        EP93XX_GPIO_LINE_E(3)
-#define EP93XX_GPIO_LINE_IDECS2n        EP93XX_GPIO_LINE_E(4)
-#define EP93XX_GPIO_LINE_IDEDA0         EP93XX_GPIO_LINE_E(5)
-#define EP93XX_GPIO_LINE_IDEDA1         EP93XX_GPIO_LINE_E(6)
-#define EP93XX_GPIO_LINE_IDEDA2         EP93XX_GPIO_LINE_E(7)
-
-/* GPIO port F.  */
-#define EP93XX_GPIO_LINE_F(x)           ((x) + 16)
-#define EP93XX_GPIO_LINE_WP             EP93XX_GPIO_LINE_F(0)
-#define EP93XX_GPIO_LINE_MCCD1          EP93XX_GPIO_LINE_F(1)
-#define EP93XX_GPIO_LINE_MCCD2          EP93XX_GPIO_LINE_F(2)
-#define EP93XX_GPIO_LINE_MCBVD1         EP93XX_GPIO_LINE_F(3)
-#define EP93XX_GPIO_LINE_MCBVD2         EP93XX_GPIO_LINE_F(4)
-#define EP93XX_GPIO_LINE_VS1            EP93XX_GPIO_LINE_F(5)
-#define EP93XX_GPIO_LINE_READY          EP93XX_GPIO_LINE_F(6)
-#define EP93XX_GPIO_LINE_VS2            EP93XX_GPIO_LINE_F(7)
-
-/* GPIO port G.  */
-#define EP93XX_GPIO_LINE_G(x)           ((x) + 48)
-#define EP93XX_GPIO_LINE_EECLK          EP93XX_GPIO_LINE_G(0)
-#define EP93XX_GPIO_LINE_EEDAT          EP93XX_GPIO_LINE_G(1)
-#define EP93XX_GPIO_LINE_SLA0           EP93XX_GPIO_LINE_G(2)
-#define EP93XX_GPIO_LINE_SLA1           EP93XX_GPIO_LINE_G(3)
-#define EP93XX_GPIO_LINE_DD12           EP93XX_GPIO_LINE_G(4)
-#define EP93XX_GPIO_LINE_DD13           EP93XX_GPIO_LINE_G(5)
-#define EP93XX_GPIO_LINE_DD14           EP93XX_GPIO_LINE_G(6)
-#define EP93XX_GPIO_LINE_DD15           EP93XX_GPIO_LINE_G(7)
-
-/* GPIO port H.  */
-#define EP93XX_GPIO_LINE_H(x)           ((x) + 56)
-#define EP93XX_GPIO_LINE_DD0            EP93XX_GPIO_LINE_H(0)
-#define EP93XX_GPIO_LINE_DD1            EP93XX_GPIO_LINE_H(1)
-#define EP93XX_GPIO_LINE_DD2            EP93XX_GPIO_LINE_H(2)
-#define EP93XX_GPIO_LINE_DD3            EP93XX_GPIO_LINE_H(3)
-#define EP93XX_GPIO_LINE_DD4            EP93XX_GPIO_LINE_H(4)
-#define EP93XX_GPIO_LINE_DD5            EP93XX_GPIO_LINE_H(5)
-#define EP93XX_GPIO_LINE_DD6            EP93XX_GPIO_LINE_H(6)
-#define EP93XX_GPIO_LINE_DD7            EP93XX_GPIO_LINE_H(7)
-
-/* maximum value for gpio line identifiers */
-#define EP93XX_GPIO_LINE_MAX            EP93XX_GPIO_LINE_H(7)
-
-/* maximum value for irq capable line identifiers */
-#define EP93XX_GPIO_LINE_MAX_IRQ        EP93XX_GPIO_LINE_F(7)
-
-#endif /* __GPIO_EP93XX_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index efcd47815a9..4df842897ea 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -5,6 +5,7 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
+#include <mach/ep93xx-regs.h>
 #include <mach/platform.h>
 
 /*
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 33a5122c6dc..50660455b1d 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -21,6 +21,20 @@ struct ep93xx_eth_data
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 
+/* EP93xx System Controller software locked register write */
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
+
+static inline void ep93xx_devcfg_set_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(bits, 0x00);
+}
+
+static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(0x00, bits);
+}
+
 #define EP93XX_CHIP_REV_D0      3
 #define EP93XX_CHIP_REV_D1      4
 #define EP93XX_CHIP_REV_E0      5
@@ -45,23 +59,11 @@ void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
 void ep93xx_keypad_release_gpio(struct platform_device *pdev);
 void ep93xx_register_i2s(void);
-int ep93xx_i2s_acquire(void);
+int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config);
 void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
-void ep93xx_register_ide(void);
-int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
-void ep93xx_ide_release_gpio(struct platform_device *pdev);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
 
-void ep93xx_restart(char, const char *);
-void ep93xx_init_late(void);
-
-#ifdef CONFIG_CRUNCH
-int crunch_init(void);
-#else
-static inline int crunch_init(void) { return 0; }
-#endif
-
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d64274fc576..16026c2b1c8 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
 
 static inline void putc(int c)
 {
-        /* Transmit fifo not full?  */
-        while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)
-                ;
+        int i;
+
+        for (i = 0; i < 1000; i++) {
+                /* Transmit fifo not full?  */
+                if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
+                        break;
+        }
 
         __raw_writeb(c, PHYS_UART_DATA);
 }