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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/arm/mach-dove
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/arm/mach-dove')
-rw-r--r--arch/arm/mach-dove/Kconfig9
-rw-r--r--arch/arm/mach-dove/Makefile4
-rw-r--r--arch/arm/mach-dove/Makefile.boot2
-rw-r--r--arch/arm/mach-dove/addr-map.c122
-rw-r--r--arch/arm/mach-dove/cm-a510.c3
-rw-r--r--arch/arm/mach-dove/common.c256
-rw-r--r--arch/arm/mach-dove/common.h6
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c4
-rw-r--r--arch/arm/mach-dove/include/mach/bridge-regs.h15
-rw-r--r--arch/arm/mach-dove/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h135
-rw-r--r--arch/arm/mach-dove/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-dove/include/mach/pm.h56
-rw-r--r--arch/arm/mach-dove/irq.c77
-rw-r--r--arch/arm/mach-dove/mpp.c9
-rw-r--r--arch/arm/mach-dove/pcie.c89
16 files changed, 317 insertions, 478 deletions
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 603c5fd99e8..dd937c526a4 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,15 +15,6 @@ config MACH_CM_A510
15 Say 'Y' here if you want your kernel to support the 15 Say 'Y' here if you want your kernel to support the
16 CompuLab CM-A510 Board. 16 CompuLab CM-A510 Board.
17 17
18config MACH_DOVE_DT
19 bool "Marvell Dove Flattened Device Tree"
20 select MVEBU_CLK_CORE
21 select MVEBU_CLK_GATING
22 select USE_OF
23 help
24 Say 'Y' here if you want your kernel to support the
25 Marvell Dove using flattened device tree.
26
27endmenu 18endmenu
28 19
29endif 20endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 5e683baf96c..fa0f0185606 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o irq.o mpp.o 1obj-y += common.o addr-map.o irq.o pcie.o mpp.o
2obj-$(CONFIG_PCI) += pcie.o 2
3obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o 3obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
4obj-$(CONFIG_MACH_CM_A510) += cm-a510.o 4obj-$(CONFIG_MACH_CM_A510) += cm-a510.o
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
index 760a0efe758..67039c3e0c4 100644
--- a/arch/arm/mach-dove/Makefile.boot
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -1,3 +1,3 @@
1 zreladdr-y += 0x00008000 1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100 2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000 3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 2a06c016341..00be4fc26dd 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,8 +14,6 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
16#include <asm/setup.h> 16#include <asm/setup.h>
17#include <mach/dove.h>
18#include <plat/addr-map.h>
19#include "common.h" 17#include "common.h"
20 18
21/* 19/*
@@ -36,72 +34,98 @@
36#define ATTR_PCIE_MEM 0xe8 34#define ATTR_PCIE_MEM 0xe8
37#define ATTR_SCRATCHPAD 0x0 35#define ATTR_SCRATCHPAD 0x0
38 36
37/*
38 * CPU Address Decode Windows registers
39 */
40#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
41#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
42#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
43#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
44
45struct mbus_dram_target_info dove_mbus_dram_info;
46
39static inline void __iomem *ddr_map_sc(int i) 47static inline void __iomem *ddr_map_sc(int i)
40{ 48{
41 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); 49 return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
42} 50}
43 51
44/* 52static int cpu_win_can_remap(int win)
45 * Description of the windows needed by the platform code 53{
46 */ 54 if (win < 4)
47static struct __initdata orion_addr_map_cfg addr_map_cfg = { 55 return 1;
48 .num_wins = 8, 56
49 .remappable_wins = 4, 57 return 0;
50 .bridge_virt_base = BRIDGE_VIRT_BASE, 58}
51}; 59
60static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62{
63 u32 ctrl;
64
65 base &= 0xffff0000;
66 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
67
68 writel(base, WIN_BASE(win));
69 writel(ctrl, WIN_CTRL(win));
70 if (cpu_win_can_remap(win)) {
71 if (remap < 0)
72 remap = base;
73 writel(remap & 0xffff0000, WIN_REMAP_LO(win));
74 writel(0, WIN_REMAP_HI(win));
75 }
76}
77
78void __init dove_setup_cpu_mbus(void)
79{
80 int i;
81 int cs;
52 82
53static const struct __initdata orion_addr_map_info addr_map_info[] = {
54 /* 83 /*
55 * Windows for PCIe IO+MEM space. 84 * First, disable and clear windows.
56 */ 85 */
57 { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, 86 for (i = 0; i < 8; i++) {
58 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE 87 writel(0, WIN_BASE(i));
59 }, 88 writel(0, WIN_CTRL(i));
60 { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, 89 if (cpu_win_can_remap(i)) {
61 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE 90 writel(0, WIN_REMAP_LO(i));
62 }, 91 writel(0, WIN_REMAP_HI(i));
63 { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, 92 }
64 TARGET_PCIE0, ATTR_PCIE_MEM, -1 93 }
65 }, 94
66 { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
67 TARGET_PCIE1, ATTR_PCIE_MEM, -1
68 },
69 /* 95 /*
70 * Window for CESA engine. 96 * Setup windows for PCIe IO+MEM space.
71 */ 97 */
72 { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, 98 setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
73 TARGET_CESA, ATTR_CESA, -1 99 TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
74 }, 100 setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
101 TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
102 setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
103 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
104 setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
105 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
106
75 /* 107 /*
76 * Window to the BootROM for Standby and Sleep Resume 108 * Setup window for CESA engine.
77 */ 109 */
78 { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, 110 setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
79 TARGET_BOOTROM, ATTR_BOOTROM, -1 111 TARGET_CESA, ATTR_CESA, -1);
80 }, 112
81 /* 113 /*
82 * Window to the PMU Scratch Pad space 114 * Setup the Window to the BootROM for Standby and Sleep Resume
83 */ 115 */
84 { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, 116 setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
85 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 117 TARGET_BOOTROM, ATTR_BOOTROM, -1);
86 },
87 /* End marker */
88 { -1, 0, 0, 0, 0, 0 }
89};
90
91void __init dove_setup_cpu_mbus(void)
92{
93 int i;
94 int cs;
95 118
96 /* 119 /*
97 * Disable, clear and configure windows. 120 * Setup the Window to the PMU Scratch Pad space
98 */ 121 */
99 orion_config_wins(&addr_map_cfg, addr_map_info); 122 setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
123 TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
100 124
101 /* 125 /*
102 * Setup MBUS dram target info. 126 * Setup MBUS dram target info.
103 */ 127 */
104 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 128 dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
105 129
106 for (i = 0, cs = 0; i < 2; i++) { 130 for (i = 0, cs = 0; i < 2; i++) {
107 u32 map = readl(ddr_map_sc(i)); 131 u32 map = readl(ddr_map_sc(i));
@@ -112,7 +136,7 @@ void __init dove_setup_cpu_mbus(void)
112 if (map & 1) { 136 if (map & 1) {
113 struct mbus_dram_window *w; 137 struct mbus_dram_window *w;
114 138
115 w = &orion_mbus_dram_info.cs[cs++]; 139 w = &dove_mbus_dram_info.cs[cs++];
116 w->cs_index = i; 140 w->cs_index = i;
117 w->mbus_attr = 0; /* CS address decoding done inside */ 141 w->mbus_attr = 0; /* CS address decoding done inside */
118 /* the DDR controller, no need to */ 142 /* the DDR controller, no need to */
@@ -121,5 +145,5 @@ void __init dove_setup_cpu_mbus(void)
121 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); 145 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
122 } 146 }
123 } 147 }
124 orion_mbus_dram_info.num_cs = cs; 148 dove_mbus_dram_info.num_cs = cs;
125} 149}
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 792b4e2e24f..03e11f9dca9 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -87,11 +87,10 @@ static void __init cm_a510_init(void)
87} 87}
88 88
89MACHINE_START(CM_A510, "Compulab CM-A510 Board") 89MACHINE_START(CM_A510, "Compulab CM-A510 Board")
90 .atag_offset = 0x100, 90 .boot_params = 0x00000100,
91 .init_machine = cm_a510_init, 91 .init_machine = cm_a510_init,
92 .map_io = dove_map_io, 92 .map_io = dove_map_io,
93 .init_early = dove_init_early, 93 .init_early = dove_init_early,
94 .init_irq = dove_init_irq, 94 .init_irq = dove_init_irq,
95 .timer = &dove_timer, 95 .timer = &dove_timer,
96 .restart = dove_restart,
97MACHINE_END 96MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 89f4f993cd0..a9e0dae86a2 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -13,12 +13,10 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/clk-provider.h> 16#include <linux/clk.h>
17#include <linux/clk/mvebu.h> 17#include <linux/mbus.h>
18#include <linux/ata_platform.h> 18#include <linux/ata_platform.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <asm/page.h> 20#include <asm/page.h>
23#include <asm/setup.h> 21#include <asm/setup.h>
24#include <asm/timex.h> 22#include <asm/timex.h>
@@ -27,32 +25,39 @@
27#include <asm/mach/time.h> 25#include <asm/mach/time.h>
28#include <asm/mach/pci.h> 26#include <asm/mach/pci.h>
29#include <mach/dove.h> 27#include <mach/dove.h>
30#include <mach/pm.h>
31#include <mach/bridge-regs.h> 28#include <mach/bridge-regs.h>
32#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
33#include <linux/irq.h> 30#include <linux/irq.h>
34#include <plat/time.h> 31#include <plat/time.h>
35#include <linux/platform_data/usb-ehci-orion.h>
36#include <linux/platform_data/dma-mv_xor.h>
37#include <plat/irq.h>
38#include <plat/common.h> 32#include <plat/common.h>
39#include <plat/addr-map.h>
40#include "common.h" 33#include "common.h"
41 34
35static int get_tclk(void);
36
42/***************************************************************************** 37/*****************************************************************************
43 * I/O Address Mapping 38 * I/O Address Mapping
44 ****************************************************************************/ 39 ****************************************************************************/
45static struct map_desc dove_io_desc[] __initdata = { 40static struct map_desc dove_io_desc[] __initdata = {
46 { 41 {
47 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, 42 .virtual = DOVE_SB_REGS_VIRT_BASE,
48 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 43 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
49 .length = DOVE_SB_REGS_SIZE, 44 .length = DOVE_SB_REGS_SIZE,
50 .type = MT_DEVICE, 45 .type = MT_DEVICE,
51 }, { 46 }, {
52 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, 47 .virtual = DOVE_NB_REGS_VIRT_BASE,
53 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 48 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
54 .length = DOVE_NB_REGS_SIZE, 49 .length = DOVE_NB_REGS_SIZE,
55 .type = MT_DEVICE, 50 .type = MT_DEVICE,
51 }, {
52 .virtual = DOVE_PCIE0_IO_VIRT_BASE,
53 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
54 .length = DOVE_PCIE0_IO_SIZE,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = DOVE_PCIE1_IO_VIRT_BASE,
58 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
59 .length = DOVE_PCIE1_IO_SIZE,
60 .type = MT_DEVICE,
56 }, 61 },
57}; 62};
58 63
@@ -62,79 +67,12 @@ void __init dove_map_io(void)
62} 67}
63 68
64/***************************************************************************** 69/*****************************************************************************
65 * CLK tree
66 ****************************************************************************/
67static int dove_tclk;
68
69static DEFINE_SPINLOCK(gating_lock);
70static struct clk *tclk;
71
72static struct clk __init *dove_register_gate(const char *name,
73 const char *parent, u8 bit_idx)
74{
75 return clk_register_gate(NULL, name, parent, 0,
76 (void __iomem *)CLOCK_GATING_CONTROL,
77 bit_idx, 0, &gating_lock);
78}
79
80static void __init dove_clk_init(void)
81{
82 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
83 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
84 struct clk *xor0, *xor1, *ge, *gephy;
85
86 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
87 dove_tclk);
88
89 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
90 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
91 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
92 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
93 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
94 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
95 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
96 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
97 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
98 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
99 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
100 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
101 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
102 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
103 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
104 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
105 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
106 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
107
108 orion_clkdev_add(NULL, "orion_spi.0", tclk);
109 orion_clkdev_add(NULL, "orion_spi.1", tclk);
110 orion_clkdev_add(NULL, "orion_wdt", tclk);
111 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
112
113 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
114 orion_clkdev_add(NULL, "orion-ehci.1", usb1);
115 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
116 orion_clkdev_add(NULL, "sata_mv.0", sata);
117 orion_clkdev_add("0", "pcie", pex0);
118 orion_clkdev_add("1", "pcie", pex1);
119 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
120 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
121 orion_clkdev_add(NULL, "orion_nand", nand);
122 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
123 orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
124 orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
125 orion_clkdev_add(NULL, "mv_crypto", crypto);
126 orion_clkdev_add(NULL, "dove-ac97", ac97);
127 orion_clkdev_add(NULL, "dove-pdma", pdma);
128 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
129 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
130}
131
132/*****************************************************************************
133 * EHCI0 70 * EHCI0
134 ****************************************************************************/ 71 ****************************************************************************/
135void __init dove_ehci0_init(void) 72void __init dove_ehci0_init(void)
136{ 73{
137 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 74 orion_ehci_init(&dove_mbus_dram_info,
75 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
138} 76}
139 77
140/***************************************************************************** 78/*****************************************************************************
@@ -142,7 +80,8 @@ void __init dove_ehci0_init(void)
142 ****************************************************************************/ 80 ****************************************************************************/
143void __init dove_ehci1_init(void) 81void __init dove_ehci1_init(void)
144{ 82{
145 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 83 orion_ehci_1_init(&dove_mbus_dram_info,
84 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
146} 85}
147 86
148/***************************************************************************** 87/*****************************************************************************
@@ -150,9 +89,9 @@ void __init dove_ehci1_init(void)
150 ****************************************************************************/ 89 ****************************************************************************/
151void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 90void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
152{ 91{
153 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 92 orion_ge00_init(eth_data, &dove_mbus_dram_info,
154 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, 93 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
155 1600); 94 0, get_tclk());
156} 95}
157 96
158/***************************************************************************** 97/*****************************************************************************
@@ -168,7 +107,8 @@ void __init dove_rtc_init(void)
168 ****************************************************************************/ 107 ****************************************************************************/
169void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 108void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
170{ 109{
171 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 110 orion_sata_init(sata_data, &dove_mbus_dram_info,
111 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
172 112
173} 113}
174 114
@@ -178,7 +118,7 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
178void __init dove_uart0_init(void) 118void __init dove_uart0_init(void)
179{ 119{
180 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, 120 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
181 IRQ_DOVE_UART_0, tclk); 121 IRQ_DOVE_UART_0, get_tclk());
182} 122}
183 123
184/***************************************************************************** 124/*****************************************************************************
@@ -187,7 +127,7 @@ void __init dove_uart0_init(void)
187void __init dove_uart1_init(void) 127void __init dove_uart1_init(void)
188{ 128{
189 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, 129 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
190 IRQ_DOVE_UART_1, tclk); 130 IRQ_DOVE_UART_1, get_tclk());
191} 131}
192 132
193/***************************************************************************** 133/*****************************************************************************
@@ -196,7 +136,7 @@ void __init dove_uart1_init(void)
196void __init dove_uart2_init(void) 136void __init dove_uart2_init(void)
197{ 137{
198 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, 138 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
199 IRQ_DOVE_UART_2, tclk); 139 IRQ_DOVE_UART_2, get_tclk());
200} 140}
201 141
202/***************************************************************************** 142/*****************************************************************************
@@ -205,7 +145,7 @@ void __init dove_uart2_init(void)
205void __init dove_uart3_init(void) 145void __init dove_uart3_init(void)
206{ 146{
207 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, 147 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
208 IRQ_DOVE_UART_3, tclk); 148 IRQ_DOVE_UART_3, get_tclk());
209} 149}
210 150
211/***************************************************************************** 151/*****************************************************************************
@@ -213,12 +153,12 @@ void __init dove_uart3_init(void)
213 ****************************************************************************/ 153 ****************************************************************************/
214void __init dove_spi0_init(void) 154void __init dove_spi0_init(void)
215{ 155{
216 orion_spi_init(DOVE_SPI0_PHYS_BASE); 156 orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
217} 157}
218 158
219void __init dove_spi1_init(void) 159void __init dove_spi1_init(void)
220{ 160{
221 orion_spi_1_init(DOVE_SPI1_PHYS_BASE); 161 orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
222} 162}
223 163
224/***************************************************************************** 164/*****************************************************************************
@@ -237,16 +177,16 @@ void __init dove_init_early(void)
237 orion_time_set_base(TIMER_VIRT_BASE); 177 orion_time_set_base(TIMER_VIRT_BASE);
238} 178}
239 179
240static int __init dove_find_tclk(void) 180static int get_tclk(void)
241{ 181{
182 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
242 return 166666667; 183 return 166666667;
243} 184}
244 185
245static void __init dove_timer_init(void) 186static void dove_timer_init(void)
246{ 187{
247 dove_tclk = dove_find_tclk();
248 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 188 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
249 IRQ_DOVE_BRIDGE, dove_tclk); 189 IRQ_DOVE_BRIDGE, get_tclk());
250} 190}
251 191
252struct sys_timer dove_timer = { 192struct sys_timer dove_timer = {
@@ -254,20 +194,12 @@ struct sys_timer dove_timer = {
254}; 194};
255 195
256/***************************************************************************** 196/*****************************************************************************
257 * Cryptographic Engines and Security Accelerator (CESA)
258 ****************************************************************************/
259void __init dove_crypto_init(void)
260{
261 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
262 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
263}
264
265/*****************************************************************************
266 * XOR 0 197 * XOR 0
267 ****************************************************************************/ 198 ****************************************************************************/
268void __init dove_xor0_init(void) 199void __init dove_xor0_init(void)
269{ 200{
270 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 201 orion_xor0_init(&dove_mbus_dram_info,
202 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
271 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 203 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
272} 204}
273 205
@@ -343,120 +275,20 @@ void __init dove_sdio1_init(void)
343 275
344void __init dove_init(void) 276void __init dove_init(void)
345{ 277{
346 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", 278 int tclk;
347 (dove_tclk + 499999) / 1000000); 279
280 tclk = get_tclk();
281
282 printk(KERN_INFO "Dove 88AP510 SoC, ");
283 printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
348 284
349#ifdef CONFIG_CACHE_TAUROS2 285#ifdef CONFIG_CACHE_TAUROS2
350 tauros2_init(0); 286 tauros2_init();
351#endif 287#endif
352 dove_setup_cpu_mbus(); 288 dove_setup_cpu_mbus();
353 289
354 /* Setup root of clk tree */
355 dove_clk_init();
356
357 /* internal devices that every board has */ 290 /* internal devices that every board has */
358 dove_rtc_init(); 291 dove_rtc_init();
359 dove_xor0_init(); 292 dove_xor0_init();
360 dove_xor1_init(); 293 dove_xor1_init();
361} 294}
362
363void dove_restart(char mode, const char *cmd)
364{
365 /*
366 * Enable soft reset to assert RSTOUTn.
367 */
368 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
369
370 /*
371 * Assert soft reset.
372 */
373 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
374
375 while (1)
376 ;
377}
378
379#if defined(CONFIG_MACH_DOVE_DT)
380/*
381 * There are still devices that doesn't even know about DT,
382 * get clock gates here and add a clock lookup.
383 */
384static void __init dove_legacy_clk_init(void)
385{
386 struct device_node *np = of_find_compatible_node(NULL, NULL,
387 "marvell,dove-gating-clock");
388 struct of_phandle_args clkspec;
389
390 clkspec.np = np;
391 clkspec.args_count = 1;
392
393 clkspec.args[0] = CLOCK_GATING_BIT_USB0;
394 orion_clkdev_add(NULL, "orion-ehci.0",
395 of_clk_get_from_provider(&clkspec));
396
397 clkspec.args[0] = CLOCK_GATING_BIT_USB1;
398 orion_clkdev_add(NULL, "orion-ehci.1",
399 of_clk_get_from_provider(&clkspec));
400
401 clkspec.args[0] = CLOCK_GATING_BIT_GBE;
402 orion_clkdev_add(NULL, "mv643xx_eth_port.0",
403 of_clk_get_from_provider(&clkspec));
404
405 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
406 orion_clkdev_add("0", "pcie",
407 of_clk_get_from_provider(&clkspec));
408
409 clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
410 orion_clkdev_add("1", "pcie",
411 of_clk_get_from_provider(&clkspec));
412}
413
414static void __init dove_of_clk_init(void)
415{
416 mvebu_clocks_init();
417 dove_legacy_clk_init();
418}
419
420static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
421 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
422};
423
424static void __init dove_dt_init(void)
425{
426 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
427 (dove_tclk + 499999) / 1000000);
428
429#ifdef CONFIG_CACHE_TAUROS2
430 tauros2_init(0);
431#endif
432 dove_setup_cpu_mbus();
433
434 /* Setup root of clk tree */
435 dove_of_clk_init();
436
437 /* Internal devices not ported to DT yet */
438 dove_rtc_init();
439
440 dove_ge00_init(&dove_dt_ge00_data);
441 dove_ehci0_init();
442 dove_ehci1_init();
443 dove_pcie_init(1, 1);
444
445 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
446}
447
448static const char * const dove_dt_board_compat[] = {
449 "marvell,dove",
450 NULL
451};
452
453DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
454 .map_io = dove_map_io,
455 .init_early = dove_init_early,
456 .init_irq = orion_dt_init_irq,
457 .timer = &dove_timer,
458 .init_machine = dove_dt_init,
459 .restart = dove_restart,
460 .dt_compat = dove_dt_board_compat,
461MACHINE_END
462#endif
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 1a233404b73..6a2046e4470 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -15,6 +15,7 @@ struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data; 15struct mv_sata_platform_data;
16 16
17extern struct sys_timer dove_timer; 17extern struct sys_timer dove_timer;
18extern struct mbus_dram_target_info dove_mbus_dram_info;
18 19
19/* 20/*
20 * Basic Dove init functions used early by machine-setup. 21 * Basic Dove init functions used early by machine-setup.
@@ -26,11 +27,7 @@ void dove_init_irq(void);
26void dove_setup_cpu_mbus(void); 27void dove_setup_cpu_mbus(void);
27void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); 28void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
28void dove_sata_init(struct mv_sata_platform_data *sata_data); 29void dove_sata_init(struct mv_sata_platform_data *sata_data);
29#ifdef CONFIG_PCI
30void dove_pcie_init(int init_port0, int init_port1); 30void dove_pcie_init(int init_port0, int init_port1);
31#else
32static inline void dove_pcie_init(int init_port0, int init_port1) { }
33#endif
34void dove_ehci0_init(void); 31void dove_ehci0_init(void);
35void dove_ehci1_init(void); 32void dove_ehci1_init(void);
36void dove_uart0_init(void); 33void dove_uart0_init(void);
@@ -42,6 +39,5 @@ void dove_spi1_init(void);
42void dove_i2c_init(void); 39void dove_i2c_init(void);
43void dove_sdio0_init(void); 40void dove_sdio0_init(void);
44void dove_sdio1_init(void); 41void dove_sdio1_init(void);
45void dove_restart(char, const char *);
46 42
47#endif 43#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index bc2867f1134..2ac34ecfa74 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -20,6 +20,7 @@
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/pci.h> 21#include <linux/pci.h>
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/spi/orion_spi.h>
23#include <linux/spi/flash.h> 24#include <linux/spi/flash.h>
24#include <linux/gpio.h> 25#include <linux/gpio.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -93,11 +94,10 @@ static void __init dove_db_init(void)
93} 94}
94 95
95MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") 96MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
96 .atag_offset = 0x100, 97 .boot_params = 0x00000100,
97 .init_machine = dove_db_init, 98 .init_machine = dove_db_init,
98 .map_io = dove_map_io, 99 .map_io = dove_map_io,
99 .init_early = dove_init_early, 100 .init_early = dove_init_early,
100 .init_irq = dove_init_irq, 101 .init_irq = dove_init_irq,
101 .timer = &dove_timer, 102 .timer = &dove_timer,
102 .restart = dove_restart,
103MACHINE_END 103MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 99f259e8cf3..226949dc4ac 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
13 13
14#include <mach/dove.h> 14#include <mach/dove.h>
15 15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) 16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)
17 17
18#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) 18#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
19#define CPU_CTRL_PCIE0_LINK 0x00000001 19#define CPU_CTRL_PCIE0_LINK 0x00000001
20#define CPU_RESET 0x00000002 20#define CPU_RESET 0x00000002
21#define CPU_CTRL_PCIE1_LINK 0x00000008 21#define CPU_CTRL_PCIE1_LINK 0x00000008
22 22
23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) 23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
24#define SOFT_RESET_OUT_EN 0x00000004 24#define SOFT_RESET_OUT_EN 0x00000004
25 25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) 26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
27#define SOFT_RESET 0x00000001 27#define SOFT_RESET 0x00000001
28 28
29#define BRIDGE_INT_TIMER1_CLR (~0x0004) 29#define BRIDGE_INT_TIMER1_CLR (~0x0004)
30 30
31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) 31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
32#define IRQ_CAUSE_LOW_OFF 0x0000 32#define IRQ_CAUSE_LOW_OFF 0x0000
33#define IRQ_MASK_LOW_OFF 0x0004 33#define IRQ_MASK_LOW_OFF 0x0004
34#define FIQ_MASK_LOW_OFF 0x0008 34#define FIQ_MASK_LOW_OFF 0x0008
@@ -47,9 +47,8 @@
47#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 47#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
48#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 48#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
49 49
50#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) 50#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)
51 51
52#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) 52#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
53#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
54 53
55#endif 54#endif
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
index 5929cbc5916..da8bf2bad3b 100644
--- a/arch/arm/mach-dove/include/mach/debug-macro.S
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
8 8
9#include <mach/bridge-regs.h> 9#include <mach/bridge-regs.h>
10 10
11 .macro addruart, rp, rv, tmp 11 .macro addruart, rp, rv
12 ldr \rp, =DOVE_SB_REGS_PHYS_BASE 12 ldr \rp, =DOVE_SB_REGS_PHYS_BASE
13 ldr \rv, =DOVE_SB_REGS_VIRT_BASE 13 ldr \rv, =DOVE_SB_REGS_VIRT_BASE
14 orr \rp, \rp, #0x00012000 14 orr \rp, \rp, #0x00012000
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 661725e3115..b20ec9af788 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_ARCH_DOVE_H 11#ifndef __ASM_ARCH_DOVE_H
12#define __ASM_ARCH_DOVE_H 12#define __ASM_ARCH_DOVE_H
13 13
14#include <mach/vmalloc.h>
15
14/* 16/*
15 * Marvell Dove address maps. 17 * Marvell Dove address maps.
16 * 18 *
@@ -25,7 +27,7 @@
25 */ 27 */
26 28
27#define DOVE_CESA_PHYS_BASE 0xc8000000 29#define DOVE_CESA_PHYS_BASE 0xc8000000
28#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) 30#define DOVE_CESA_VIRT_BASE 0xfdb00000
29#define DOVE_CESA_SIZE SZ_1M 31#define DOVE_CESA_SIZE SZ_1M
30 32
31#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 33#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
@@ -38,99 +40,100 @@
38#define DOVE_BOOTROM_SIZE SZ_128M 40#define DOVE_BOOTROM_SIZE SZ_128M
39 41
40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 42#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) 43#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000
42#define DOVE_SCRATCHPAD_SIZE SZ_1M 44#define DOVE_SCRATCHPAD_SIZE SZ_1M
43 45
44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 46#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
45#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 47#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
46#define DOVE_SB_REGS_SIZE SZ_8M 48#define DOVE_SB_REGS_SIZE SZ_8M
47 49
48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 50#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
49#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) 51#define DOVE_NB_REGS_VIRT_BASE 0xfe600000
50#define DOVE_NB_REGS_SIZE SZ_8M 52#define DOVE_NB_REGS_SIZE SZ_8M
51 53
52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 54#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
55#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000
53#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 56#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
54#define DOVE_PCIE0_IO_SIZE SZ_64K 57#define DOVE_PCIE0_IO_SIZE SZ_1M
55 58
56#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 59#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
57#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 60#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000
58#define DOVE_PCIE1_IO_SIZE SZ_64K 61#define DOVE_PCIE1_IO_BUS_BASE 0x00100000
62#define DOVE_PCIE1_IO_SIZE SZ_1M
59 63
60/* 64/*
61 * Dove Core Registers Map 65 * Dove Core Registers Map
62 */ 66 */
63 67
64/* SPI, I2C, UART */ 68/* SPI, I2C, UART */
65#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) 69#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000)
66#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) 70#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000)
67#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) 71#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000)
68#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) 72#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100)
69#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) 73#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100)
70#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) 74#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200)
71#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) 75#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200)
72#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) 76#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300)
73#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) 77#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300)
74#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) 78#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600)
75#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) 79#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600)
76 80
77/* North-South Bridge */ 81/* North-South Bridge */
78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) 82#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000)
79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
80 83
81/* Cryptographic Engine */ 84/* Cryptographic Engine */
82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) 85#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000)
83 86
84/* PCIe 0 */ 87/* PCIe 0 */
85#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) 88#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000)
86 89
87/* USB */ 90/* USB */
88#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) 91#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000)
89#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) 92#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000)
90 93
91/* XOR 0 Engine */ 94/* XOR 0 Engine */
92#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) 95#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800)
93#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) 96#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800)
94#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) 97#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
95#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) 98#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
96 99
97/* XOR 1 Engine */ 100/* XOR 1 Engine */
98#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) 101#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900)
99#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) 102#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900)
100#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) 103#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
101#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) 104#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
102 105
103/* Gigabit Ethernet */ 106/* Gigabit Ethernet */
104#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) 107#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000)
105 108
106/* PCIe 1 */ 109/* PCIe 1 */
107#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) 110#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000)
108 111
109/* CAFE */ 112/* CAFE */
110#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) 113#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000)
111#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) 114#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000)
112#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) 115#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000)
113#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) 116#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
114 117
115/* SATA */ 118/* SATA */
116#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) 119#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
117 120
118/* I2S/SPDIF */ 121/* I2S/SPDIF */
119#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) 122#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
120#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) 123#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
121 124
122/* NAND Flash Controller */ 125/* NAND Flash Controller */
123#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) 126#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
124 127
125/* MPP, GPIO, Reset Sampling */ 128/* MPP, GPIO, Reset Sampling */
126#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 129#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
127#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 130#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
128#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) 131#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014)
129#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) 132#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018)
130#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 133#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
131#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) 134#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
132#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) 135#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
133#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 136#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
134#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 137#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
135#define DOVE_NAND_GPIO_EN (1 << 0) 138#define DOVE_NAND_GPIO_EN (1 << 0)
136#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 139#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +145,44 @@
142#define DOVE_SD0_GPIO_SEL (1 << 0) 145#define DOVE_SD0_GPIO_SEL (1 << 0)
143 146
144/* Power Management */ 147/* Power Management */
145#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) 148#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
146#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) 149#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
147 150
148/* Real Time Clock */ 151/* Real Time Clock */
149#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) 152#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
150 153
151/* AC97 */ 154/* AC97 */
152#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) 155#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
153#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) 156#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
154 157
155/* Peripheral DMA */ 158/* Peripheral DMA */
156#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) 159#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
157#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) 160#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
158 161
159#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 162#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
160#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) 163#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
161#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 164#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
162#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) 165#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
163#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) 166#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
164#define DOVE_TWSI_OPTION3_GPIO (1 << 22) 167#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
165#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) 168#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000)
166#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 169#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
167#define DOVE_SSP_ON_AU1 (1 << 0) 170#define DOVE_SSP_ON_AU1 (1 << 0)
168#define DOVE_SSP_CLOCK_ENABLE (1 << 1) 171#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) 172#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
170/* Memory Controller */ 173/* Memory Controller */
171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) 174#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000)
172 175
173/* LCD Controller */ 176/* LCD Controller */
174#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) 177#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
175#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) 178#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000)
176#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) 179#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000)
177#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) 180#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
178 181
179/* Graphic Engine */ 182/* Graphic Engine */
180#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) 183#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000)
181 184
182/* Video Engine */ 185/* Video Engine */
183#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) 186#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000)
184 187
185#endif 188#endif
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
index 72d622baaad..e84c78c2a8b 100644
--- a/arch/arm/mach-dove/include/mach/entry-macro.S
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -10,6 +10,12 @@
10 10
11#include <mach/bridge-regs.h> 11#include <mach/bridge-regs.h>
12 12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
13 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
14 ldr \base, =IRQ_VIRT_BASE 20 ldr \base, =IRQ_VIRT_BASE
15 .endm 21 .endm
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index b47f7503868..3ad9f946a9e 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,42 +13,24 @@
13#include <mach/irqs.h> 13#include <mach/irqs.h>
14 14
15#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) 15#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38)
16#define CLOCK_GATING_BIT_USB0 0 16#define CLOCK_GATING_USB0_MASK (1 << 0)
17#define CLOCK_GATING_BIT_USB1 1 17#define CLOCK_GATING_USB1_MASK (1 << 1)
18#define CLOCK_GATING_BIT_GBE 2 18#define CLOCK_GATING_GBE_MASK (1 << 2)
19#define CLOCK_GATING_BIT_SATA 3 19#define CLOCK_GATING_SATA_MASK (1 << 3)
20#define CLOCK_GATING_BIT_PCIE0 4 20#define CLOCK_GATING_PCIE0_MASK (1 << 4)
21#define CLOCK_GATING_BIT_PCIE1 5 21#define CLOCK_GATING_PCIE1_MASK (1 << 5)
22#define CLOCK_GATING_BIT_SDIO0 8 22#define CLOCK_GATING_SDIO0_MASK (1 << 8)
23#define CLOCK_GATING_BIT_SDIO1 9 23#define CLOCK_GATING_SDIO1_MASK (1 << 9)
24#define CLOCK_GATING_BIT_NAND 10 24#define CLOCK_GATING_NAND_MASK (1 << 10)
25#define CLOCK_GATING_BIT_CAMERA 11 25#define CLOCK_GATING_CAMERA_MASK (1 << 11)
26#define CLOCK_GATING_BIT_I2S0 12 26#define CLOCK_GATING_I2S0_MASK (1 << 12)
27#define CLOCK_GATING_BIT_I2S1 13 27#define CLOCK_GATING_I2S1_MASK (1 << 13)
28#define CLOCK_GATING_BIT_CRYPTO 15 28#define CLOCK_GATING_CRYPTO_MASK (1 << 15)
29#define CLOCK_GATING_BIT_AC97 21 29#define CLOCK_GATING_AC97_MASK (1 << 21)
30#define CLOCK_GATING_BIT_PDMA 22 30#define CLOCK_GATING_PDMA_MASK (1 << 22)
31#define CLOCK_GATING_BIT_XOR0 23 31#define CLOCK_GATING_XOR0_MASK (1 << 23)
32#define CLOCK_GATING_BIT_XOR1 24 32#define CLOCK_GATING_XOR1_MASK (1 << 24)
33#define CLOCK_GATING_BIT_GIGA_PHY 30 33#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30)
34#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0)
35#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1)
36#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE)
37#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA)
38#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0)
39#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1)
40#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0)
41#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1)
42#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND)
43#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA)
44#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0)
45#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1)
46#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO)
47#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97)
48#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA)
49#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0)
50#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1)
51#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
52 34
53#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) 35#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
54#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) 36#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
@@ -63,7 +45,7 @@ static inline int pmu_to_irq(int pin)
63 45
64static inline int irq_to_pmu(int irq) 46static inline int irq_to_pmu(int irq)
65{ 47{
66 if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS) 48 if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
67 return irq - IRQ_DOVE_PMU_START; 49 return irq - IRQ_DOVE_PMU_START;
68 50
69 return -EINVAL; 51 return -EINVAL;
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index bc4344aa100..f07fd16e0c9 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -18,9 +18,24 @@
18#include <asm/mach/irq.h> 18#include <asm/mach/irq.h>
19#include <mach/pm.h> 19#include <mach/pm.h>
20#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include <plat/orion-gpio.h>
22#include "common.h" 21#include "common.h"
23 22
23static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
24{
25 int irqoff;
26 BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
27
28 irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
29 3 + irq - IRQ_DOVE_GPIO_24_31;
30
31 orion_gpio_irq_handler(irqoff << 3);
32 if (irq == IRQ_DOVE_HIGH_GPIO) {
33 orion_gpio_irq_handler(40);
34 orion_gpio_irq_handler(48);
35 orion_gpio_irq_handler(56);
36 }
37}
38
24static void pmu_irq_mask(struct irq_data *d) 39static void pmu_irq_mask(struct irq_data *d)
25{ 40{
26 int pin = irq_to_pmu(d->irq); 41 int pin = irq_to_pmu(d->irq);
@@ -46,20 +61,8 @@ static void pmu_irq_ack(struct irq_data *d)
46 int pin = irq_to_pmu(d->irq); 61 int pin = irq_to_pmu(d->irq);
47 u32 u; 62 u32 u;
48 63
49 /*
50 * The PMU mask register is not RW0C: it is RW. This means that
51 * the bits take whatever value is written to them; if you write
52 * a '1', you will set the interrupt.
53 *
54 * Unfortunately this means there is NO race free way to clear
55 * these interrupts.
56 *
57 * So, let's structure the code so that the window is as small as
58 * possible.
59 */
60 u = ~(1 << (pin & 31)); 64 u = ~(1 << (pin & 31));
61 u &= readl_relaxed(PMU_INTERRUPT_CAUSE); 65 writel(u, PMU_INTERRUPT_CAUSE);
62 writel_relaxed(u, PMU_INTERRUPT_CAUSE);
63} 66}
64 67
65static struct irq_chip pmu_irq_chip = { 68static struct irq_chip pmu_irq_chip = {
@@ -87,45 +90,29 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
87 } 90 }
88} 91}
89 92
90static int __initdata gpio0_irqs[4] = {
91 IRQ_DOVE_GPIO_0_7,
92 IRQ_DOVE_GPIO_8_15,
93 IRQ_DOVE_GPIO_16_23,
94 IRQ_DOVE_GPIO_24_31,
95};
96
97static int __initdata gpio1_irqs[4] = {
98 IRQ_DOVE_HIGH_GPIO,
99 0,
100 0,
101 0,
102};
103
104static int __initdata gpio2_irqs[4] = {
105 0,
106 0,
107 0,
108 0,
109};
110
111void __init dove_init_irq(void) 93void __init dove_init_irq(void)
112{ 94{
113 int i; 95 int i;
114 96
115 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); 97 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
116 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); 98 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
117 99
118 /* 100 /*
119 * Initialize gpiolib for GPIOs 0-71. 101 * Initialize gpiolib for GPIOs 0-71.
120 */ 102 */
121 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, 103 orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
122 IRQ_DOVE_GPIO_START, gpio0_irqs); 104 IRQ_DOVE_GPIO_START);
123 105 irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
124 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, 106 irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
125 IRQ_DOVE_GPIO_START + 32, gpio1_irqs); 107 irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
126 108 irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
127 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, 109
128 IRQ_DOVE_GPIO_START + 64, gpio2_irqs); 110 orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
111 IRQ_DOVE_GPIO_START + 32);
112 irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
113
114 orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
115 IRQ_DOVE_GPIO_START + 64);
129 116
130 /* 117 /*
131 * Mask and clear PMU interrupts 118 * Mask and clear PMU interrupts
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 60bd729a1ba..51e0e411c9c 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -13,7 +13,6 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <plat/mpp.h> 14#include <plat/mpp.h>
15#include <mach/dove.h> 15#include <mach/dove.h>
16#include <plat/orion-gpio.h>
17#include "mpp.h" 16#include "mpp.h"
18 17
19struct dove_mpp_grp { 18struct dove_mpp_grp {
@@ -57,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
57 56
58/* Dump all the extra MPP registers. The platform code will dump the 57/* Dump all the extra MPP registers. The platform code will dump the
59 registers for pins 0-23. */ 58 registers for pins 0-23. */
60static void __init dove_mpp_dump_regs(void) 59static void dove_mpp_dump_regs(void)
61{ 60{
62 pr_debug("PMU_CTRL4_CTRL: %08x\n", 61 pr_debug("PMU_CTRL4_CTRL: %08x\n",
63 readl(DOVE_MPP_CTRL4_VIRT_BASE)); 62 readl(DOVE_MPP_CTRL4_VIRT_BASE));
@@ -68,7 +67,7 @@ static void __init dove_mpp_dump_regs(void)
68 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); 67 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
69} 68}
70 69
71static void __init dove_mpp_cfg_nfc(int sel) 70static void dove_mpp_cfg_nfc(int sel)
72{ 71{
73 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); 72 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
74 73
@@ -79,7 +78,7 @@ static void __init dove_mpp_cfg_nfc(int sel)
79 dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); 78 dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
80} 79}
81 80
82static void __init dove_mpp_cfg_au1(int sel) 81static void dove_mpp_cfg_au1(int sel)
83{ 82{
84 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 83 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
85 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); 84 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
@@ -119,7 +118,7 @@ static void __init dove_mpp_cfg_au1(int sel)
119 118
120/* Configure the group registers, enabling GPIO if sel indicates the 119/* Configure the group registers, enabling GPIO if sel indicates the
121 pin is to be used for GPIO */ 120 pin is to be used for GPIO */
122static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list) 121static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
123{ 122{
124 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 123 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
125 int gpio_mode; 124 int gpio_mode;
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 8a275f29752..aa2b3a09a51 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -10,7 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/clk.h> 13#include <linux/mbus.h>
14#include <video/vga.h> 14#include <video/vga.h>
15#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
@@ -19,7 +19,6 @@
19#include <plat/pcie.h> 19#include <plat/pcie.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21#include <mach/bridge-regs.h> 21#include <mach/bridge-regs.h>
22#include <plat/addr-map.h>
23#include "common.h" 22#include "common.h"
24 23
25struct pcie_port { 24struct pcie_port {
@@ -27,8 +26,9 @@ struct pcie_port {
27 u8 root_bus_nr; 26 u8 root_bus_nr;
28 void __iomem *base; 27 void __iomem *base;
29 spinlock_t conf_lock; 28 spinlock_t conf_lock;
29 char io_space_name[16];
30 char mem_space_name[16]; 30 char mem_space_name[16];
31 struct resource res; 31 struct resource res[2];
32}; 32};
33 33
34static struct pcie_port pcie_port[2]; 34static struct pcie_port pcie_port[2];
@@ -43,7 +43,6 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
43 return 0; 43 return 0;
44 44
45 pp = &pcie_port[nr]; 45 pp = &pcie_port[nr];
46 sys->private_data = pp;
47 pp->root_bus_nr = sys->busnr; 46 pp->root_bus_nr = sys->busnr;
48 47
49 /* 48 /*
@@ -51,12 +50,26 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
51 */ 50 */
52 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
53 52
54 orion_pcie_setup(pp->base); 53 orion_pcie_setup(pp->base, &dove_mbus_dram_info);
55 54
56 if (pp->index == 0) 55 /*
57 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); 56 * IORESOURCE_IO
58 else 57 */
59 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); 58 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
59 "PCIe %d I/O", pp->index);
60 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
61 pp->res[0].name = pp->io_space_name;
62 if (pp->index == 0) {
63 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
64 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
65 } else {
66 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
67 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
68 }
69 pp->res[0].flags = IORESOURCE_IO;
70 if (request_resource(&ioport_resource, &pp->res[0]))
71 panic("Request PCIe IO resource failed\n");
72 sys->resource[0] = &pp->res[0];
60 73
61 /* 74 /*
62 * IORESOURCE_MEM 75 * IORESOURCE_MEM
@@ -64,22 +77,37 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
64 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 77 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
65 "PCIe %d MEM", pp->index); 78 "PCIe %d MEM", pp->index);
66 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 79 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
67 pp->res.name = pp->mem_space_name; 80 pp->res[1].name = pp->mem_space_name;
68 if (pp->index == 0) { 81 if (pp->index == 0) {
69 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; 82 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
70 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; 83 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
71 } else { 84 } else {
72 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; 85 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
73 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; 86 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
74 } 87 }
75 pp->res.flags = IORESOURCE_MEM; 88 pp->res[1].flags = IORESOURCE_MEM;
76 if (request_resource(&iomem_resource, &pp->res)) 89 if (request_resource(&iomem_resource, &pp->res[1]))
77 panic("Request PCIe Memory resource failed\n"); 90 panic("Request PCIe Memory resource failed\n");
78 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); 91 sys->resource[1] = &pp->res[1];
92
93 sys->resource[2] = NULL;
79 94
80 return 1; 95 return 1;
81} 96}
82 97
98static struct pcie_port *bus_to_port(int bus)
99{
100 int i;
101
102 for (i = num_pcie_ports - 1; i >= 0; i--) {
103 int rbus = pcie_port[i].root_bus_nr;
104 if (rbus != -1 && rbus <= bus)
105 break;
106 }
107
108 return i >= 0 ? pcie_port + i : NULL;
109}
110
83static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) 111static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
84{ 112{
85 /* 113 /*
@@ -95,8 +123,7 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
95static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 123static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
96 int size, u32 *val) 124 int size, u32 *val)
97{ 125{
98 struct pci_sys_data *sys = bus->sysdata; 126 struct pcie_port *pp = bus_to_port(bus->number);
99 struct pcie_port *pp = sys->private_data;
100 unsigned long flags; 127 unsigned long flags;
101 int ret; 128 int ret;
102 129
@@ -115,8 +142,7 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
115static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 142static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
116 int where, int size, u32 val) 143 int where, int size, u32 val)
117{ 144{
118 struct pci_sys_data *sys = bus->sysdata; 145 struct pcie_port *pp = bus_to_port(bus->number);
119 struct pcie_port *pp = sys->private_data;
120 unsigned long flags; 146 unsigned long flags;
121 int ret; 147 int ret;
122 148
@@ -135,7 +161,7 @@ static struct pci_ops pcie_ops = {
135 .write = pcie_wr_conf, 161 .write = pcie_wr_conf,
136}; 162};
137 163
138static void rc_pci_fixup(struct pci_dev *dev) 164static void __devinit rc_pci_fixup(struct pci_dev *dev)
139{ 165{
140 /* 166 /*
141 * Prevent enumeration of root complex. 167 * Prevent enumeration of root complex.
@@ -158,8 +184,7 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
158 struct pci_bus *bus; 184 struct pci_bus *bus;
159 185
160 if (nr < num_pcie_ports) { 186 if (nr < num_pcie_ports) {
161 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, 187 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
162 &sys->resources);
163 } else { 188 } else {
164 bus = NULL; 189 bus = NULL;
165 BUG(); 190 BUG();
@@ -170,37 +195,33 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
170 195
171static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 196static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
172{ 197{
173 struct pci_sys_data *sys = dev->sysdata; 198 struct pcie_port *pp = bus_to_port(dev->bus->number);
174 struct pcie_port *pp = sys->private_data;
175 199
176 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; 200 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
177} 201}
178 202
179static struct hw_pci dove_pci __initdata = { 203static struct hw_pci dove_pci __initdata = {
180 .nr_controllers = 2, 204 .nr_controllers = 2,
205 .swizzle = pci_std_swizzle,
181 .setup = dove_pcie_setup, 206 .setup = dove_pcie_setup,
182 .scan = dove_pcie_scan_bus, 207 .scan = dove_pcie_scan_bus,
183 .map_irq = dove_pcie_map_irq, 208 .map_irq = dove_pcie_map_irq,
184}; 209};
185 210
186static void __init add_pcie_port(int index, void __iomem *base) 211static void __init add_pcie_port(int index, unsigned long base)
187{ 212{
188 printk(KERN_INFO "Dove PCIe port %d: ", index); 213 printk(KERN_INFO "Dove PCIe port %d: ", index);
189 214
190 if (orion_pcie_link_up(base)) { 215 if (orion_pcie_link_up((void __iomem *)base)) {
191 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 216 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
192 struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0"));
193
194 if (!IS_ERR(clk))
195 clk_prepare_enable(clk);
196 217
197 printk(KERN_INFO "link up\n"); 218 printk(KERN_INFO "link up\n");
198 219
199 pp->index = index; 220 pp->index = index;
200 pp->root_bus_nr = -1; 221 pp->root_bus_nr = -1;
201 pp->base = base; 222 pp->base = (void __iomem *)base;
202 spin_lock_init(&pp->conf_lock); 223 spin_lock_init(&pp->conf_lock);
203 memset(&pp->res, 0, sizeof(pp->res)); 224 memset(pp->res, 0, sizeof(pp->res));
204 } else { 225 } else {
205 printk(KERN_INFO "link down, ignoring\n"); 226 printk(KERN_INFO "link down, ignoring\n");
206 } 227 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 01:14:22 -0400