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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/arm/mach-bcmring
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/arm/mach-bcmring')
-rw-r--r--arch/arm/mach-bcmring/Kconfig21
-rw-r--r--arch/arm/mach-bcmring/Makefile8
-rw-r--r--arch/arm/mach-bcmring/Makefile.boot6
-rw-r--r--arch/arm/mach-bcmring/arch.c176
-rw-r--r--arch/arm/mach-bcmring/clock.c223
-rw-r--r--arch/arm/mach-bcmring/clock.h33
-rw-r--r--arch/arm/mach-bcmring/core.c248
-rw-r--r--arch/arm/mach-bcmring/core.h31
-rw-r--r--arch/arm/mach-bcmring/csp/Makefile3
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/Makefile1
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw.c776
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c293
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c124
-rw-r--r--arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c64
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/Makefile1
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw.c917
-rw-r--r--arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c1017
-rw-r--r--arch/arm/mach-bcmring/csp/tmr/Makefile1
-rw-r--r--arch/arm/mach-bcmring/csp/tmr/tmrHw.c576
-rw-r--r--arch/arm/mach-bcmring/dma.c2329
-rw-r--r--arch/arm/mach-bcmring/dma_device.c593
-rw-r--r--arch/arm/mach-bcmring/include/cfg_global.h13
-rw-r--r--arch/arm/mach-bcmring/include/cfg_global_defines.h40
-rw-r--r--arch/arm/mach-bcmring/include/csp/cache.h35
-rw-r--r--arch/arm/mach-bcmring/include/csp/delay.h36
-rw-r--r--arch/arm/mach-bcmring/include/csp/dmacHw.h596
-rw-r--r--arch/arm/mach-bcmring/include/csp/errno.h32
-rw-r--r--arch/arm/mach-bcmring/include/csp/intcHw.h40
-rw-r--r--arch/arm/mach-bcmring/include/csp/module.h32
-rw-r--r--arch/arm/mach-bcmring/include/csp/reg.h114
-rw-r--r--arch/arm/mach-bcmring/include/csp/secHw.h65
-rw-r--r--arch/arm/mach-bcmring/include/csp/stdint.h30
-rw-r--r--arch/arm/mach-bcmring/include/csp/string.h34
-rw-r--r--arch/arm/mach-bcmring/include/csp/tmrHw.h263
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/cap.h63
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/cap_inline.h409
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h1123
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h1673
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h530
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h872
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h145
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h406
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h73
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h246
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_addr.h101
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/mm_io.h147
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_def.h100
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h79
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h82
-rw-r--r--arch/arm/mach-bcmring/include/mach/dma.h826
-rw-r--r--arch/arm/mach-bcmring/include/mach/entry-macro.S82
-rw-r--r--arch/arm/mach-bcmring/include/mach/hardware.h58
-rw-r--r--arch/arm/mach-bcmring/include/mach/io.h33
-rw-r--r--arch/arm/mach-bcmring/include/mach/irqs.h132
-rw-r--r--arch/arm/mach-bcmring/include/mach/memory.h33
-rw-r--r--arch/arm/mach-bcmring/include/mach/memory_settings.h67
-rw-r--r--arch/arm/mach-bcmring/include/mach/reg_nand.h66
-rw-r--r--arch/arm/mach-bcmring/include/mach/reg_umi.h237
-rw-r--r--arch/arm/mach-bcmring/include/mach/system.h54
-rw-r--r--arch/arm/mach-bcmring/include/mach/timer.h77
-rw-r--r--arch/arm/mach-bcmring/include/mach/timex.h25
-rw-r--r--arch/arm/mach-bcmring/include/mach/uncompress.h43
-rw-r--r--arch/arm/mach-bcmring/include/mach/vmalloc.h25
-rw-r--r--arch/arm/mach-bcmring/irq.c127
-rw-r--r--arch/arm/mach-bcmring/mm.c56
-rw-r--r--arch/arm/mach-bcmring/timer.c62
66 files changed, 16823 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
new file mode 100644
index 00000000000..457b4384913
--- /dev/null
+++ b/arch/arm/mach-bcmring/Kconfig
@@ -0,0 +1,21 @@
1choice
2 prompt "Processor selection in BCMRING family of devices"
3 depends on ARCH_BCMRING
4 default ARCH_BCM11107
5
6config ARCH_FPGA11107
7 bool "FPGA11107"
8
9config ARCH_BCM11107
10 bool "BCM11107"
11endchoice
12
13menu "BCMRING Options"
14 depends on ARCH_BCMRING
15
16config BCM_ZRELADDR
17 hex "Compressed ZREL ADDR"
18
19endmenu
20
21# source "drivers/char/bcmring/Kconfig"
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
new file mode 100644
index 00000000000..f8d9fcedf91
--- /dev/null
+++ b/arch/arm/mach-bcmring/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
8obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
new file mode 100644
index 00000000000..fb53b283beb
--- /dev/null
+++ b/arch/arm/mach-bcmring/Makefile.boot
@@ -0,0 +1,6 @@
1# Address where decompressor will be written and eventually executed.
2#
3# default to SDRAM
4zreladdr-y := $(CONFIG_BCM_ZRELADDR)
5params_phys-y := 0x00000800
6
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
new file mode 100644
index 00000000000..a604b9ebb50
--- /dev/null
+++ b/arch/arm/mach-bcmring/arch.c
@@ -0,0 +1,176 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/types.h>
18#include <linux/sched.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/errno.h>
22#include <linux/spinlock.h>
23#include <linux/module.h>
24
25#include <linux/proc_fs.h>
26#include <linux/sysctl.h>
27
28#include <asm/irq.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/mach/time.h>
32#include <asm/pmu.h>
33
34#include <asm/mach/arch.h>
35#include <mach/dma.h>
36#include <mach/hardware.h>
37#include <mach/csp/mm_io.h>
38#include <mach/csp/chipcHw_def.h>
39#include <mach/csp/chipcHw_inline.h>
40
41#include <cfg_global.h>
42
43#include "core.h"
44
45HW_DECLARE_SPINLOCK(arch)
46HW_DECLARE_SPINLOCK(gpio)
47#if defined(CONFIG_DEBUG_SPINLOCK)
48 EXPORT_SYMBOL(bcmring_gpio_reg_lock);
49#endif
50
51/* sysctl */
52int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */
53
54static struct ctl_table_header *bcmring_sysctl_header;
55
56static struct ctl_table bcmring_sysctl_warm_reboot[] = {
57 {
58 .procname = "warm",
59 .data = &bcmring_arch_warm_reboot,
60 .maxlen = sizeof(int),
61 .mode = 0644,
62 .proc_handler = proc_dointvec},
63 {}
64};
65
66static struct ctl_table bcmring_sysctl_reboot[] = {
67 {
68 .procname = "reboot",
69 .mode = 0555,
70 .child = bcmring_sysctl_warm_reboot},
71 {}
72};
73
74static struct resource nand_resource[] = {
75 [0] = {
76 .start = MM_ADDR_IO_NAND,
77 .end = MM_ADDR_IO_NAND + 0x1000 - 1,
78 .flags = IORESOURCE_MEM,
79 },
80};
81
82static struct platform_device nand_device = {
83 .name = "bcm-nand",
84 .id = -1,
85 .resource = nand_resource,
86 .num_resources = ARRAY_SIZE(nand_resource),
87};
88
89static struct resource pmu_resource = {
90 .start = IRQ_PMUIRQ,
91 .end = IRQ_PMUIRQ,
92 .flags = IORESOURCE_IRQ,
93};
94
95static struct platform_device pmu_device = {
96 .name = "arm-pmu",
97 .id = ARM_PMU_DEVICE_CPU,
98 .resource = &pmu_resource,
99 .num_resources = 1,
100};
101
102
103static struct platform_device *devices[] __initdata = {
104 &nand_device,
105 &pmu_device,
106};
107
108/****************************************************************************
109*
110* Called from the customize_machine function in arch/arm/kernel/setup.c
111*
112* The customize_machine function is tagged as an arch_initcall
113* (see include/linux/init.h for the order that the various init sections
114* are called in.
115*
116*****************************************************************************/
117static void __init bcmring_init_machine(void)
118{
119
120 bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
121
122 /* Enable spread spectrum */
123 chipcHw_enableSpreadSpectrum();
124
125 platform_add_devices(devices, ARRAY_SIZE(devices));
126
127 bcmring_amba_init();
128
129 dma_init();
130}
131
132/****************************************************************************
133*
134* Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
135* passed in by the boot loader.
136*
137*****************************************************************************/
138
139static void __init bcmring_fixup(struct machine_desc *desc,
140 struct tag *t, char **cmdline, struct meminfo *mi) {
141#ifdef CONFIG_BLK_DEV_INITRD
142 printk(KERN_NOTICE "bcmring_fixup\n");
143 t->hdr.tag = ATAG_CORE;
144 t->hdr.size = tag_size(tag_core);
145 t->u.core.flags = 0;
146 t->u.core.pagesize = PAGE_SIZE;
147 t->u.core.rootdev = 31 << 8 | 0;
148 t = tag_next(t);
149
150 t->hdr.tag = ATAG_MEM;
151 t->hdr.size = tag_size(tag_mem32);
152 t->u.mem.start = CFG_GLOBAL_RAM_BASE;
153 t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
154
155 t = tag_next(t);
156
157 t->hdr.tag = ATAG_NONE;
158 t->hdr.size = 0;
159#endif
160}
161
162/****************************************************************************
163*
164* Machine Description
165*
166*****************************************************************************/
167
168MACHINE_START(BCMRING, "BCMRING")
169 /* Maintainer: Broadcom Corporation */
170 .fixup = bcmring_fixup,
171 .map_io = bcmring_map_io,
172 .init_early = bcmring_init_early,
173 .init_irq = bcmring_init_irq,
174 .timer = &bcmring_timer,
175 .init_machine = bcmring_init_machine
176MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
new file mode 100644
index 00000000000..ad237a42d26
--- /dev/null
+++ b/arch/arm/mach-bcmring/clock.c
@@ -0,0 +1,223 @@
1/*****************************************************************************
2* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/device.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/string.h>
22#include <linux/clk.h>
23#include <linux/spinlock.h>
24#include <linux/clkdev.h>
25#include <mach/csp/hw_cfg.h>
26#include <mach/csp/chipcHw_def.h>
27#include <mach/csp/chipcHw_reg.h>
28#include <mach/csp/chipcHw_inline.h>
29
30#include "clock.h"
31
32#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
33#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
34#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
35#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
36#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
37
38#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
39
40static DEFINE_SPINLOCK(clk_lock);
41
42static void __clk_enable(struct clk *clk)
43{
44 if (!clk)
45 return;
46
47 /* enable parent clock first */
48 if (clk->parent)
49 __clk_enable(clk->parent);
50
51 if (clk->use_cnt++ == 0) {
52 if (clk_is_pll1(clk)) { /* PLL1 */
53 chipcHw_pll1Enable(clk->rate_hz, 0);
54 } else if (clk_is_pll2(clk)) { /* PLL2 */
55 chipcHw_pll2Enable(clk->rate_hz);
56 } else if (clk_is_using_xtal(clk)) { /* source is crystal */
57 if (!clk_is_primary(clk))
58 chipcHw_bypassClockEnable(clk->csp_id);
59 } else { /* source is PLL */
60 chipcHw_setClockEnable(clk->csp_id);
61 }
62 }
63}
64
65int clk_enable(struct clk *clk)
66{
67 unsigned long flags;
68
69 if (!clk)
70 return -EINVAL;
71
72 spin_lock_irqsave(&clk_lock, flags);
73 __clk_enable(clk);
74 spin_unlock_irqrestore(&clk_lock, flags);
75
76 return 0;
77}
78EXPORT_SYMBOL(clk_enable);
79
80static void __clk_disable(struct clk *clk)
81{
82 if (!clk)
83 return;
84
85 BUG_ON(clk->use_cnt == 0);
86
87 if (--clk->use_cnt == 0) {
88 if (clk_is_pll1(clk)) { /* PLL1 */
89 chipcHw_pll1Disable();
90 } else if (clk_is_pll2(clk)) { /* PLL2 */
91 chipcHw_pll2Disable();
92 } else if (clk_is_using_xtal(clk)) { /* source is crystal */
93 if (!clk_is_primary(clk))
94 chipcHw_bypassClockDisable(clk->csp_id);
95 } else { /* source is PLL */
96 chipcHw_setClockDisable(clk->csp_id);
97 }
98 }
99
100 if (clk->parent)
101 __clk_disable(clk->parent);
102}
103
104void clk_disable(struct clk *clk)
105{
106 unsigned long flags;
107
108 if (!clk)
109 return;
110
111 spin_lock_irqsave(&clk_lock, flags);
112 __clk_disable(clk);
113 spin_unlock_irqrestore(&clk_lock, flags);
114}
115EXPORT_SYMBOL(clk_disable);
116
117unsigned long clk_get_rate(struct clk *clk)
118{
119 if (!clk)
120 return 0;
121
122 return clk->rate_hz;
123}
124EXPORT_SYMBOL(clk_get_rate);
125
126long clk_round_rate(struct clk *clk, unsigned long rate)
127{
128 unsigned long flags;
129 unsigned long actual;
130 unsigned long rate_hz;
131
132 if (!clk)
133 return -EINVAL;
134
135 if (!clk_is_programmable(clk))
136 return -EINVAL;
137
138 if (clk->use_cnt)
139 return -EBUSY;
140
141 spin_lock_irqsave(&clk_lock, flags);
142 actual = clk->parent->rate_hz;
143 rate_hz = min(actual, rate);
144 spin_unlock_irqrestore(&clk_lock, flags);
145
146 return rate_hz;
147}
148EXPORT_SYMBOL(clk_round_rate);
149
150int clk_set_rate(struct clk *clk, unsigned long rate)
151{
152 unsigned long flags;
153 unsigned long actual;
154 unsigned long rate_hz;
155
156 if (!clk)
157 return -EINVAL;
158
159 if (!clk_is_programmable(clk))
160 return -EINVAL;
161
162 if (clk->use_cnt)
163 return -EBUSY;
164
165 spin_lock_irqsave(&clk_lock, flags);
166 actual = clk->parent->rate_hz;
167 rate_hz = min(actual, rate);
168 rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
169 clk->rate_hz = rate_hz;
170 spin_unlock_irqrestore(&clk_lock, flags);
171
172 return 0;
173}
174EXPORT_SYMBOL(clk_set_rate);
175
176struct clk *clk_get_parent(struct clk *clk)
177{
178 if (!clk)
179 return NULL;
180
181 return clk->parent;
182}
183EXPORT_SYMBOL(clk_get_parent);
184
185int clk_set_parent(struct clk *clk, struct clk *parent)
186{
187 unsigned long flags;
188 struct clk *old_parent;
189
190 if (!clk || !parent)
191 return -EINVAL;
192
193 if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
194 return -EINVAL;
195
196 /* if more than one user, parent is not allowed */
197 if (clk->use_cnt > 1)
198 return -EBUSY;
199
200 if (clk->parent == parent)
201 return 0;
202
203 spin_lock_irqsave(&clk_lock, flags);
204 old_parent = clk->parent;
205 clk->parent = parent;
206 if (clk_is_using_xtal(parent))
207 clk->mode |= CLK_MODE_XTAL;
208 else
209 clk->mode &= (~CLK_MODE_XTAL);
210
211 /* if clock is active */
212 if (clk->use_cnt != 0) {
213 clk->use_cnt--;
214 /* enable clock with the new parent */
215 __clk_enable(clk);
216 /* disable the old parent */
217 __clk_disable(old_parent);
218 }
219 spin_unlock_irqrestore(&clk_lock, flags);
220
221 return 0;
222}
223EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
new file mode 100644
index 00000000000..5e0b9813897
--- /dev/null
+++ b/arch/arm/mach-bcmring/clock.h
@@ -0,0 +1,33 @@
1/*****************************************************************************
2* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14#include <mach/csp/chipcHw_def.h>
15
16#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */
17#define CLK_TYPE_PLL1 2 /* PPL1 */
18#define CLK_TYPE_PLL2 4 /* PPL2 */
19#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */
20#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */
21
22#define CLK_MODE_XTAL 1 /* clock source is from crystal */
23
24struct clk {
25 const char *name; /* clock name */
26 unsigned int type; /* clock type */
27 unsigned int mode; /* current mode */
28 volatile int use_bypass; /* indicate if it's in bypass mode */
29 chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
30 unsigned long rate_hz; /* clock rate in Hz */
31 unsigned int use_cnt; /* usage count */
32 struct clk *parent; /* parent clock */
33};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
new file mode 100644
index 00000000000..43eadbcc29e
--- /dev/null
+++ b/arch/arm/mach-bcmring/core.c
@@ -0,0 +1,248 @@
1/*
2 * derived from linux/arch/arm/mach-versatile/core.c
3 * linux/arch/arm/mach-bcmring/core.c
4 *
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22/* Portions copyright Broadcom 2008 */
23
24#include <linux/init.h>
25#include <linux/device.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/sysdev.h>
29#include <linux/interrupt.h>
30#include <linux/amba/bus.h>
31#include <linux/clkdev.h>
32
33#include <mach/csp/mm_addr.h>
34#include <mach/hardware.h>
35#include <linux/io.h>
36#include <asm/irq.h>
37#include <asm/hardware/arm_timer.h>
38#include <asm/hardware/timer-sp.h>
39#include <asm/mach-types.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/flash.h>
43#include <asm/mach/irq.h>
44#include <asm/mach/time.h>
45#include <asm/mach/map.h>
46
47#include <cfg_global.h>
48
49#include "clock.h"
50
51#include <csp/secHw.h>
52#include <mach/csp/secHw_def.h>
53#include <mach/csp/chipcHw_inline.h>
54#include <mach/csp/tmrHw_reg.h>
55
56#define AMBA_DEVICE(name, initname, base, plat, size) \
57static struct amba_device name##_device = { \
58 .dev = { \
59 .coherent_dma_mask = ~0, \
60 .init_name = initname, \
61 .platform_data = plat \
62 }, \
63 .res = { \
64 .start = MM_ADDR_IO_##base, \
65 .end = MM_ADDR_IO_##base + (size) - 1, \
66 .flags = IORESOURCE_MEM \
67 }, \
68 .dma_mask = ~0, \
69 .irq = { \
70 IRQ_##base \
71 } \
72}
73
74
75AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
76AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
77
78static struct clk pll1_clk = {
79 .name = "PLL1",
80 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
81 .rate_hz = 2000000000,
82 .use_cnt = 7,
83};
84
85static struct clk uart_clk = {
86 .name = "UART",
87 .type = CLK_TYPE_PROGRAMMABLE,
88 .csp_id = chipcHw_CLOCK_UART,
89 .rate_hz = HW_CFG_UART_CLK_HZ,
90 .parent = &pll1_clk,
91};
92
93static struct clk dummy_apb_pclk = {
94 .name = "BUSCLK",
95 .type = CLK_TYPE_PRIMARY,
96 .mode = CLK_MODE_XTAL,
97};
98
99/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
100#if defined(CONFIG_ARCH_FPGA11107)
101/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
102/* slow down Linux's sense of time */
103#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
104#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
105#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
106#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
107#else
108#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
109#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
110#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
111#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
112#endif
113
114static struct clk sp804_timer012_clk = {
115 .name = "sp804-timer-0,1,2",
116 .type = CLK_TYPE_PRIMARY,
117 .mode = CLK_MODE_XTAL,
118 .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
119};
120
121static struct clk sp804_timer3_clk = {
122 .name = "sp804-timer-3",
123 .type = CLK_TYPE_PRIMARY,
124 .mode = CLK_MODE_XTAL,
125 .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
126};
127
128static struct clk_lookup lookups[] = {
129 { /* Bus clock */
130 .con_id = "apb_pclk",
131 .clk = &dummy_apb_pclk,
132 }, { /* UART0 */
133 .dev_id = "uarta",
134 .clk = &uart_clk,
135 }, { /* UART1 */
136 .dev_id = "uartb",
137 .clk = &uart_clk,
138 }, { /* SP804 timer 0 */
139 .dev_id = "sp804",
140 .con_id = "timer0",
141 .clk = &sp804_timer012_clk,
142 }, { /* SP804 timer 1 */
143 .dev_id = "sp804",
144 .con_id = "timer1",
145 .clk = &sp804_timer012_clk,
146 }, { /* SP804 timer 3 */
147 .dev_id = "sp804",
148 .con_id = "timer3",
149 .clk = &sp804_timer3_clk,
150 }
151};
152
153static struct amba_device *amba_devs[] __initdata = {
154 &uartA_device,
155 &uartB_device,
156};
157
158void __init bcmring_amba_init(void)
159{
160 int i;
161 u32 bus_clock;
162
163/* Linux is run initially in non-secure mode. Secure peripherals */
164/* generate FIQ, and must be handled in secure mode. Until we have */
165/* a linux security monitor implementation, keep everything in */
166/* non-secure mode. */
167 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
168 secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
169 secHw_BLK_MASK_KEY_SCAN |
170 secHw_BLK_MASK_TOUCH_SCREEN |
171 secHw_BLK_MASK_UART0 |
172 secHw_BLK_MASK_UART1 |
173 secHw_BLK_MASK_WATCHDOG |
174 secHw_BLK_MASK_SPUM |
175 secHw_BLK_MASK_DDR2 |
176 secHw_BLK_MASK_SPU |
177 secHw_BLK_MASK_PKA |
178 secHw_BLK_MASK_RNG |
179 secHw_BLK_MASK_RTC |
180 secHw_BLK_MASK_OTP |
181 secHw_BLK_MASK_BOOT |
182 secHw_BLK_MASK_MPU |
183 secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
184
185 /* Only the devices attached to the AMBA bus are enabled just before the bus is */
186 /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
187 /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
188 /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
189 bus_clock = chipcHw_REG_BUS_CLOCK_GE
190 | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
191
192 chipcHw_busInterfaceClockEnable(bus_clock);
193
194 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
195 struct amba_device *d = amba_devs[i];
196 amba_device_register(d, &iomem_resource);
197 }
198}
199
200/*
201 * Where is the timer (VA)?
202 */
203#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
204#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
205#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
206#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
207
208static int __init bcmring_clocksource_init(void)
209{
210 /* setup timer1 as free-running clocksource */
211 sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
212
213 /* setup timer3 as free-running clocksource */
214 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
215
216 return 0;
217}
218
219/*
220 * Set up timer interrupt, and return the current time in seconds.
221 */
222void __init bcmring_init_timer(void)
223{
224 printk(KERN_INFO "bcmring_init_timer\n");
225 /*
226 * Initialise to a known state (all timers off)
227 */
228 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
229 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
230 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
231 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
232
233 /*
234 * Make irqs happen for the system timer
235 */
236 bcmring_clocksource_init();
237
238 sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
239}
240
241struct sys_timer bcmring_timer = {
242 .init = bcmring_init_timer,
243};
244
245void __init bcmring_init_early(void)
246{
247 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
248}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
new file mode 100644
index 00000000000..e0e02c48f9b
--- /dev/null
+++ b/arch/arm/mach-bcmring/core.h
@@ -0,0 +1,31 @@
1/*
2 * linux/arch/arm/mach-versatile/core.h
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21/* Portions copyright Broadcom 2008 */
22#ifndef __ASM_ARCH_BCMRING_H
23#define __ASM_ARCH_BCMRING_H
24
25void __init bcmring_amba_init(void);
26void __init bcmring_map_io(void);
27void __init bcmring_init_irq(void);
28void __init bcmring_init_early(void);
29
30extern struct sys_timer bcmring_timer;
31#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
new file mode 100644
index 00000000000..648c0377530
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/Makefile
@@ -0,0 +1,3 @@
1obj-y += dmac/
2obj-y += tmr/
3obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
new file mode 100644
index 00000000000..673952768ee
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/Makefile
@@ -0,0 +1 @@
obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
new file mode 100644
index 00000000000..96273ff3495
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -0,0 +1,776 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw.c
18*
19* @brief Low level Various CHIP clock controlling routines
20*
21* @note
22*
23* These routines provide basic clock controlling functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <csp/errno.h>
30#include <csp/stdint.h>
31#include <csp/module.h>
32
33#include <mach/csp/chipcHw_def.h>
34#include <mach/csp/chipcHw_inline.h>
35
36#include <csp/reg.h>
37#include <csp/delay.h>
38
39/* ---- Private Constants and Types --------------------------------------- */
40
41/* VPM alignment algorithm uses this */
42#define MAX_PHASE_ADJUST_COUNT 0xFFFF /* Max number of times allowed to adjust the phase */
43#define MAX_PHASE_ALIGN_ATTEMPTS 10 /* Max number of attempt to align the phase */
44
45/* Local definition of clock type */
46#define PLL_CLOCK 1 /* PLL Clock */
47#define NON_PLL_CLOCK 2 /* Divider clock */
48
49static int chipcHw_divide(int num, int denom)
50 __attribute__ ((section(".aramtext")));
51
52/****************************************************************************/
53/**
54* @brief Set clock fequency for miscellaneous configurable clocks
55*
56* This function sets clock frequency
57*
58* @return Configured clock frequency in hertz
59*
60*/
61/****************************************************************************/
62chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
63 ) {
64 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
65 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
66 volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
67 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
68 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
69 uint32_t dependentClockType = 0;
70 uint32_t vcoHz = 0;
71
72 /* Get VCO frequencies */
73 if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
74 uint64_t adjustFreq = 0;
75
76 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
77 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
78 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
79 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
80
81 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
82 adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
83 (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
84 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
85 vcoFreqPll1Hz += (uint32_t) adjustFreq;
86 } else {
87 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
88 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
89 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
90 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
91 }
92 vcoFreqPll2Hz =
93 chipcHw_XTAL_FREQ_Hz *
94 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
95 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
96 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
97
98 switch (clock) {
99 case chipcHw_CLOCK_DDR:
100 pPLLReg = &pChipcHw->DDRClock;
101 vcoHz = vcoFreqPll1Hz;
102 break;
103 case chipcHw_CLOCK_ARM:
104 pPLLReg = &pChipcHw->ARMClock;
105 vcoHz = vcoFreqPll1Hz;
106 break;
107 case chipcHw_CLOCK_ESW:
108 pPLLReg = &pChipcHw->ESWClock;
109 vcoHz = vcoFreqPll1Hz;
110 break;
111 case chipcHw_CLOCK_VPM:
112 pPLLReg = &pChipcHw->VPMClock;
113 vcoHz = vcoFreqPll1Hz;
114 break;
115 case chipcHw_CLOCK_ESW125:
116 pPLLReg = &pChipcHw->ESW125Clock;
117 vcoHz = vcoFreqPll1Hz;
118 break;
119 case chipcHw_CLOCK_UART:
120 pPLLReg = &pChipcHw->UARTClock;
121 vcoHz = vcoFreqPll1Hz;
122 break;
123 case chipcHw_CLOCK_SDIO0:
124 pPLLReg = &pChipcHw->SDIO0Clock;
125 vcoHz = vcoFreqPll1Hz;
126 break;
127 case chipcHw_CLOCK_SDIO1:
128 pPLLReg = &pChipcHw->SDIO1Clock;
129 vcoHz = vcoFreqPll1Hz;
130 break;
131 case chipcHw_CLOCK_SPI:
132 pPLLReg = &pChipcHw->SPIClock;
133 vcoHz = vcoFreqPll1Hz;
134 break;
135 case chipcHw_CLOCK_ETM:
136 pPLLReg = &pChipcHw->ETMClock;
137 vcoHz = vcoFreqPll1Hz;
138 break;
139 case chipcHw_CLOCK_USB:
140 pPLLReg = &pChipcHw->USBClock;
141 vcoHz = vcoFreqPll2Hz;
142 break;
143 case chipcHw_CLOCK_LCD:
144 pPLLReg = &pChipcHw->LCDClock;
145 vcoHz = vcoFreqPll2Hz;
146 break;
147 case chipcHw_CLOCK_APM:
148 pPLLReg = &pChipcHw->APMClock;
149 vcoHz = vcoFreqPll2Hz;
150 break;
151 case chipcHw_CLOCK_BUS:
152 pClockCtrl = &pChipcHw->ACLKClock;
153 pDependentClock = &pChipcHw->ARMClock;
154 vcoHz = vcoFreqPll1Hz;
155 dependentClockType = PLL_CLOCK;
156 break;
157 case chipcHw_CLOCK_OTP:
158 pClockCtrl = &pChipcHw->OTPClock;
159 break;
160 case chipcHw_CLOCK_I2C:
161 pClockCtrl = &pChipcHw->I2CClock;
162 break;
163 case chipcHw_CLOCK_I2S0:
164 pClockCtrl = &pChipcHw->I2S0Clock;
165 break;
166 case chipcHw_CLOCK_RTBUS:
167 pClockCtrl = &pChipcHw->RTBUSClock;
168 pDependentClock = &pChipcHw->ACLKClock;
169 dependentClockType = NON_PLL_CLOCK;
170 break;
171 case chipcHw_CLOCK_APM100:
172 pClockCtrl = &pChipcHw->APM100Clock;
173 pDependentClock = &pChipcHw->APMClock;
174 vcoHz = vcoFreqPll2Hz;
175 dependentClockType = PLL_CLOCK;
176 break;
177 case chipcHw_CLOCK_TSC:
178 pClockCtrl = &pChipcHw->TSCClock;
179 break;
180 case chipcHw_CLOCK_LED:
181 pClockCtrl = &pChipcHw->LEDClock;
182 break;
183 case chipcHw_CLOCK_I2S1:
184 pClockCtrl = &pChipcHw->I2S1Clock;
185 break;
186 }
187
188 if (pPLLReg) {
189 /* Obtain PLL clock frequency */
190 if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
191 /* Return crystal clock frequency when bypassed */
192 return chipcHw_XTAL_FREQ_Hz;
193 } else if (clock == chipcHw_CLOCK_DDR) {
194 /* DDR frequency is configured in PLLDivider register */
195 return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
196 } else {
197 /* From chip revision number B0, LCD clock is internally divided by 2 */
198 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
199 vcoHz >>= 1;
200 }
201 /* Obtain PLL clock frequency using VCO dividers */
202 return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
203 }
204 } else if (pClockCtrl) {
205 /* Obtain divider clock frequency */
206 uint32_t div;
207 uint32_t freq = 0;
208
209 if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
210 /* Return crystal clock frequency when bypassed */
211 return chipcHw_XTAL_FREQ_Hz;
212 } else if (pDependentClock) {
213 /* Identify the dependent clock frequency */
214 switch (dependentClockType) {
215 case PLL_CLOCK:
216 if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
217 /* Use crystal clock frequency when dependent PLL clock is bypassed */
218 freq = chipcHw_XTAL_FREQ_Hz;
219 } else {
220 /* Obtain PLL clock frequency using VCO dividers */
221 div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
222 freq = div ? chipcHw_divide(vcoHz, div) : 0;
223 }
224 break;
225 case NON_PLL_CLOCK:
226 if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
227 freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
228 } else {
229 if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
230 /* Use crystal clock frequency when dependent divider clock is bypassed */
231 freq = chipcHw_XTAL_FREQ_Hz;
232 } else {
233 /* Obtain divider clock frequency using XTAL dividers */
234 div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
235 freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
236 }
237 }
238 break;
239 }
240 } else {
241 /* Dependent on crystal clock */
242 freq = chipcHw_XTAL_FREQ_Hz;
243 }
244
245 div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
246 return chipcHw_divide(freq, (div ? div : 256));
247 }
248 return 0;
249}
250
251/****************************************************************************/
252/**
253* @brief Set clock fequency for miscellaneous configurable clocks
254*
255* This function sets clock frequency
256*
257* @return Configured clock frequency in Hz
258*
259*/
260/****************************************************************************/
261chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
262 uint32_t freq /* [ IN ] Clock frequency in Hz */
263 ) {
264 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
265 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
266 volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
267 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
268 uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */
269 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
270 uint32_t dependentClockType = 0;
271 uint32_t vcoHz = 0;
272 uint32_t desVcoHz = 0;
273
274 /* Get VCO frequencies */
275 if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
276 uint64_t adjustFreq = 0;
277
278 vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
279 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
280 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
281 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
282
283 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
284 adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
285 (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
286 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
287 vcoFreqPll1Hz += (uint32_t) adjustFreq;
288
289 /* Desired VCO frequency */
290 desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
291 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
292 (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
293 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
294 } else {
295 vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
296 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
297 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
298 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
299 }
300 vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
301 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
302 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
303
304 switch (clock) {
305 case chipcHw_CLOCK_DDR:
306 /* Configure the DDR_ctrl:BUS ratio settings */
307 {
308 REG_LOCAL_IRQ_SAVE;
309 /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
310 pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
311 << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
312 REG_LOCAL_IRQ_RESTORE;
313 }
314 pPLLReg = &pChipcHw->DDRClock;
315 vcoHz = vcoFreqPll1Hz;
316 desVcoHz = desVcoFreqPll1Hz;
317 break;
318 case chipcHw_CLOCK_ARM:
319 pPLLReg = &pChipcHw->ARMClock;
320 vcoHz = vcoFreqPll1Hz;
321 desVcoHz = desVcoFreqPll1Hz;
322 break;
323 case chipcHw_CLOCK_ESW:
324 pPLLReg = &pChipcHw->ESWClock;
325 vcoHz = vcoFreqPll1Hz;
326 desVcoHz = desVcoFreqPll1Hz;
327 break;
328 case chipcHw_CLOCK_VPM:
329 /* Configure the VPM:BUS ratio settings */
330 {
331 REG_LOCAL_IRQ_SAVE;
332 pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
333 << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
334 REG_LOCAL_IRQ_RESTORE;
335 }
336 pPLLReg = &pChipcHw->VPMClock;
337 vcoHz = vcoFreqPll1Hz;
338 desVcoHz = desVcoFreqPll1Hz;
339 break;
340 case chipcHw_CLOCK_ESW125:
341 pPLLReg = &pChipcHw->ESW125Clock;
342 vcoHz = vcoFreqPll1Hz;
343 desVcoHz = desVcoFreqPll1Hz;
344 break;
345 case chipcHw_CLOCK_UART:
346 pPLLReg = &pChipcHw->UARTClock;
347 vcoHz = vcoFreqPll1Hz;
348 desVcoHz = desVcoFreqPll1Hz;
349 break;
350 case chipcHw_CLOCK_SDIO0:
351 pPLLReg = &pChipcHw->SDIO0Clock;
352 vcoHz = vcoFreqPll1Hz;
353 desVcoHz = desVcoFreqPll1Hz;
354 break;
355 case chipcHw_CLOCK_SDIO1:
356 pPLLReg = &pChipcHw->SDIO1Clock;
357 vcoHz = vcoFreqPll1Hz;
358 desVcoHz = desVcoFreqPll1Hz;
359 break;
360 case chipcHw_CLOCK_SPI:
361 pPLLReg = &pChipcHw->SPIClock;
362 vcoHz = vcoFreqPll1Hz;
363 desVcoHz = desVcoFreqPll1Hz;
364 break;
365 case chipcHw_CLOCK_ETM:
366 pPLLReg = &pChipcHw->ETMClock;
367 vcoHz = vcoFreqPll1Hz;
368 desVcoHz = desVcoFreqPll1Hz;
369 break;
370 case chipcHw_CLOCK_USB:
371 pPLLReg = &pChipcHw->USBClock;
372 vcoHz = vcoFreqPll2Hz;
373 desVcoHz = vcoFreqPll2Hz;
374 break;
375 case chipcHw_CLOCK_LCD:
376 pPLLReg = &pChipcHw->LCDClock;
377 vcoHz = vcoFreqPll2Hz;
378 desVcoHz = vcoFreqPll2Hz;
379 break;
380 case chipcHw_CLOCK_APM:
381 pPLLReg = &pChipcHw->APMClock;
382 vcoHz = vcoFreqPll2Hz;
383 desVcoHz = vcoFreqPll2Hz;
384 break;
385 case chipcHw_CLOCK_BUS:
386 pClockCtrl = &pChipcHw->ACLKClock;
387 pDependentClock = &pChipcHw->ARMClock;
388 vcoHz = vcoFreqPll1Hz;
389 desVcoHz = desVcoFreqPll1Hz;
390 dependentClockType = PLL_CLOCK;
391 break;
392 case chipcHw_CLOCK_OTP:
393 pClockCtrl = &pChipcHw->OTPClock;
394 break;
395 case chipcHw_CLOCK_I2C:
396 pClockCtrl = &pChipcHw->I2CClock;
397 break;
398 case chipcHw_CLOCK_I2S0:
399 pClockCtrl = &pChipcHw->I2S0Clock;
400 break;
401 case chipcHw_CLOCK_RTBUS:
402 pClockCtrl = &pChipcHw->RTBUSClock;
403 pDependentClock = &pChipcHw->ACLKClock;
404 dependentClockType = NON_PLL_CLOCK;
405 break;
406 case chipcHw_CLOCK_APM100:
407 pClockCtrl = &pChipcHw->APM100Clock;
408 pDependentClock = &pChipcHw->APMClock;
409 vcoHz = vcoFreqPll2Hz;
410 desVcoHz = vcoFreqPll2Hz;
411 dependentClockType = PLL_CLOCK;
412 break;
413 case chipcHw_CLOCK_TSC:
414 pClockCtrl = &pChipcHw->TSCClock;
415 break;
416 case chipcHw_CLOCK_LED:
417 pClockCtrl = &pChipcHw->LEDClock;
418 break;
419 case chipcHw_CLOCK_I2S1:
420 pClockCtrl = &pChipcHw->I2S1Clock;
421 break;
422 }
423
424 if (pPLLReg) {
425 /* Select XTAL as bypass source */
426 reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
427 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
428 /* For DDR settings use only the PLL divider clock */
429 if (pPLLReg == &pChipcHw->DDRClock) {
430 /* Set M1DIV for PLL1, which controls the DDR clock */
431 reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
432 /* Calculate expected frequency */
433 freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
434 } else {
435 /* From chip revision number B0, LCD clock is internally divided by 2 */
436 if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
437 desVcoHz >>= 1;
438 vcoHz >>= 1;
439 }
440 /* Set MDIV to change the frequency */
441 reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
442 reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
443 /* Calculate expected frequency */
444 freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
445 }
446 /* Wait for for atleast 200ns as per the protocol to change frequency */
447 udelay(1);
448 /* Do not bypass */
449 reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
450 /* Return the configured frequency */
451 return freq;
452 } else if (pClockCtrl) {
453 uint32_t divider = 0;
454
455 /* Divider clock should not be bypassed */
456 reg32_modify_and(pClockCtrl,
457 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
458
459 /* Identify the clock source */
460 if (pDependentClock) {
461 switch (dependentClockType) {
462 case PLL_CLOCK:
463 divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
464 break;
465 case NON_PLL_CLOCK:
466 {
467 uint32_t sourceClock = 0;
468
469 if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
470 sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
471 } else {
472 uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
473 sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
474 }
475 divider = chipcHw_divide(sourceClock, freq);
476 }
477 break;
478 }
479 } else {
480 divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
481 }
482
483 if (divider) {
484 REG_LOCAL_IRQ_SAVE;
485 /* Set the divider to obtain the required frequency */
486 *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
487 REG_LOCAL_IRQ_RESTORE;
488 return freq;
489 }
490 }
491
492 return 0;
493}
494
495EXPORT_SYMBOL(chipcHw_setClockFrequency);
496
497/****************************************************************************/
498/**
499* @brief Set VPM clock in sync with BUS clock for Chip Rev #A0
500*
501* This function does the phase adjustment between VPM and BUS clock
502*
503* @return >= 0 : On success (# of adjustment required)
504* -1 : On failure
505*
506*/
507/****************************************************************************/
508static int vpmPhaseAlignA0(void)
509{
510 uint32_t phaseControl;
511 uint32_t phaseValue;
512 uint32_t prevPhaseComp;
513 int iter = 0;
514 int adjustCount = 0;
515 int count = 0;
516
517 for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
518 phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
519 phaseValue = 0;
520 prevPhaseComp = 0;
521
522 /* Step 1: Look for falling PH_COMP transition */
523
524 /* Read the contents of VPM Clock resgister */
525 phaseValue = pChipcHw->VPMClock;
526 do {
527 /* Store previous value of phase comparator */
528 prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
529 /* Change the value of PH_CTRL. */
530 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
531 /* Wait atleast 20 ns */
532 udelay(1);
533 /* Toggle the LOAD_CH after phase control is written. */
534 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
535 /* Read the contents of VPM Clock resgister. */
536 phaseValue = pChipcHw->VPMClock;
537
538 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
539 phaseControl = (0x3F & (phaseControl - 1));
540 } else {
541 /* Increment to the Phase count value for next write, if Phase is not stable. */
542 phaseControl = (0x3F & (phaseControl + 1));
543 }
544 /* Count number of adjustment made */
545 adjustCount++;
546 } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
547 ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && /* Look for a falling edge */
548 (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
549 );
550
551 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
552 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
553 return -1;
554 }
555
556 /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
557
558 for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
559 phaseControl = (0x3F & (phaseControl + 1));
560 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
561 /* Wait atleast 20 ns */
562 udelay(1);
563 /* Toggle the LOAD_CH after phase control is written. */
564 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
565 phaseValue = pChipcHw->VPMClock;
566 /* Count number of adjustment made */
567 adjustCount++;
568 }
569
570 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
571 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
572 return -1;
573 }
574
575 if (count != 5) {
576 /* Detected false transition */
577 continue;
578 }
579
580 /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
581
582 for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
583 phaseControl = (0x3F & (phaseControl - 1));
584 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
585 /* Wait atleast 20 ns */
586 udelay(1);
587 /* Toggle the LOAD_CH after phase control is written. */
588 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
589 phaseValue = pChipcHw->VPMClock;
590 /* Count number of adjustment made */
591 adjustCount++;
592 }
593
594 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
595 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
596 return -1;
597 }
598
599 if (count != 3) {
600 /* Detected noisy transition */
601 continue;
602 }
603
604 /* Step 4: Keep moving backward before the original transition took place. */
605
606 for (count = 0; (count < 5); count++) {
607 phaseControl = (0x3F & (phaseControl - 1));
608 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
609 /* Wait atleast 20 ns */
610 udelay(1);
611 /* Toggle the LOAD_CH after phase control is written. */
612 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
613 phaseValue = pChipcHw->VPMClock;
614 /* Count number of adjustment made */
615 adjustCount++;
616 }
617
618 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
619 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
620 return -1;
621 }
622
623 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
624 /* Detected false transition */
625 continue;
626 }
627
628 /* Step 5: Re discover the valid transition */
629
630 do {
631 /* Store previous value of phase comparator */
632 prevPhaseComp = phaseValue;
633 /* Change the value of PH_CTRL. */
634 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
635 /* Wait atleast 20 ns */
636 udelay(1);
637 /* Toggle the LOAD_CH after phase control is written. */
638 pChipcHw->VPMClock ^=
639 chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
640 /* Read the contents of VPM Clock resgister. */
641 phaseValue = pChipcHw->VPMClock;
642
643 if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
644 phaseControl = (0x3F & (phaseControl - 1));
645 } else {
646 /* Increment to the Phase count value for next write, if Phase is not stable. */
647 phaseControl = (0x3F & (phaseControl + 1));
648 }
649
650 /* Count number of adjustment made */
651 adjustCount++;
652 } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
653
654 if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
655 /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
656 return -1;
657 } else {
658 /* Valid phase must have detected */
659 break;
660 }
661 }
662
663 /* For VPM Phase should be perfectly aligned. */
664 phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
665 {
666 REG_LOCAL_IRQ_SAVE;
667
668 pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
669 /* Load new phase value */
670 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
671
672 REG_LOCAL_IRQ_RESTORE;
673 }
674 /* Return the status */
675 return (int)adjustCount;
676}
677
678/****************************************************************************/
679/**
680* @brief Set VPM clock in sync with BUS clock
681*
682* This function does the phase adjustment between VPM and BUS clock
683*
684* @return >= 0 : On success (# of adjustment required)
685* -1 : On failure
686*
687*/
688/****************************************************************************/
689int chipcHw_vpmPhaseAlign(void)
690{
691
692 if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
693 return vpmPhaseAlignA0();
694 } else {
695 uint32_t phaseControl = chipcHw_getVpmPhaseControl();
696 uint32_t phaseValue = 0;
697 int adjustCount = 0;
698
699 /* Disable VPM access */
700 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
701 /* Disable HW VPM phase alignment */
702 chipcHw_vpmHwPhaseAlignDisable();
703 /* Enable SW VPM phase alignment */
704 chipcHw_vpmSwPhaseAlignEnable();
705 /* Adjust VPM phase */
706 while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
707 phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
708
709 /* Adjust phase control value */
710 if (phaseValue > 0xF) {
711 /* Increment phase control value */
712 phaseControl++;
713 } else if (phaseValue < 0xF) {
714 /* Decrement phase control value */
715 phaseControl--;
716 } else {
717 /* Enable VPM access */
718 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
719 /* Return adjust count */
720 return adjustCount;
721 }
722 /* Change the value of PH_CTRL. */
723 reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
724 /* Wait atleast 20 ns */
725 udelay(1);
726 /* Toggle the LOAD_CH after phase control is written. */
727 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
728 /* Count adjustment */
729 adjustCount++;
730 }
731 }
732
733 /* Disable VPM access */
734 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
735 return -1;
736}
737
738/****************************************************************************/
739/**
740* @brief Local Divide function
741*
742* This function does the divide
743*
744* @return divide value
745*
746*/
747/****************************************************************************/
748static int chipcHw_divide(int num, int denom)
749{
750 int r;
751 int t = 1;
752
753 /* Shift denom and t up to the largest value to optimize algorithm */
754 /* t contains the units of each divide */
755 while ((denom & 0x40000000) == 0) { /* fails if denom=0 */
756 denom = denom << 1;
757 t = t << 1;
758 }
759
760 /* Initialize the result */
761 r = 0;
762
763 do {
764 /* Determine if there exists a positive remainder */
765 if ((num - denom) >= 0) {
766 /* Accumlate t to the result and calculate a new remainder */
767 num = num - denom;
768 r = r + t;
769 }
770 /* Continue to shift denom and shift t down to 0 */
771 denom = denom >> 1;
772 t = t >> 1;
773 } while (t != 0);
774
775 return r;
776}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
new file mode 100644
index 00000000000..367df75d4bb
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -0,0 +1,293 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw_init.c
18*
19* @brief Low level CHIPC PLL configuration functions
20*
21* @note
22*
23* These routines provide basic PLL controlling functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <csp/errno.h>
30#include <csp/stdint.h>
31#include <csp/module.h>
32
33#include <mach/csp/chipcHw_def.h>
34#include <mach/csp/chipcHw_inline.h>
35
36#include <csp/reg.h>
37#include <csp/delay.h>
38/* ---- Private Constants and Types --------------------------------------- */
39
40/*
41 Calculation for NDIV_i to obtain VCO frequency
42 -----------------------------------------------
43
44 Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
45 for Freq_vco = VCO_FREQ_MHz
46 Freq_ref = chipcHw_XTAL_FREQ_Hz
47 PLL_P1 = PLL_P2 = 1
48 and
49 PLL_NDIV_f = 0
50
51 We get:
52 PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
53
54 Calculation for PLL MDIV to obtain frequency Freq_x for channel x
55 -----------------------------------------------------------------
56 Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
57
58 PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
59*/
60
61/* ---- Private Variables ------------------------------------------------- */
62/****************************************************************************/
63/**
64* @brief Initializes the PLL2
65*
66* This function initializes the PLL2
67*
68*/
69/****************************************************************************/
70void chipcHw_pll2Enable(uint32_t vcoFreqHz)
71{
72 uint32_t pllPreDivider2 = 0;
73
74 {
75 REG_LOCAL_IRQ_SAVE;
76 pChipcHw->PLLConfig2 =
77 chipcHw_REG_PLL_CONFIG_D_RESET |
78 chipcHw_REG_PLL_CONFIG_A_RESET;
79
80 pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
81 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
82 (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
83 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
84 (chipcHw_REG_PLL_PREDIVIDER_P1 <<
85 chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
86 (chipcHw_REG_PLL_PREDIVIDER_P2 <<
87 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
88
89 /* Enable CHIPC registers to control the PLL */
90 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
91
92 /* Set pre divider to get desired VCO frequency */
93 pChipcHw->PLLPreDivider2 = pllPreDivider2;
94 /* Set NDIV Frac */
95 pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
96
97 /* This has to be removed once the default values are fixed for PLL2. */
98 pChipcHw->PLLControl12 = 0x38000700;
99 pChipcHw->PLLControl22 = 0x00000015;
100
101 /* Reset PLL2 */
102 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
103 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
104 chipcHw_REG_PLL_CONFIG_A_RESET |
105 chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
106 chipcHw_REG_PLL_CONFIG_POWER_DOWN;
107 } else {
108 pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
109 chipcHw_REG_PLL_CONFIG_A_RESET |
110 chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
111 chipcHw_REG_PLL_CONFIG_POWER_DOWN;
112 }
113 REG_LOCAL_IRQ_RESTORE;
114 }
115
116 /* Insert certain amount of delay before deasserting ARESET. */
117 udelay(1);
118
119 {
120 REG_LOCAL_IRQ_SAVE;
121 /* Remove analog reset and Power on the PLL */
122 pChipcHw->PLLConfig2 &=
123 ~(chipcHw_REG_PLL_CONFIG_A_RESET |
124 chipcHw_REG_PLL_CONFIG_POWER_DOWN);
125
126 REG_LOCAL_IRQ_RESTORE;
127
128 }
129
130 /* Wait until PLL is locked */
131 while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
132 ;
133
134 {
135 REG_LOCAL_IRQ_SAVE;
136 /* Remove digital reset */
137 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
138
139 REG_LOCAL_IRQ_RESTORE;
140 }
141}
142
143EXPORT_SYMBOL(chipcHw_pll2Enable);
144
145/****************************************************************************/
146/**
147* @brief Initializes the PLL1
148*
149* This function initializes the PLL1
150*
151*/
152/****************************************************************************/
153void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
154{
155 uint32_t pllPreDivider = 0;
156
157 {
158 REG_LOCAL_IRQ_SAVE;
159
160 pChipcHw->PLLConfig =
161 chipcHw_REG_PLL_CONFIG_D_RESET |
162 chipcHw_REG_PLL_CONFIG_A_RESET;
163 /* Setting VCO frequency */
164 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
165 pllPreDivider =
166 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
167 ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
168 1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
169 (chipcHw_REG_PLL_PREDIVIDER_P1 <<
170 chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
171 (chipcHw_REG_PLL_PREDIVIDER_P2 <<
172 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
173 } else {
174 pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
175 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
176 (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
177 chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
178 (chipcHw_REG_PLL_PREDIVIDER_P1 <<
179 chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
180 (chipcHw_REG_PLL_PREDIVIDER_P2 <<
181 chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
182 }
183
184 /* Enable CHIPC registers to control the PLL */
185 pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
186
187 /* Set pre divider to get desired VCO frequency */
188 pChipcHw->PLLPreDivider = pllPreDivider;
189 /* Set NDIV Frac */
190 if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
191 pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
192 chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
193 } else {
194 pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
195 chipcHw_REG_PLL_DIVIDER_NDIV_f;
196 }
197
198 /* Reset PLL1 */
199 if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
200 pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
201 chipcHw_REG_PLL_CONFIG_A_RESET |
202 chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
203 chipcHw_REG_PLL_CONFIG_POWER_DOWN;
204 } else {
205 pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
206 chipcHw_REG_PLL_CONFIG_A_RESET |
207 chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
208 chipcHw_REG_PLL_CONFIG_POWER_DOWN;
209 }
210
211 REG_LOCAL_IRQ_RESTORE;
212
213 /* Insert certain amount of delay before deasserting ARESET. */
214 udelay(1);
215
216 {
217 REG_LOCAL_IRQ_SAVE;
218 /* Remove analog reset and Power on the PLL */
219 pChipcHw->PLLConfig &=
220 ~(chipcHw_REG_PLL_CONFIG_A_RESET |
221 chipcHw_REG_PLL_CONFIG_POWER_DOWN);
222 REG_LOCAL_IRQ_RESTORE;
223 }
224
225 /* Wait until PLL is locked */
226 while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
227 || !(pChipcHw->
228 PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
229 ;
230
231 /* Remove digital reset */
232 {
233 REG_LOCAL_IRQ_SAVE;
234 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
235 REG_LOCAL_IRQ_RESTORE;
236 }
237 }
238}
239
240EXPORT_SYMBOL(chipcHw_pll1Enable);
241
242/****************************************************************************/
243/**
244* @brief Initializes the chipc module
245*
246* This function initializes the PLLs and core system clocks
247*
248*/
249/****************************************************************************/
250
251void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
252 ) {
253#if !(defined(__KERNEL__) && !defined(STANDALONE))
254 delay_init();
255#endif
256
257 /* Do not program PLL, when warm reset */
258 if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
259 chipcHw_pll1Enable(initParam->pllVcoFreqHz,
260 initParam->ssSupport);
261 chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
262 } else {
263 /* Clear sticky bits */
264 chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
265 }
266 /* Clear sticky bits */
267 chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
268
269 /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
270 pChipcHw->ACLKClock =
271 (pChipcHw->
272 ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
273 armBusRatio &
274 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
275
276 /* Set various core component frequencies. The order in which this is done is important for some. */
277 /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
278 /* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */
279 /* then VPM and RTBUS. */
280
281 chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
282 initParam->busClockFreqHz *
283 initParam->armBusRatio);
284 chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
285 chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
286 initParam->busClockFreqHz *
287 initParam->vpmBusRatio);
288 chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
289 initParam->busClockFreqHz *
290 initParam->ddrBusRatio);
291 chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
292 initParam->busClockFreqHz / 2);
293}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
new file mode 100644
index 00000000000..2671d8896bb
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -0,0 +1,124 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/* ---- Include Files ---------------------------------------------------- */
16#include <csp/stdint.h>
17#include <mach/csp/chipcHw_def.h>
18#include <mach/csp/chipcHw_inline.h>
19#include <csp/intcHw.h>
20#include <csp/cache.h>
21
22/* ---- Private Constants and Types --------------------------------------- */
23/* ---- Private Variables ------------------------------------------------- */
24void chipcHw_reset_run_from_aram(void);
25
26typedef void (*RUNFUNC) (void);
27
28/****************************************************************************/
29/**
30* @brief warmReset
31*
32* @note warmReset configures the clocks which are not reset back to the state
33* required to execute on reset. To do so we need to copy the code into internal
34* memory to change the ARM clock while we are not executing from DDR.
35*/
36/****************************************************************************/
37void chipcHw_reset(uint32_t mask)
38{
39 int i = 0;
40 RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
41
42 /* Disable all interrupts */
43 intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
44 intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
45 intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
46
47 {
48 REG_LOCAL_IRQ_SAVE;
49 if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
50 chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
51 }
52 /* Bypass the PLL clocks before reboot */
53 pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
54 pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
55
56 /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
57 do {
58 ((uint32_t *) MM_IO_BASE_ARAM)[i] =
59 ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
60 i++;
61 } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
62
63 CSP_CACHE_FLUSH_ALL;
64
65 /* run the function from ARAM */
66 runFunc();
67
68 /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
69 REG_LOCAL_IRQ_RESTORE;
70 }
71}
72
73/* This function must run from internal memory */
74void chipcHw_reset_run_from_aram(void)
75{
76/* Make sure, pipeline is filled with instructions coming from ARAM */
77__asm (" nop \n\t"
78 " nop \n\t"
79#if defined(__KERNEL__) && !defined(STANDALONE)
80 " MRC p15,#0x0,r0,c1,c0,#0 \n\t"
81 " BIC r0,r0,#0xd \n\t"
82 " MCR p15,#0x0,r0,c1,c0,#0 \n\t"
83 " nop \n\t"
84 " nop \n\t"
85 " nop \n\t"
86 " nop \n\t"
87 " nop \n\t"
88 " nop \n\t"
89#endif
90 " nop \n\t"
91 " nop \n\t"
92/* Bypass the ARM clock and switch to XTAL clock */
93 " MOV r2,#0x80000000 \n\t"
94 " LDR r3,[r2,#8] \n\t"
95 " ORR r3,r3,#0x20000 \n\t"
96 " STR r3,[r2,#8] \n\t"
97
98 " nop \n\t"
99 " nop \n\t"
100 " nop \n\t"
101 " nop \n\t"
102 " nop \n\t"
103 " nop \n\t"
104 " nop \n\t"
105 " nop \n\t"
106 " nop \n\t"
107 " nop \n\t"
108 " nop \n\t"
109 " nop \n\t"
110 " nop \n\t"
111 " nop \n\t"
112 " nop \n\t"
113 " nop \n\t"
114 " nop \n\t"
115 " nop \n\t"
116 " nop \n\t"
117 " nop \n\t"
118/* Issue reset */
119 " MOV r3,#0x2 \n\t"
120 " STR r3,[r2,#0x80] \n\t"
121/* End here */
122 " MOV pc,pc \n\t");
123/* 0xe1a0f00f == asm ("mov r15, r15"); */
124}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
new file mode 100644
index 00000000000..54ad964fe94
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
@@ -0,0 +1,64 @@
1/*****************************************************************************
2* Copyright 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14/****************************************************************************/
15/**
16* @file chipcHw_str.c
17*
18* @brief Contains strings which are useful to linux and csp
19*
20* @note
21*/
22/****************************************************************************/
23
24/* ---- Include Files ---------------------------------------------------- */
25
26#include <mach/csp/chipcHw_inline.h>
27
28/* ---- Private Constants and Types --------------------------------------- */
29
30static const char *gMuxStr[] = {
31 "GPIO", /* 0 */
32 "KeyPad", /* 1 */
33 "I2C-Host", /* 2 */
34 "SPI", /* 3 */
35 "Uart", /* 4 */
36 "LED-Mtx-P", /* 5 */
37 "LED-Mtx-S", /* 6 */
38 "SDIO-0", /* 7 */
39 "SDIO-1", /* 8 */
40 "PCM", /* 9 */
41 "I2S", /* 10 */
42 "ETM", /* 11 */
43 "Debug", /* 12 */
44 "Misc", /* 13 */
45 "0xE", /* 14 */
46 "0xF", /* 15 */
47};
48
49/****************************************************************************/
50/**
51* @brief Retrieves a string representation of the mux setting for a pin.
52*
53* @return Pointer to a character string.
54*/
55/****************************************************************************/
56
57const char *chipcHw_getGpioPinFunctionStr(int pin)
58{
59 if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
60 return "";
61 }
62
63 return gMuxStr[chipcHw_getGpioPinFunction(pin)];
64}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
new file mode 100644
index 00000000000..fb1104fe56b
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/Makefile
@@ -0,0 +1 @@
obj-y += dmacHw.o dmacHw_extra.o \ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
new file mode 100644
index 00000000000..6b9be2e98e5
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -0,0 +1,917 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw.c
18*
19* @brief Low level DMA controller driver routines
20*
21* @note
22*
23* These routines provide basic DMA functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28#include <csp/stdint.h>
29#include <csp/string.h>
30#include <stddef.h>
31
32#include <csp/dmacHw.h>
33#include <mach/csp/dmacHw_reg.h>
34#include <mach/csp/dmacHw_priv.h>
35#include <mach/csp/chipcHw_inline.h>
36
37/* ---- External Function Prototypes ------------------------------------- */
38
39/* Allocate DMA control blocks */
40dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
41
42uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
43uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
44
45/****************************************************************************/
46/**
47* @brief Get maximum FIFO for a DMA channel
48*
49* @return Maximum allowable FIFO size
50*
51*
52*/
53/****************************************************************************/
54static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
55 ) {
56 uint32_t val = 0;
57 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
58 dmacHw_MISC_t *pMiscReg =
59 (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
60
61 switch (pCblk->channel) {
62 case 0:
63 val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
64 break;
65 case 1:
66 val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
67 break;
68 case 2:
69 val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
70 break;
71 case 3:
72 val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
73 break;
74 case 4:
75 val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
76 break;
77 case 5:
78 val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
79 break;
80 case 6:
81 val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
82 break;
83 case 7:
84 val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
85 break;
86 }
87
88 if (val <= 0x4) {
89 return 8 << val;
90 } else {
91 dmacHw_ASSERT(0);
92 }
93 return 0;
94}
95
96/****************************************************************************/
97/**
98* @brief Program channel register to initiate transfer
99*
100* @return void
101*
102*
103* @note
104* - Descriptor buffer MUST ALWAYS be flushed before calling this function
105* - This function should also be called from ISR to program the channel with
106* pending descriptors
107*/
108/****************************************************************************/
109void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
110 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
111 void *pDescriptor /* [ IN ] Descriptor buffer */
112 ) {
113 dmacHw_DESC_RING_t *pRing;
114 dmacHw_DESC_t *pProg;
115 dmacHw_CBLK_t *pCblk;
116
117 pCblk = dmacHw_HANDLE_TO_CBLK(handle);
118 pRing = dmacHw_GET_DESC_RING(pDescriptor);
119
120 if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
121 /* Not safe yet to program the channel */
122 return;
123 }
124
125 if (pCblk->varDataStarted) {
126 if (pCblk->descUpdated) {
127 pCblk->descUpdated = 0;
128 pProg =
129 (dmacHw_DESC_t *) ((uint32_t)
130 dmacHw_REG_LLP(pCblk->module,
131 pCblk->channel) +
132 pRing->virt2PhyOffset);
133
134 /* Load descriptor if not loaded */
135 if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
136 dmacHw_SET_SAR(pCblk->module, pCblk->channel,
137 pProg->sar);
138 dmacHw_SET_DAR(pCblk->module, pCblk->channel,
139 pProg->dar);
140 dmacHw_REG_CTL_LO(pCblk->module,
141 pCblk->channel) =
142 pProg->ctl.lo;
143 dmacHw_REG_CTL_HI(pCblk->module,
144 pCblk->channel) =
145 pProg->ctl.hi;
146 } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
147 /* Return as end descriptor is processed */
148 return;
149 } else {
150 dmacHw_ASSERT(0);
151 }
152 } else {
153 return;
154 }
155 } else {
156 if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
157 /* Do not make a single chain, rather process one descriptor at a time */
158 pProg = pRing->pHead;
159 /* Point to the next descriptor for next iteration */
160 dmacHw_NEXT_DESC(pRing, pHead);
161 } else {
162 /* Return if no more pending descriptor */
163 if (pRing->pEnd == NULL) {
164 return;
165 }
166
167 pProg = pRing->pProg;
168 if (pConfig->transferMode ==
169 dmacHw_TRANSFER_MODE_CONTINUOUS) {
170 /* Make sure a complete ring can be formed */
171 dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
172 llp == pRing->pProg);
173 /* Make sure pProg pointing to the pHead */
174 dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
175 pRing->pHead);
176 /* Make a complete ring */
177 do {
178 pRing->pProg->ctl.lo |=
179 (dmacHw_REG_CTL_LLP_DST_EN |
180 dmacHw_REG_CTL_LLP_SRC_EN);
181 pRing->pProg =
182 (dmacHw_DESC_t *) pRing->pProg->llp;
183 } while (pRing->pProg != pRing->pHead);
184 } else {
185 /* Make a single long chain */
186 while (pRing->pProg != pRing->pEnd) {
187 pRing->pProg->ctl.lo |=
188 (dmacHw_REG_CTL_LLP_DST_EN |
189 dmacHw_REG_CTL_LLP_SRC_EN);
190 pRing->pProg =
191 (dmacHw_DESC_t *) pRing->pProg->llp;
192 }
193 }
194 }
195
196 /* Program the channel registers */
197 dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
198 dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
199 dmacHw_SET_LLP(pCblk->module, pCblk->channel,
200 (uint32_t) pProg - pRing->virt2PhyOffset);
201 dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
202 pProg->ctl.lo;
203 dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
204 pProg->ctl.hi;
205 if (pRing->pEnd) {
206 /* Remember the descriptor to use next */
207 pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
208 }
209 /* Indicate no more pending descriptor */
210 pRing->pEnd = (dmacHw_DESC_t *) NULL;
211 }
212 /* Start DMA operation */
213 dmacHw_DMA_START(pCblk->module, pCblk->channel);
214}
215
216/****************************************************************************/
217/**
218* @brief Initializes DMA
219*
220* This function initializes DMA CSP driver
221*
222* @note
223* Must be called before using any DMA channel
224*/
225/****************************************************************************/
226void dmacHw_initDma(void)
227{
228
229 uint32_t i = 0;
230
231 dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
232 dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
233
234 /* Enable access to the DMA block */
235 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
236 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
237
238 if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
239 dmacHw_ASSERT(0);
240 }
241
242 memset((void *)dmacHw_gCblk, 0,
243 sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
244 for (i = 0; i < dmaChannelCount_0; i++) {
245 dmacHw_gCblk[i].module = 0;
246 dmacHw_gCblk[i].channel = i;
247 }
248 for (i = 0; i < dmaChannelCount_1; i++) {
249 dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
250 dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
251 }
252}
253
254/****************************************************************************/
255/**
256* @brief Exit function for DMA
257*
258* This function isolates DMA from the system
259*
260*/
261/****************************************************************************/
262void dmacHw_exitDma(void)
263{
264 /* Disable access to the DMA block */
265 chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
266 chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
267}
268
269/****************************************************************************/
270/**
271* @brief Gets a handle to a DMA channel
272*
273* This function returns a handle, representing a control block of a particular DMA channel
274*
275* @return -1 - On Failure
276* handle - On Success, representing a channel control block
277*
278* @note
279* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
280*/
281/****************************************************************************/
282dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
283 ) {
284 int idx;
285
286 switch ((channelId >> 8)) {
287 case 0:
288 dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
289 idx = (channelId & 0xff);
290 break;
291 case 1:
292 dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
293 idx = dmaChannelCount_0 + (channelId & 0xff);
294 break;
295 default:
296 dmacHw_ASSERT(0);
297 return (dmacHw_HANDLE_t) -1;
298 }
299
300 return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
301}
302
303/****************************************************************************/
304/**
305* @brief Initializes a DMA channel for use
306*
307* This function initializes and resets a DMA channel for use
308*
309* @return -1 - On Failure
310* 0 - On Success
311*
312* @note
313* None
314*/
315/****************************************************************************/
316int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
317 ) {
318 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
319 int module = pCblk->module;
320 int channel = pCblk->channel;
321
322 /* Reinitialize the control block */
323 memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
324 pCblk->module = module;
325 pCblk->channel = channel;
326
327 /* Enable DMA controller */
328 dmacHw_DMA_ENABLE(pCblk->module);
329 /* Reset DMA channel */
330 dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
331 dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
332 dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
333 dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
334
335 /* Clear all raw interrupt status */
336 dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
337 dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
338 dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
339
340 /* Mask event specific interrupts */
341 dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
342 dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
343 dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
344 dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
345 dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
346
347 return 0;
348}
349
350/****************************************************************************/
351/**
352* @brief Finds amount of memory required to form a descriptor ring
353*
354*
355* @return Number of bytes required to form a descriptor ring
356*
357*
358*/
359/****************************************************************************/
360uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
361 ) {
362 /* Need extra 4 byte to ensure 32 bit alignment */
363 return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
364 sizeof(uint32_t);
365}
366
367/****************************************************************************/
368/**
369* @brief Initializes descriptor ring
370*
371* This function will initializes the descriptor ring of a DMA channel
372*
373*
374* @return -1 - On failure
375* 0 - On success
376* @note
377* - "len" parameter should be obtained from "dmacHw_descriptorLen"
378* - Descriptor buffer MUST be 32 bit aligned and uncached as it is
379* accessed by ARM and DMA
380*/
381/****************************************************************************/
382int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
383 uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
384 uint32_t len, /* [ IN ] Size of the pBuf */
385 uint32_t num /* [ IN ] Number of descriptor in the ring */
386 ) {
387 uint32_t i;
388 dmacHw_DESC_RING_t *pRing;
389 dmacHw_DESC_t *pDesc;
390
391 /* Check the alignment of the descriptor */
392 if ((uint32_t) pDescriptorVirt & 0x00000003) {
393 dmacHw_ASSERT(0);
394 return -1;
395 }
396
397 /* Check if enough space has been allocated for descriptor ring */
398 if (len < dmacHw_descriptorLen(num)) {
399 return -1;
400 }
401
402 pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
403 pRing->pHead =
404 (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
405 pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
406 pRing->pProg = dmacHw_DESC_INIT;
407 /* Initialize link item chain, starting from the head */
408 pDesc = pRing->pHead;
409 /* Find the offset between virtual to physical address */
410 pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
411
412 /* Form the descriptor ring */
413 for (i = 0; i < num - 1; i++) {
414 /* Clear link list item */
415 memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
416 /* Point to the next item in the physical address */
417 pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
418 /* Point to the next item in the virtual address */
419 pDesc->llp = (uint32_t) (pDesc + 1);
420 /* Mark descriptor is ready to use */
421 pDesc->ctl.hi = dmacHw_DESC_FREE;
422 /* Look into next link list item */
423 pDesc++;
424 }
425
426 /* Clear last link list item */
427 memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
428 /* Last item pointing to the first item in the
429 physical address to complete the ring */
430 pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
431 /* Last item pointing to the first item in the
432 virtual address to complete the ring
433 */
434 pDesc->llp = (uint32_t) pRing->pHead;
435 /* Mark descriptor is ready to use */
436 pDesc->ctl.hi = dmacHw_DESC_FREE;
437 /* Set the number of descriptors in the ring */
438 pRing->num = num;
439 return 0;
440}
441
442/****************************************************************************/
443/**
444* @brief Configure DMA channel
445*
446* @return 0 : On success
447* -1 : On failure
448*/
449/****************************************************************************/
450int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
451 dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
452 ) {
453 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
454 uint32_t cfgHigh = 0;
455 int srcTrSize;
456 int dstTrSize;
457
458 pCblk->varDataStarted = 0;
459 pCblk->userData = NULL;
460
461 /* Configure
462 - Burst transaction when enough data in available in FIFO
463 - AHB Access protection 1
464 - Source and destination peripheral ports
465 */
466 cfgHigh =
467 dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
468 dmacHw_SRC_PERI_INTF(pConfig->
469 srcPeripheralPort) |
470 dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
471 /* Set priority */
472 dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
473 pConfig->channelPriority);
474
475 if (pConfig->dstStatusRegisterAddress != 0) {
476 /* Destination status update enable */
477 cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
478 /* Configure status registers */
479 dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
480 pConfig->dstStatusRegisterAddress);
481 }
482
483 if (pConfig->srcStatusRegisterAddress != 0) {
484 /* Source status update enable */
485 cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
486 /* Source status update enable */
487 dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
488 pConfig->srcStatusRegisterAddress);
489 }
490 /* Configure the config high register */
491 dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
492
493 /* Clear all raw interrupt status */
494 dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
495 dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
496 dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
497
498 /* Configure block interrupt */
499 if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
500 dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
501 } else {
502 dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
503 }
504 /* Configure complete transfer interrupt */
505 if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
506 dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
507 } else {
508 dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
509 }
510 /* Configure error interrupt */
511 if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
512 dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
513 } else {
514 dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
515 }
516 /* Configure gather register */
517 if (pConfig->srcGatherWidth) {
518 srcTrSize =
519 dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
520 if (!
521 ((pConfig->srcGatherWidth % srcTrSize)
522 && (pConfig->srcGatherJump % srcTrSize))) {
523 dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
524 ((pConfig->srcGatherWidth /
525 srcTrSize) << 20) | (pConfig->srcGatherJump /
526 srcTrSize);
527 } else {
528 return -1;
529 }
530 }
531 /* Configure scatter register */
532 if (pConfig->dstScatterWidth) {
533 dstTrSize =
534 dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
535 if (!
536 ((pConfig->dstScatterWidth % dstTrSize)
537 && (pConfig->dstScatterJump % dstTrSize))) {
538 dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
539 ((pConfig->dstScatterWidth /
540 dstTrSize) << 20) | (pConfig->dstScatterJump /
541 dstTrSize);
542 } else {
543 return -1;
544 }
545 }
546 return 0;
547}
548
549/****************************************************************************/
550/**
551* @brief Indicates whether DMA transfer is in progress or completed
552*
553* @return DMA transfer status
554* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
555* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
556* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
557*
558*/
559/****************************************************************************/
560dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
561 ) {
562 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
563
564 if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
565 return dmacHw_TRANSFER_STATUS_BUSY;
566 } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
567 (0x00000001 << pCblk->channel)) {
568 return dmacHw_TRANSFER_STATUS_ERROR;
569 }
570
571 return dmacHw_TRANSFER_STATUS_DONE;
572}
573
574/****************************************************************************/
575/**
576* @brief Set descriptors for known data length
577*
578* When DMA has to work as a flow controller, this function prepares the
579* descriptor chain to transfer data
580*
581* from:
582* - Memory to memory
583* - Peripheral to memory
584* - Memory to Peripheral
585* - Peripheral to Peripheral
586*
587* @return -1 - On failure
588* 0 - On success
589*
590*/
591/****************************************************************************/
592int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
593 void *pDescriptor, /* [ IN ] Descriptor buffer */
594 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
595 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
596 size_t dataLen /* [ IN ] Data length in bytes */
597 ) {
598 dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
599 dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
600 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
601 dmacHw_DESC_t *pStart;
602 dmacHw_DESC_t *pProg;
603 int srcTs = 0;
604 int blkTs = 0;
605 int oddSize = 0;
606 int descCount = 0;
607 int count = 0;
608 int dstTrSize = 0;
609 int srcTrSize = 0;
610 uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
611
612 dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
613 srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
614
615 /* Skip Tx if buffer is NULL or length is unknown */
616 if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
617 /* Do not initiate transfer */
618 return -1;
619 }
620
621 /* Ensure scatter and gather are transaction aligned */
622 if ((pConfig->srcGatherWidth % srcTrSize)
623 || (pConfig->dstScatterWidth % dstTrSize)) {
624 return -2;
625 }
626
627 /*
628 Background 1: DMAC can not perform DMA if source and destination addresses are
629 not properly aligned with the channel's transaction width. So, for successful
630 DMA transfer, transaction width must be set according to the alignment of the
631 source and destination address.
632 */
633
634 /* Adjust destination transaction width if destination address is not aligned properly */
635 dstTrWidth = pConfig->dstMaxTransactionWidth;
636 while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
637 dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
638 dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
639 }
640
641 /* Adjust source transaction width if source address is not aligned properly */
642 srcTrWidth = pConfig->srcMaxTransactionWidth;
643 while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
644 srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
645 srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
646 }
647
648 /* Find the maximum transaction per descriptor */
649 if (pConfig->maxDataPerBlock
650 && ((pConfig->maxDataPerBlock / srcTrSize) <
651 dmacHw_MAX_BLOCKSIZE)) {
652 maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
653 }
654
655 /* Find number of source transactions needed to complete the DMA transfer */
656 srcTs = dataLen / srcTrSize;
657 /* Find the odd number of bytes that need to be transferred as single byte transaction width */
658 if (srcTs && (dstTrSize > srcTrSize)) {
659 oddSize = dataLen % dstTrSize;
660 /* Adjust source transaction count due to "oddSize" */
661 srcTs = srcTs - (oddSize / srcTrSize);
662 } else {
663 oddSize = dataLen % srcTrSize;
664 }
665 /* Adjust "descCount" due to "oddSize" */
666 if (oddSize) {
667 descCount++;
668 }
669 /* Find the number of descriptor needed for total "srcTs" */
670 if (srcTs) {
671 descCount += ((srcTs - 1) / maxBlockSize) + 1;
672 }
673
674 /* Check the availability of "descCount" discriptors in the ring */
675 pProg = pRing->pHead;
676 for (count = 0; (descCount <= pRing->num) && (count < descCount);
677 count++) {
678 if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
679 /* Sufficient descriptors are not available */
680 return -3;
681 }
682 pProg = (dmacHw_DESC_t *) pProg->llp;
683 }
684
685 /* Remember the link list item to program the channel registers */
686 pStart = pProg = pRing->pHead;
687 /* Make a link list with "descCount(=count)" number of descriptors */
688 while (count) {
689 /* Reset channel control information */
690 pProg->ctl.lo = 0;
691 /* Enable source gather if configured */
692 if (pConfig->srcGatherWidth) {
693 pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
694 }
695 /* Enable destination scatter if configured */
696 if (pConfig->dstScatterWidth) {
697 pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
698 }
699 /* Set source and destination address */
700 pProg->sar = (uint32_t) pSrcAddr;
701 pProg->dar = (uint32_t) pDstAddr;
702 /* Use "devCtl" to mark that user memory need to be freed later if needed */
703 if (pProg == pRing->pHead) {
704 pProg->devCtl = dmacHw_FREE_USER_MEMORY;
705 } else {
706 pProg->devCtl = 0;
707 }
708
709 blkTs = srcTs;
710
711 /* Special treatmeant for last descriptor */
712 if (count == 1) {
713 /* Mark the last descriptor */
714 pProg->ctl.lo &=
715 ~(dmacHw_REG_CTL_LLP_DST_EN |
716 dmacHw_REG_CTL_LLP_SRC_EN);
717 /* Treatment for odd data bytes */
718 if (oddSize) {
719 /* Adjust for single byte transaction width */
720 switch (pConfig->transferType) {
721 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
722 dstTrWidth =
723 dmacHw_DST_TRANSACTION_WIDTH_8;
724 blkTs =
725 (oddSize / srcTrSize) +
726 ((oddSize % srcTrSize) ? 1 : 0);
727 break;
728 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
729 srcTrWidth =
730 dmacHw_SRC_TRANSACTION_WIDTH_8;
731 blkTs = oddSize;
732 break;
733 case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
734 srcTrWidth =
735 dmacHw_SRC_TRANSACTION_WIDTH_8;
736 dstTrWidth =
737 dmacHw_DST_TRANSACTION_WIDTH_8;
738 blkTs = oddSize;
739 break;
740 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
741 /* Do not adjust the transaction width */
742 break;
743 }
744 } else {
745 srcTs -= blkTs;
746 }
747 } else {
748 if (srcTs / maxBlockSize) {
749 blkTs = maxBlockSize;
750 }
751 /* Remaining source transactions for next iteration */
752 srcTs -= blkTs;
753 }
754 /* Must have a valid source transactions */
755 dmacHw_ASSERT(blkTs > 0);
756 /* Set control information */
757 if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
758 pProg->ctl.lo |= pConfig->transferType |
759 pConfig->srcUpdate |
760 pConfig->dstUpdate |
761 srcTrWidth |
762 dstTrWidth |
763 pConfig->srcMaxBurstWidth |
764 pConfig->dstMaxBurstWidth |
765 pConfig->srcMasterInterface |
766 pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
767 } else {
768 uint32_t transferType = 0;
769 switch (pConfig->transferType) {
770 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
771 transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
772 break;
773 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
774 transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
775 break;
776 default:
777 dmacHw_ASSERT(0);
778 }
779 pProg->ctl.lo |= transferType |
780 pConfig->srcUpdate |
781 pConfig->dstUpdate |
782 srcTrWidth |
783 dstTrWidth |
784 pConfig->srcMaxBurstWidth |
785 pConfig->dstMaxBurstWidth |
786 pConfig->srcMasterInterface |
787 pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
788 }
789
790 /* Set block transaction size */
791 pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
792 /* Look for next descriptor */
793 if (count > 1) {
794 /* Point to the next descriptor */
795 pProg = (dmacHw_DESC_t *) pProg->llp;
796
797 /* Update source and destination address for next iteration */
798 switch (pConfig->transferType) {
799 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
800 if (pConfig->dstScatterWidth) {
801 pDstAddr =
802 (char *)pDstAddr +
803 blkTs * srcTrSize +
804 (((blkTs * srcTrSize) /
805 pConfig->dstScatterWidth) *
806 pConfig->dstScatterJump);
807 } else {
808 pDstAddr =
809 (char *)pDstAddr +
810 blkTs * srcTrSize;
811 }
812 break;
813 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
814 if (pConfig->srcGatherWidth) {
815 pSrcAddr =
816 (char *)pDstAddr +
817 blkTs * srcTrSize +
818 (((blkTs * srcTrSize) /
819 pConfig->srcGatherWidth) *
820 pConfig->srcGatherJump);
821 } else {
822 pSrcAddr =
823 (char *)pSrcAddr +
824 blkTs * srcTrSize;
825 }
826 break;
827 case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
828 if (pConfig->dstScatterWidth) {
829 pDstAddr =
830 (char *)pDstAddr +
831 blkTs * srcTrSize +
832 (((blkTs * srcTrSize) /
833 pConfig->dstScatterWidth) *
834 pConfig->dstScatterJump);
835 } else {
836 pDstAddr =
837 (char *)pDstAddr +
838 blkTs * srcTrSize;
839 }
840
841 if (pConfig->srcGatherWidth) {
842 pSrcAddr =
843 (char *)pDstAddr +
844 blkTs * srcTrSize +
845 (((blkTs * srcTrSize) /
846 pConfig->srcGatherWidth) *
847 pConfig->srcGatherJump);
848 } else {
849 pSrcAddr =
850 (char *)pSrcAddr +
851 blkTs * srcTrSize;
852 }
853 break;
854 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
855 /* Do not adjust the address */
856 break;
857 default:
858 dmacHw_ASSERT(0);
859 }
860 } else {
861 /* At the end of transfer "srcTs" must be zero */
862 dmacHw_ASSERT(srcTs == 0);
863 }
864 count--;
865 }
866
867 /* Remember the descriptor to initialize the registers */
868 if (pRing->pProg == dmacHw_DESC_INIT) {
869 pRing->pProg = pStart;
870 }
871 /* Indicate that the descriptor is updated */
872 pRing->pEnd = pProg;
873 /* Head pointing to the next descriptor */
874 pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
875 /* Update Tail pointer if destination is a peripheral,
876 because no one is going to read from the pTail
877 */
878 if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
879 pRing->pTail = pRing->pHead;
880 }
881 return 0;
882}
883
884/****************************************************************************/
885/**
886* @brief Provides DMA controller attributes
887*
888*
889* @return DMA controller attributes
890*
891* @note
892* None
893*/
894/****************************************************************************/
895uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
896 dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
897 ) {
898 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
899
900 switch (attr) {
901 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
902 return dmacHw_GET_NUM_CHANNEL(pCblk->module);
903 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
904 return (1 <<
905 (dmacHw_GET_MAX_BLOCK_SIZE
906 (pCblk->module, pCblk->module) + 2)) - 8;
907 case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
908 return dmacHw_GET_NUM_INTERFACE(pCblk->module);
909 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
910 return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
911 pCblk->channel);
912 case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
913 return GetFifoSize(handle);
914 }
915 dmacHw_ASSERT(0);
916 return 0;
917}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
new file mode 100644
index 00000000000..a1f328357aa
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -0,0 +1,1017 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_extra.c
18*
19* @brief Extra Low level DMA controller driver routines
20*
21* @note
22*
23* These routines provide basic DMA functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <csp/stdint.h>
30#include <stddef.h>
31
32#include <csp/dmacHw.h>
33#include <mach/csp/dmacHw_reg.h>
34#include <mach/csp/dmacHw_priv.h>
35
36extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT]; /* Declared in dmacHw.c */
37
38/* ---- External Function Prototypes ------------------------------------- */
39
40/* ---- Internal Use Function Prototypes --------------------------------- */
41/****************************************************************************/
42/**
43* @brief Overwrites data length in the descriptor
44*
45* This function overwrites data length in the descriptor
46*
47*
48* @return void
49*
50* @note
51* This is only used for PCM channel
52*/
53/****************************************************************************/
54void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
55 void *pDescriptor, /* [ IN ] Descriptor buffer */
56 size_t dataLen /* [ IN ] Data length in bytes */
57 );
58
59/****************************************************************************/
60/**
61* @brief Helper function to display DMA registers
62*
63* @return void
64*
65*
66* @note
67* None
68*/
69/****************************************************************************/
70static void DisplayRegisterContents(int module, /* [ IN ] DMA Controller unit (0-1) */
71 int channel, /* [ IN ] DMA Channel (0-7) / -1(all) */
72 int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */
73 ) {
74 int chan;
75
76 (*fpPrint) ("Displaying register content \n\n");
77 (*fpPrint) ("Module %d: Interrupt raw transfer 0x%X\n",
78 module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
79 (*fpPrint) ("Module %d: Interrupt raw block 0x%X\n",
80 module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
81 (*fpPrint) ("Module %d: Interrupt raw src transfer 0x%X\n",
82 module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
83 (*fpPrint) ("Module %d: Interrupt raw dst transfer 0x%X\n",
84 module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
85 (*fpPrint) ("Module %d: Interrupt raw error 0x%X\n",
86 module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
87 (*fpPrint) ("--------------------------------------------------\n");
88 (*fpPrint) ("Module %d: Interrupt stat transfer 0x%X\n",
89 module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
90 (*fpPrint) ("Module %d: Interrupt stat block 0x%X\n",
91 module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
92 (*fpPrint) ("Module %d: Interrupt stat src transfer 0x%X\n",
93 module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
94 (*fpPrint) ("Module %d: Interrupt stat dst transfer 0x%X\n",
95 module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
96 (*fpPrint) ("Module %d: Interrupt stat error 0x%X\n",
97 module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
98 (*fpPrint) ("--------------------------------------------------\n");
99 (*fpPrint) ("Module %d: Interrupt mask transfer 0x%X\n",
100 module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
101 (*fpPrint) ("Module %d: Interrupt mask block 0x%X\n",
102 module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
103 (*fpPrint) ("Module %d: Interrupt mask src transfer 0x%X\n",
104 module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
105 (*fpPrint) ("Module %d: Interrupt mask dst transfer 0x%X\n",
106 module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
107 (*fpPrint) ("Module %d: Interrupt mask error 0x%X\n",
108 module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
109 (*fpPrint) ("--------------------------------------------------\n");
110 (*fpPrint) ("Module %d: Interrupt clear transfer 0x%X\n",
111 module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
112 (*fpPrint) ("Module %d: Interrupt clear block 0x%X\n",
113 module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
114 (*fpPrint) ("Module %d: Interrupt clear src transfer 0x%X\n",
115 module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
116 (*fpPrint) ("Module %d: Interrupt clear dst transfer 0x%X\n",
117 module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
118 (*fpPrint) ("Module %d: Interrupt clear error 0x%X\n",
119 module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
120 (*fpPrint) ("--------------------------------------------------\n");
121 (*fpPrint) ("Module %d: SW source req 0x%X\n",
122 module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
123 (*fpPrint) ("Module %d: SW dest req 0x%X\n",
124 module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
125 (*fpPrint) ("Module %d: SW source signal 0x%X\n",
126 module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
127 (*fpPrint) ("Module %d: SW dest signal 0x%X\n",
128 module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
129 (*fpPrint) ("Module %d: SW source last 0x%X\n",
130 module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
131 (*fpPrint) ("Module %d: SW dest last 0x%X\n",
132 module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
133 (*fpPrint) ("--------------------------------------------------\n");
134 (*fpPrint) ("Module %d: misc config 0x%X\n",
135 module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
136 (*fpPrint) ("Module %d: misc channel enable 0x%X\n",
137 module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
138 (*fpPrint) ("Module %d: misc ID 0x%X\n",
139 module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
140 (*fpPrint) ("Module %d: misc test 0x%X\n",
141 module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
142
143 if (channel == -1) {
144 for (chan = 0; chan < 8; chan++) {
145 (*fpPrint)
146 ("--------------------------------------------------\n");
147 (*fpPrint)
148 ("Module %d: Channel %d Source 0x%X\n",
149 module, chan,
150 (uint32_t) (dmacHw_REG_SAR(module, chan)));
151 (*fpPrint)
152 ("Module %d: Channel %d Destination 0x%X\n",
153 module, chan,
154 (uint32_t) (dmacHw_REG_DAR(module, chan)));
155 (*fpPrint)
156 ("Module %d: Channel %d LLP 0x%X\n",
157 module, chan,
158 (uint32_t) (dmacHw_REG_LLP(module, chan)));
159 (*fpPrint)
160 ("Module %d: Channel %d Control (LO) 0x%X\n",
161 module, chan,
162 (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
163 (*fpPrint)
164 ("Module %d: Channel %d Control (HI) 0x%X\n",
165 module, chan,
166 (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
167 (*fpPrint)
168 ("Module %d: Channel %d Source Stats 0x%X\n",
169 module, chan,
170 (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
171 (*fpPrint)
172 ("Module %d: Channel %d Dest Stats 0x%X\n",
173 module, chan,
174 (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
175 (*fpPrint)
176 ("Module %d: Channel %d Source Stats Addr 0x%X\n",
177 module, chan,
178 (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
179 (*fpPrint)
180 ("Module %d: Channel %d Dest Stats Addr 0x%X\n",
181 module, chan,
182 (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
183 (*fpPrint)
184 ("Module %d: Channel %d Config (LO) 0x%X\n",
185 module, chan,
186 (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
187 (*fpPrint)
188 ("Module %d: Channel %d Config (HI) 0x%X\n",
189 module, chan,
190 (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
191 }
192 } else {
193 chan = channel;
194 (*fpPrint)
195 ("--------------------------------------------------\n");
196 (*fpPrint)
197 ("Module %d: Channel %d Source 0x%X\n",
198 module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
199 (*fpPrint)
200 ("Module %d: Channel %d Destination 0x%X\n",
201 module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
202 (*fpPrint)
203 ("Module %d: Channel %d LLP 0x%X\n",
204 module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
205 (*fpPrint)
206 ("Module %d: Channel %d Control (LO) 0x%X\n",
207 module, chan,
208 (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
209 (*fpPrint)
210 ("Module %d: Channel %d Control (HI) 0x%X\n",
211 module, chan,
212 (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
213 (*fpPrint)
214 ("Module %d: Channel %d Source Stats 0x%X\n",
215 module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
216 (*fpPrint)
217 ("Module %d: Channel %d Dest Stats 0x%X\n",
218 module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
219 (*fpPrint)
220 ("Module %d: Channel %d Source Stats Addr 0x%X\n",
221 module, chan,
222 (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
223 (*fpPrint)
224 ("Module %d: Channel %d Dest Stats Addr 0x%X\n",
225 module, chan,
226 (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
227 (*fpPrint)
228 ("Module %d: Channel %d Config (LO) 0x%X\n",
229 module, chan,
230 (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
231 (*fpPrint)
232 ("Module %d: Channel %d Config (HI) 0x%X\n",
233 module, chan,
234 (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
235 }
236}
237
238/****************************************************************************/
239/**
240* @brief Helper function to display descriptor ring
241*
242* @return void
243*
244*
245* @note
246* None
247*/
248/****************************************************************************/
249static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */
250 int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */
251 ) {
252 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
253 dmacHw_DESC_t *pStart;
254
255 if (pRing->pHead == NULL) {
256 return;
257 }
258
259 pStart = pRing->pHead;
260
261 while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
262 if (pStart == pRing->pHead) {
263 (*fpPrint) ("Head\n");
264 }
265 if (pStart == pRing->pTail) {
266 (*fpPrint) ("Tail\n");
267 }
268 if (pStart == pRing->pProg) {
269 (*fpPrint) ("Prog\n");
270 }
271 if (pStart == pRing->pEnd) {
272 (*fpPrint) ("End\n");
273 }
274 if (pStart == pRing->pFree) {
275 (*fpPrint) ("Free\n");
276 }
277 (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
278 (*fpPrint) ("sar 0x%0X\n", pStart->sar);
279 (*fpPrint) ("dar 0x%0X\n", pStart->dar);
280 (*fpPrint) ("llp 0x%0X\n", pStart->llp);
281 (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
282 (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
283 (*fpPrint) ("sstat 0x%0X\n", pStart->sstat);
284 (*fpPrint) ("dstat 0x%0X\n", pStart->dstat);
285 (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
286
287 pStart = (dmacHw_DESC_t *) pStart->llp;
288 }
289 if (pStart == pRing->pHead) {
290 (*fpPrint) ("Head\n");
291 }
292 if (pStart == pRing->pTail) {
293 (*fpPrint) ("Tail\n");
294 }
295 if (pStart == pRing->pProg) {
296 (*fpPrint) ("Prog\n");
297 }
298 if (pStart == pRing->pEnd) {
299 (*fpPrint) ("End\n");
300 }
301 if (pStart == pRing->pFree) {
302 (*fpPrint) ("Free\n");
303 }
304 (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
305 (*fpPrint) ("sar 0x%0X\n", pStart->sar);
306 (*fpPrint) ("dar 0x%0X\n", pStart->dar);
307 (*fpPrint) ("llp 0x%0X\n", pStart->llp);
308 (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
309 (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
310 (*fpPrint) ("sstat 0x%0X\n", pStart->sstat);
311 (*fpPrint) ("dstat 0x%0X\n", pStart->dstat);
312 (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
313}
314
315/****************************************************************************/
316/**
317* @brief Check if DMA channel is the flow controller
318*
319* @return 1 : If DMA is a flow controller
320* 0 : Peripheral is the flow controller
321*
322* @note
323* None
324*/
325/****************************************************************************/
326static inline int DmaIsFlowController(void *pDescriptor /* [ IN ] Descriptor buffer */
327 ) {
328 uint32_t ttfc =
329 (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
330 lo & dmacHw_REG_CTL_TTFC_MASK;
331
332 switch (ttfc) {
333 case dmacHw_REG_CTL_TTFC_MM_DMAC:
334 case dmacHw_REG_CTL_TTFC_MP_DMAC:
335 case dmacHw_REG_CTL_TTFC_PM_DMAC:
336 case dmacHw_REG_CTL_TTFC_PP_DMAC:
337 return 1;
338 }
339
340 return 0;
341}
342
343/****************************************************************************/
344/**
345* @brief Overwrites data length in the descriptor
346*
347* This function overwrites data length in the descriptor
348*
349*
350* @return void
351*
352* @note
353* This is only used for PCM channel
354*/
355/****************************************************************************/
356void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
357 void *pDescriptor, /* [ IN ] Descriptor buffer */
358 size_t dataLen /* [ IN ] Data length in bytes */
359 ) {
360 dmacHw_DESC_t *pProg;
361 dmacHw_DESC_t *pHead;
362 int srcTs = 0;
363 int srcTrSize = 0;
364
365 pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
366 pProg = pHead;
367
368 srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
369 srcTs = dataLen / srcTrSize;
370 do {
371 pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
372 pProg = (dmacHw_DESC_t *) pProg->llp;
373 } while (pProg != pHead);
374}
375
376/****************************************************************************/
377/**
378* @brief Clears the interrupt
379*
380* This function clears the DMA channel specific interrupt
381*
382*
383* @return void
384*
385* @note
386* Must be called under the context of ISR
387*/
388/****************************************************************************/
389void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
390 ) {
391 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
392
393 dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
394 dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
395 dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
396}
397
398/****************************************************************************/
399/**
400* @brief Returns the cause of channel specific DMA interrupt
401*
402* This function returns the cause of interrupt
403*
404* @return Interrupt status, each bit representing a specific type of interrupt
405*
406* @note
407* Should be called under the context of ISR
408*/
409/****************************************************************************/
410dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
411 ) {
412 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
413 dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
414
415 if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
416 ((0x00000001 << pCblk->channel))) {
417 status |= dmacHw_INTERRUPT_STATUS_TRANS;
418 }
419 if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
420 ((0x00000001 << pCblk->channel))) {
421 status |= dmacHw_INTERRUPT_STATUS_BLOCK;
422 }
423 if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
424 ((0x00000001 << pCblk->channel))) {
425 status |= dmacHw_INTERRUPT_STATUS_ERROR;
426 }
427
428 return status;
429}
430
431/****************************************************************************/
432/**
433* @brief Indentifies a DMA channel causing interrupt
434*
435* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
436*
437* @return NULL : No channel causing DMA interrupt
438* ! NULL : Handle to a channel causing DMA interrupt
439* @note
440* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
441*/
442/****************************************************************************/
443dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
444{
445 uint32_t i;
446
447 for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
448 if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
449 ((0x00000001 << dmacHw_gCblk[i].channel)))
450 || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
451 ((0x00000001 << dmacHw_gCblk[i].channel)))
452 || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
453 ((0x00000001 << dmacHw_gCblk[i].channel)))
454 ) {
455 return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
456 }
457 }
458 return dmacHw_CBLK_TO_HANDLE(NULL);
459}
460
461/****************************************************************************/
462/**
463* @brief Estimates number of descriptor needed to perform certain DMA transfer
464*
465*
466* @return On failure : -1
467* On success : Number of descriptor count
468*
469*
470*/
471/****************************************************************************/
472int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
473 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
474 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
475 size_t dataLen /* [ IN ] Data length in bytes */
476 ) {
477 int srcTs = 0;
478 int oddSize = 0;
479 int descCount = 0;
480 int dstTrSize = 0;
481 int srcTrSize = 0;
482 uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
483 dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
484 dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
485
486 dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
487 srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
488
489 /* Skip Tx if buffer is NULL or length is unknown */
490 if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
491 /* Do not initiate transfer */
492 return -1;
493 }
494
495 /* Ensure scatter and gather are transaction aligned */
496 if (pConfig->srcGatherWidth % srcTrSize
497 || pConfig->dstScatterWidth % dstTrSize) {
498 return -1;
499 }
500
501 /*
502 Background 1: DMAC can not perform DMA if source and destination addresses are
503 not properly aligned with the channel's transaction width. So, for successful
504 DMA transfer, transaction width must be set according to the alignment of the
505 source and destination address.
506 */
507
508 /* Adjust destination transaction width if destination address is not aligned properly */
509 dstTrWidth = pConfig->dstMaxTransactionWidth;
510 while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
511 dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
512 dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
513 }
514
515 /* Adjust source transaction width if source address is not aligned properly */
516 srcTrWidth = pConfig->srcMaxTransactionWidth;
517 while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
518 srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
519 srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
520 }
521
522 /* Find the maximum transaction per descriptor */
523 if (pConfig->maxDataPerBlock
524 && ((pConfig->maxDataPerBlock / srcTrSize) <
525 dmacHw_MAX_BLOCKSIZE)) {
526 maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
527 }
528
529 /* Find number of source transactions needed to complete the DMA transfer */
530 srcTs = dataLen / srcTrSize;
531 /* Find the odd number of bytes that need to be transferred as single byte transaction width */
532 if (srcTs && (dstTrSize > srcTrSize)) {
533 oddSize = dataLen % dstTrSize;
534 /* Adjust source transaction count due to "oddSize" */
535 srcTs = srcTs - (oddSize / srcTrSize);
536 } else {
537 oddSize = dataLen % srcTrSize;
538 }
539 /* Adjust "descCount" due to "oddSize" */
540 if (oddSize) {
541 descCount++;
542 }
543
544 /* Find the number of descriptor needed for total "srcTs" */
545 if (srcTs) {
546 descCount += ((srcTs - 1) / maxBlockSize) + 1;
547 }
548
549 return descCount;
550}
551
552/****************************************************************************/
553/**
554* @brief Check the existence of pending descriptor
555*
556* This function confirmes if there is any pending descriptor in the chain
557* to program the channel
558*
559* @return 1 : Channel need to be programmed with pending descriptor
560* 0 : No more pending descriptor to programe the channel
561*
562* @note
563* - This function should be called from ISR in case there are pending
564* descriptor to program the channel.
565*
566* Example:
567*
568* dmac_isr ()
569* {
570* ...
571* if (dmacHw_descriptorPending (handle))
572* {
573* dmacHw_initiateTransfer (handle);
574* }
575* }
576*
577*/
578/****************************************************************************/
579uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
580 void *pDescriptor /* [ IN ] Descriptor buffer */
581 ) {
582 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
583 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
584
585 /* Make sure channel is not busy */
586 if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
587 /* Check if pEnd is not processed */
588 if (pRing->pEnd) {
589 /* Something left for processing */
590 return 1;
591 }
592 }
593 return 0;
594}
595
596/****************************************************************************/
597/**
598* @brief Program channel register to stop transfer
599*
600* Ensures the channel is not doing any transfer after calling this function
601*
602* @return void
603*
604*/
605/****************************************************************************/
606void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
607 ) {
608 dmacHw_CBLK_t *pCblk;
609
610 pCblk = dmacHw_HANDLE_TO_CBLK(handle);
611
612 /* Stop the channel */
613 dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
614}
615
616/****************************************************************************/
617/**
618* @brief Deallocates source or destination memory, allocated
619*
620* This function can be called to deallocate data memory that was DMAed successfully
621*
622* @return On failure : -1
623* On success : Number of buffer freed
624*
625* @note
626* This function will be called ONLY, when source OR destination address is pointing
627* to dynamic memory
628*/
629/****************************************************************************/
630int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
631 void *pDescriptor, /* [ IN ] Descriptor buffer */
632 void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
633 ) {
634 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
635 uint32_t count = 0;
636
637 if (fpFree == NULL) {
638 return -1;
639 }
640
641 while ((pRing->pFree != pRing->pTail)
642 && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
643 if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
644 /* Identify, which memory to free */
645 if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
646 (*fpFree) ((void *)pRing->pFree->dar);
647 } else {
648 /* Destination was a peripheral */
649 (*fpFree) ((void *)pRing->pFree->sar);
650 }
651 /* Unmark user memory to indicate it is freed */
652 pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
653 }
654 dmacHw_NEXT_DESC(pRing, pFree);
655
656 count++;
657 }
658
659 return count;
660}
661
662/****************************************************************************/
663/**
664* @brief Prepares descriptor ring, when source peripheral working as a flow controller
665*
666* This function will update the discriptor ring by allocating buffers, when source peripheral
667* has to work as a flow controller to transfer data from:
668* - Peripheral to memory.
669*
670* @return On failure : -1
671* On success : Number of descriptor updated
672*
673*
674* @note
675* Channel must be configured for peripheral to memory transfer
676*
677*/
678/****************************************************************************/
679int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
680 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
681 void *pDescriptor, /* [ IN ] Descriptor buffer */
682 uint32_t srcAddr, /* [ IN ] Source peripheral address */
683 void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
684 int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
685 int num /* [ IN ] Number of descriptor to set */
686 ) {
687 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
688 dmacHw_DESC_t *pProg = NULL;
689 dmacHw_DESC_t *pLast = NULL;
690 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
691 uint32_t dstAddr;
692 uint32_t controlParam;
693 int i;
694
695 dmacHw_ASSERT(pConfig->transferType ==
696 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
697
698 if (num > pRing->num) {
699 return -1;
700 }
701
702 pLast = pRing->pEnd; /* Last descriptor updated */
703 pProg = pRing->pHead; /* First descriptor in the new list */
704
705 controlParam = pConfig->srcUpdate |
706 pConfig->dstUpdate |
707 pConfig->srcMaxTransactionWidth |
708 pConfig->dstMaxTransactionWidth |
709 pConfig->srcMasterInterface |
710 pConfig->dstMasterInterface |
711 pConfig->srcMaxBurstWidth |
712 pConfig->dstMaxBurstWidth |
713 dmacHw_REG_CTL_TTFC_PM_PERI |
714 dmacHw_REG_CTL_LLP_DST_EN |
715 dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
716
717 for (i = 0; i < num; i++) {
718 /* Allocate Rx buffer only for idle descriptor */
719 if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
720 ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
721 ) {
722 /* Rx descriptor is not idle */
723 break;
724 }
725 /* Set source address */
726 pRing->pHead->sar = srcAddr;
727 if (fpAlloc) {
728 /* Allocate memory for buffer in descriptor */
729 dstAddr = (uint32_t) (*fpAlloc) (len);
730 /* Check the destination address */
731 if (dstAddr == 0) {
732 if (i == 0) {
733 /* Not a single descriptor is available */
734 return -1;
735 }
736 break;
737 }
738 /* Set destination address */
739 pRing->pHead->dar = dstAddr;
740 }
741 /* Set control information */
742 pRing->pHead->ctl.lo = controlParam;
743 /* Use "devCtl" to mark the memory that need to be freed later */
744 pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
745 /* Descriptor is now owned by the channel */
746 pRing->pHead->ctl.hi = 0;
747 /* Remember the descriptor last updated */
748 pRing->pEnd = pRing->pHead;
749 /* Update next descriptor */
750 dmacHw_NEXT_DESC(pRing, pHead);
751 }
752
753 /* Mark the end of the list */
754 pRing->pEnd->ctl.lo &=
755 ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
756 /* Connect the list */
757 if (pLast != pProg) {
758 pLast->ctl.lo |=
759 dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
760 }
761 /* Mark the descriptors are updated */
762 pCblk->descUpdated = 1;
763 if (!pCblk->varDataStarted) {
764 /* LLP must be pointing to the first descriptor */
765 dmacHw_SET_LLP(pCblk->module, pCblk->channel,
766 (uint32_t) pProg - pRing->virt2PhyOffset);
767 /* Channel, handling variable data started */
768 pCblk->varDataStarted = 1;
769 }
770
771 return i;
772}
773
774/****************************************************************************/
775/**
776* @brief Read data DMAed to memory
777*
778* This function will read data that has been DMAed to memory while transferring from:
779* - Memory to memory
780* - Peripheral to memory
781*
782* @param handle -
783* @param ppBbuf -
784* @param pLen -
785*
786* @return 0 - No more data is available to read
787* 1 - More data might be available to read
788*
789*/
790/****************************************************************************/
791int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
792 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
793 void *pDescriptor, /* [ IN ] Descriptor buffer */
794 void **ppBbuf, /* [ OUT ] Data received */
795 size_t *pLlen /* [ OUT ] Length of the data received */
796 ) {
797 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
798
799 (void)handle;
800
801 if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
802 if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
803 (pRing->pTail == pRing->pHead)
804 ) {
805 /* No receive data available */
806 *ppBbuf = (char *)NULL;
807 *pLlen = 0;
808
809 return 0;
810 }
811 }
812
813 /* Return read buffer and length */
814 *ppBbuf = (char *)pRing->pTail->dar;
815
816 /* Extract length of the received data */
817 if (DmaIsFlowController(pDescriptor)) {
818 uint32_t srcTrSize = 0;
819
820 switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
821 case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
822 srcTrSize = 1;
823 break;
824 case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
825 srcTrSize = 2;
826 break;
827 case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
828 srcTrSize = 4;
829 break;
830 case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
831 srcTrSize = 8;
832 break;
833 default:
834 dmacHw_ASSERT(0);
835 }
836 /* Calculate length from the block size */
837 *pLlen =
838 (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
839 srcTrSize;
840 } else {
841 /* Extract length from the source peripheral */
842 *pLlen = pRing->pTail->sstat;
843 }
844
845 /* Advance tail to next descriptor */
846 dmacHw_NEXT_DESC(pRing, pTail);
847
848 return 1;
849}
850
851/****************************************************************************/
852/**
853* @brief Set descriptor carrying control information
854*
855* This function will be used to send specific control information to the device
856* using the DMA channel
857*
858*
859* @return -1 - On failure
860* 0 - On success
861*
862* @note
863* None
864*/
865/****************************************************************************/
866int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
867 void *pDescriptor, /* [ IN ] Descriptor buffer */
868 uint32_t ctlAddress, /* [ IN ] Address of the device control register */
869 uint32_t control /* [ IN ] Device control information */
870 ) {
871 dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
872
873 if (ctlAddress == 0) {
874 return -1;
875 }
876
877 /* Check the availability of descriptors in the ring */
878 if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
879 return -1;
880 }
881 /* Set control information */
882 pRing->pHead->devCtl = control;
883 /* Set source and destination address */
884 pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
885 pRing->pHead->dar = ctlAddress;
886 /* Set control parameters */
887 if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
888 pRing->pHead->ctl.lo = pConfig->transferType |
889 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
890 dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
891 dmacHw_SRC_TRANSACTION_WIDTH_32 |
892 pConfig->dstMaxTransactionWidth |
893 dmacHw_SRC_BURST_WIDTH_0 |
894 dmacHw_DST_BURST_WIDTH_0 |
895 pConfig->srcMasterInterface |
896 pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
897 } else {
898 uint32_t transferType = 0;
899 switch (pConfig->transferType) {
900 case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
901 transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
902 break;
903 case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
904 transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
905 break;
906 default:
907 dmacHw_ASSERT(0);
908 }
909 pRing->pHead->ctl.lo = transferType |
910 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
911 dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
912 dmacHw_SRC_TRANSACTION_WIDTH_32 |
913 pConfig->dstMaxTransactionWidth |
914 dmacHw_SRC_BURST_WIDTH_0 |
915 dmacHw_DST_BURST_WIDTH_0 |
916 pConfig->srcMasterInterface |
917 pConfig->dstMasterInterface |
918 pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
919 }
920
921 /* Set block transaction size to one 32 bit transaction */
922 pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
923
924 /* Remember the descriptor to initialize the registers */
925 if (pRing->pProg == dmacHw_DESC_INIT) {
926 pRing->pProg = pRing->pHead;
927 }
928 pRing->pEnd = pRing->pHead;
929
930 /* Advance the descriptor */
931 dmacHw_NEXT_DESC(pRing, pHead);
932
933 /* Update Tail pointer if destination is a peripheral */
934 if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
935 pRing->pTail = pRing->pHead;
936 }
937 return 0;
938}
939
940/****************************************************************************/
941/**
942* @brief Sets channel specific user data
943*
944* This function associates user data to a specific DMA channel
945*
946*/
947/****************************************************************************/
948void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
949 void *userData /* [ IN ] User data */
950 ) {
951 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
952
953 pCblk->userData = userData;
954}
955
956/****************************************************************************/
957/**
958* @brief Gets channel specific user data
959*
960* This function returns user data specific to a DMA channel
961*
962* @return user data
963*/
964/****************************************************************************/
965void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
966 ) {
967 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
968
969 return pCblk->userData;
970}
971
972/****************************************************************************/
973/**
974* @brief Resets descriptor control information
975*
976* @return void
977*/
978/****************************************************************************/
979void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
980 ) {
981 int i;
982 dmacHw_DESC_RING_t *pRing;
983 dmacHw_DESC_t *pDesc;
984
985 pRing = dmacHw_GET_DESC_RING(pDescriptor);
986 pDesc = pRing->pHead;
987
988 for (i = 0; i < pRing->num; i++) {
989 /* Mark descriptor is ready to use */
990 pDesc->ctl.hi = dmacHw_DESC_FREE;
991 /* Look into next link list item */
992 pDesc++;
993 }
994 pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
995 pRing->pProg = dmacHw_DESC_INIT;
996}
997
998/****************************************************************************/
999/**
1000* @brief Displays channel specific registers and other control parameters
1001*
1002* @return void
1003*
1004*
1005* @note
1006* None
1007*/
1008/****************************************************************************/
1009void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
1010 void *pDescriptor, /* [ IN ] Descriptor buffer */
1011 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
1012 ) {
1013 dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
1014
1015 DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
1016 DisplayDescRing(pDescriptor, fpPrint);
1017}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
new file mode 100644
index 00000000000..244a61ab769
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/tmr/Makefile
@@ -0,0 +1 @@
obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
new file mode 100644
index 00000000000..16225e43f3c
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -0,0 +1,576 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw.c
18*
19* @brief Low level Timer driver routines
20*
21* @note
22*
23* These routines provide basic timer functionality only.
24*/
25/****************************************************************************/
26
27/* ---- Include Files ---------------------------------------------------- */
28
29#include <csp/errno.h>
30#include <csp/stdint.h>
31
32#include <csp/tmrHw.h>
33#include <mach/csp/tmrHw_reg.h>
34
35#define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0
36#define tmrHw_MILLISEC_PER_SEC (1000)
37
38#define tmrHw_LOW_1_RESOLUTION_COUNT (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
39#define tmrHw_LOW_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
40#define tmrHw_LOW_16_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
41#define tmrHw_LOW_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
42#define tmrHw_LOW_256_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
43#define tmrHw_LOW_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
44
45#define tmrHw_HIGH_1_RESOLUTION_COUNT (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
46#define tmrHw_HIGH_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
47#define tmrHw_HIGH_16_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
48#define tmrHw_HIGH_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
49#define tmrHw_HIGH_256_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
50#define tmrHw_HIGH_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
51
52static void ResetTimer(tmrHw_ID_t timerId)
53 __attribute__ ((section(".aramtext")));
54static int tmrHw_divide(int num, int denom)
55 __attribute__ ((section(".aramtext")));
56
57/****************************************************************************/
58/**
59* @brief Get timer capability
60*
61* This function returns various capabilities/attributes of a timer
62*
63* @return Capability
64*
65*/
66/****************************************************************************/
67uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
68 tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */
69) {
70 switch (capability) {
71 case tmrHw_CAPABILITY_CLOCK:
72 return (timerId <=
73 1) ? tmrHw_LOW_RESOLUTION_CLOCK :
74 tmrHw_HIGH_RESOLUTION_CLOCK;
75 case tmrHw_CAPABILITY_RESOLUTION:
76 return 32;
77 default:
78 return 0;
79 }
80 return 0;
81}
82
83/****************************************************************************/
84/**
85* @brief Resets a timer
86*
87* This function initializes timer
88*
89* @return void
90*
91*/
92/****************************************************************************/
93static void ResetTimer(tmrHw_ID_t timerId /* [ IN ] Timer Id */
94) {
95 /* Reset timer */
96 pTmrHw[timerId].LoadValue = 0;
97 pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
98 pTmrHw[timerId].Control = 0;
99 pTmrHw[timerId].BackgroundLoad = 0;
100 /* Always configure as a 32 bit timer */
101 pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
102 /* Clear interrupt only if raw status interrupt is set */
103 if (pTmrHw[timerId].RawInterruptStatus) {
104 pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
105 }
106}
107
108/****************************************************************************/
109/**
110* @brief Sets counter value for an interval in ms
111*
112* @return On success: Effective counter value set
113* On failure: 0
114*
115*/
116/****************************************************************************/
117static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
118 tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
119) {
120 uint32_t scale = 0;
121 uint32_t count = 0;
122
123 if (timerId == 0 || timerId == 1) {
124 if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
125 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
126 scale = tmrHw_LOW_1_RESOLUTION_COUNT;
127 } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
128 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
129 scale = tmrHw_LOW_16_RESOLUTION_COUNT;
130 } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
131 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
132 scale = tmrHw_LOW_256_RESOLUTION_COUNT;
133 } else {
134 return 0;
135 }
136
137 count = msec * scale;
138 /* Set counter value */
139 pTmrHw[timerId].LoadValue = count;
140 pTmrHw[timerId].BackgroundLoad = count;
141
142 } else if (timerId == 2 || timerId == 3) {
143 if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
144 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
145 scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
146 } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
147 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
148 scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
149 } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
150 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
151 scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
152 } else {
153 return 0;
154 }
155
156 count = msec * scale;
157 /* Set counter value */
158 pTmrHw[timerId].LoadValue = count;
159 pTmrHw[timerId].BackgroundLoad = count;
160 }
161 return count / scale;
162}
163
164/****************************************************************************/
165/**
166* @brief Configures a periodic timer in terms of timer interrupt rate
167*
168* This function initializes a periodic timer to generate specific number of
169* timer interrupt per second
170*
171* @return On success: Effective timer frequency
172* On failure: 0
173*
174*/
175/****************************************************************************/
176tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
177 tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */
178) {
179 uint32_t resolution = 0;
180 uint32_t count = 0;
181 ResetTimer(timerId);
182
183 /* Set timer mode periodic */
184 pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
185 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
186 /* Set timer in highest resolution */
187 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
188
189 if (rate && (timerId == 0 || timerId == 1)) {
190 if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
191 return 0;
192 }
193 resolution = tmrHw_LOW_RESOLUTION_CLOCK;
194 } else if (rate && (timerId == 2 || timerId == 3)) {
195 if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
196 return 0;
197 } else {
198 resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
199 }
200 } else {
201 return 0;
202 }
203 /* Find the counter value */
204 count = resolution / rate;
205 /* Set counter value */
206 pTmrHw[timerId].LoadValue = count;
207 pTmrHw[timerId].BackgroundLoad = count;
208
209 return resolution / count;
210}
211
212/****************************************************************************/
213/**
214* @brief Configures a periodic timer to generate timer interrupt after
215* certain time interval
216*
217* This function initializes a periodic timer to generate timer interrupt
218* after every time interval in millisecond
219*
220* @return On success: Effective interval set in milli-second
221* On failure: 0
222*
223*/
224/****************************************************************************/
225tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
226 tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
227) {
228 ResetTimer(timerId);
229
230 /* Set timer mode periodic */
231 pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
232 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
233
234 return SetTimerPeriod(timerId, msec);
235}
236
237/****************************************************************************/
238/**
239* @brief Configures a periodic timer to generate timer interrupt just once
240* after certain time interval
241*
242* This function initializes a periodic timer to generate a single ticks after
243* certain time interval in millisecond
244*
245* @return On success: Effective interval set in milli-second
246* On failure: 0
247*
248*/
249/****************************************************************************/
250tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
251 tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */
252) {
253 ResetTimer(timerId);
254
255 /* Set timer mode oneshot */
256 pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
257 pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
258
259 return SetTimerPeriod(timerId, msec);
260}
261
262/****************************************************************************/
263/**
264* @brief Configures a timer to run as a free running timer
265*
266* This function initializes a timer to run as a free running timer
267*
268* @return Timer resolution (count / sec)
269*
270*/
271/****************************************************************************/
272tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
273 uint32_t divider /* [ IN ] Dividing the clock frequency */
274) {
275 uint32_t scale = 0;
276
277 ResetTimer(timerId);
278 /* Set timer as free running mode */
279 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
280 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
281
282 if (divider >= 64) {
283 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
284 scale = 256;
285 } else if (divider >= 8) {
286 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
287 scale = 16;
288 } else {
289 pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
290 scale = 1;
291 }
292
293 if (timerId == 0 || timerId == 1) {
294 return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
295 } else if (timerId == 2 || timerId == 3) {
296 return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
297 }
298
299 return 0;
300}
301
302/****************************************************************************/
303/**
304* @brief Starts a timer
305*
306* This function starts a preconfigured timer
307*
308* @return -1 - On Failure
309* 0 - On Success
310*
311*/
312/****************************************************************************/
313int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
314) {
315 pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
316 return 0;
317}
318
319/****************************************************************************/
320/**
321* @brief Stops a timer
322*
323* This function stops a running timer
324*
325* @return -1 - On Failure
326* 0 - On Success
327*
328*/
329/****************************************************************************/
330int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
331) {
332 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
333 return 0;
334}
335
336/****************************************************************************/
337/**
338* @brief Gets current timer count
339*
340* This function returns the current timer value
341*
342* @return Current downcounting timer value
343*
344*/
345/****************************************************************************/
346uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */
347) {
348 /* return 32 bit timer value */
349 switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
350 case tmrHw_CONTROL_FREE_RUNNING:
351 if (pTmrHw[timerId].CurrentValue) {
352 return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
353 }
354 break;
355 case tmrHw_CONTROL_PERIODIC:
356 case tmrHw_CONTROL_ONESHOT:
357 return pTmrHw[timerId].BackgroundLoad -
358 pTmrHw[timerId].CurrentValue;
359 }
360 return 0;
361}
362
363/****************************************************************************/
364/**
365* @brief Gets timer count rate
366*
367* This function returns the number of counts per second
368*
369* @return Count rate
370*
371*/
372/****************************************************************************/
373tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */
374) {
375 uint32_t divider = 0;
376
377 switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
378 case tmrHw_CONTROL_PRESCALE_1:
379 divider = 1;
380 break;
381 case tmrHw_CONTROL_PRESCALE_16:
382 divider = 16;
383 break;
384 case tmrHw_CONTROL_PRESCALE_256:
385 divider = 256;
386 break;
387 default:
388 tmrHw_ASSERT(0);
389 }
390
391 if (timerId == 0 || timerId == 1) {
392 return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
393 } else {
394 return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
395 }
396 return 0;
397}
398
399/****************************************************************************/
400/**
401* @brief Enables timer interrupt
402*
403* This function enables the timer interrupt
404*
405* @return N/A
406*
407*/
408/****************************************************************************/
409void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
410) {
411 pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
412}
413
414/****************************************************************************/
415/**
416* @brief Disables timer interrupt
417*
418* This function disable the timer interrupt
419*
420* @return N/A
421*
422*/
423/****************************************************************************/
424void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
425) {
426 pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
427}
428
429/****************************************************************************/
430/**
431* @brief Clears the interrupt
432*
433* This function clears the timer interrupt
434*
435* @return N/A
436*
437* @note
438* Must be called under the context of ISR
439*/
440/****************************************************************************/
441void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
442) {
443 pTmrHw[timerId].InterruptClear = 0x1;
444}
445
446/****************************************************************************/
447/**
448* @brief Gets the interrupt status
449*
450* This function returns timer interrupt status
451*
452* @return Interrupt status
453*/
454/****************************************************************************/
455tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */
456) {
457 if (pTmrHw[timerId].InterruptStatus) {
458 return tmrHw_INTERRUPT_STATUS_SET;
459 } else {
460 return tmrHw_INTERRUPT_STATUS_UNSET;
461 }
462}
463
464/****************************************************************************/
465/**
466* @brief Indentifies a timer causing interrupt
467*
468* This functions returns a timer causing interrupt
469*
470* @return 0xFFFFFFFF : No timer causing an interrupt
471* ! 0xFFFFFFFF : timer causing an interrupt
472* @note
473* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
474*/
475/****************************************************************************/
476tmrHw_ID_t tmrHw_getInterruptSource(void /* void */
477) {
478 int i;
479
480 for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
481 if (pTmrHw[i].InterruptStatus) {
482 return i;
483 }
484 }
485
486 return 0xFFFFFFFF;
487}
488
489/****************************************************************************/
490/**
491* @brief Displays specific timer registers
492*
493*
494* @return void
495*
496*/
497/****************************************************************************/
498void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */
499 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
500) {
501 (*fpPrint) ("Displaying register contents \n\n");
502 (*fpPrint) ("Timer %d: Load value 0x%X\n", timerId,
503 pTmrHw[timerId].LoadValue);
504 (*fpPrint) ("Timer %d: Background load value 0x%X\n", timerId,
505 pTmrHw[timerId].BackgroundLoad);
506 (*fpPrint) ("Timer %d: Control 0x%X\n", timerId,
507 pTmrHw[timerId].Control);
508 (*fpPrint) ("Timer %d: Interrupt clear 0x%X\n", timerId,
509 pTmrHw[timerId].InterruptClear);
510 (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
511 pTmrHw[timerId].RawInterruptStatus);
512 (*fpPrint) ("Timer %d: Interrupt status 0x%X\n", timerId,
513 pTmrHw[timerId].InterruptStatus);
514}
515
516/****************************************************************************/
517/**
518* @brief Use a timer to perform a busy wait delay for a number of usecs.
519*
520* @return N/A
521*/
522/****************************************************************************/
523void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */
524 unsigned long usecs /* [ IN ] usec to delay */
525) {
526 tmrHw_RATE_t usec_tick_rate;
527 tmrHw_COUNT_t start_time;
528 tmrHw_COUNT_t delta_time;
529
530 start_time = tmrHw_GetCurrentCount(timerId);
531 usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
532 delta_time = usecs * usec_tick_rate;
533
534 /* Busy wait */
535 while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
536 ;
537}
538
539/****************************************************************************/
540/**
541* @brief Local Divide function
542*
543* This function does the divide
544*
545* @return divide value
546*
547*/
548/****************************************************************************/
549static int tmrHw_divide(int num, int denom)
550{
551 int r;
552 int t = 1;
553
554 /* Shift denom and t up to the largest value to optimize algorithm */
555 /* t contains the units of each divide */
556 while ((denom & 0x40000000) == 0) { /* fails if denom=0 */
557 denom = denom << 1;
558 t = t << 1;
559 }
560
561 /* Initialize the result */
562 r = 0;
563
564 do {
565 /* Determine if there exists a positive remainder */
566 if ((num - denom) >= 0) {
567 /* Accumlate t to the result and calculate a new remainder */
568 num = num - denom;
569 r = r + t;
570 }
571 /* Continue to shift denom and shift t down to 0 */
572 denom = denom >> 1;
573 t = t >> 1;
574 } while (t != 0);
575 return r;
576}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
new file mode 100644
index 00000000000..0ca00050666
--- /dev/null
+++ b/arch/arm/mach-bcmring/dma.c
@@ -0,0 +1,2329 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dma.c
18*
19* @brief Implements the DMA interface.
20*/
21/****************************************************************************/
22
23/* ---- Include Files ---------------------------------------------------- */
24
25#include <linux/module.h>
26#include <linux/device.h>
27#include <linux/dma-mapping.h>
28#include <linux/interrupt.h>
29#include <linux/irqreturn.h>
30#include <linux/proc_fs.h>
31#include <linux/slab.h>
32
33#include <mach/timer.h>
34
35#include <linux/mm.h>
36#include <linux/pfn.h>
37#include <linux/atomic.h>
38#include <mach/dma.h>
39
40/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
41/* especially since dc4 doesn't use kmalloc'd memory. */
42
43#define ALLOW_MAP_OF_KMALLOC_MEMORY 0
44
45/* ---- Public Variables ------------------------------------------------- */
46
47/* ---- Private Constants and Types -------------------------------------- */
48
49#define MAKE_HANDLE(controllerIdx, channelIdx) (((controllerIdx) << 4) | (channelIdx))
50
51#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f)
52#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f)
53
54#define DMA_MAP_DEBUG 0
55
56#if DMA_MAP_DEBUG
57# define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args)
58#else
59# define DMA_MAP_PRINT(fmt, args...)
60#endif
61
62/* ---- Private Variables ------------------------------------------------ */
63
64static DMA_Global_t gDMA;
65static struct proc_dir_entry *gDmaDir;
66
67static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0);
68static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0);
69static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0);
70static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
71
72#include "dma_device.c"
73
74/* ---- Private Function Prototypes -------------------------------------- */
75
76/* ---- Functions ------------------------------------------------------- */
77
78/****************************************************************************/
79/**
80* Displays information for /proc/dma/mem-type
81*/
82/****************************************************************************/
83
84static int dma_proc_read_mem_type(char *buf, char **start, off_t offset,
85 int count, int *eof, void *data)
86{
87 int len = 0;
88
89 len += sprintf(buf + len, "dma_map_mem statistics\n");
90 len +=
91 sprintf(buf + len, "coherent: %d\n",
92 atomic_read(&gDmaStatMemTypeCoherent));
93 len +=
94 sprintf(buf + len, "kmalloc: %d\n",
95 atomic_read(&gDmaStatMemTypeKmalloc));
96 len +=
97 sprintf(buf + len, "vmalloc: %d\n",
98 atomic_read(&gDmaStatMemTypeVmalloc));
99 len +=
100 sprintf(buf + len, "user: %d\n",
101 atomic_read(&gDmaStatMemTypeUser));
102
103 return len;
104}
105
106/****************************************************************************/
107/**
108* Displays information for /proc/dma/channels
109*/
110/****************************************************************************/
111
112static int dma_proc_read_channels(char *buf, char **start, off_t offset,
113 int count, int *eof, void *data)
114{
115 int controllerIdx;
116 int channelIdx;
117 int limit = count - 200;
118 int len = 0;
119 DMA_Channel_t *channel;
120
121 if (down_interruptible(&gDMA.lock) < 0) {
122 return -ERESTARTSYS;
123 }
124
125 for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
126 controllerIdx++) {
127 for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
128 channelIdx++) {
129 if (len >= limit) {
130 break;
131 }
132
133 channel =
134 &gDMA.controller[controllerIdx].channel[channelIdx];
135
136 len +=
137 sprintf(buf + len, "%d:%d ", controllerIdx,
138 channelIdx);
139
140 if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
141 0) {
142 len +=
143 sprintf(buf + len, "Dedicated for %s ",
144 DMA_gDeviceAttribute[channel->
145 devType].name);
146 } else {
147 len += sprintf(buf + len, "Shared ");
148 }
149
150 if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
151 len += sprintf(buf + len, "No ISR ");
152 }
153
154 if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
155 len += sprintf(buf + len, "Fifo: 128 ");
156 } else {
157 len += sprintf(buf + len, "Fifo: 64 ");
158 }
159
160 if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
161 len +=
162 sprintf(buf + len, "InUse by %s",
163 DMA_gDeviceAttribute[channel->
164 devType].name);
165#if (DMA_DEBUG_TRACK_RESERVATION)
166 len +=
167 sprintf(buf + len, " (%s:%d)",
168 channel->fileName,
169 channel->lineNum);
170#endif
171 } else {
172 len += sprintf(buf + len, "Avail ");
173 }
174
175 if (channel->lastDevType != DMA_DEVICE_NONE) {
176 len +=
177 sprintf(buf + len, "Last use: %s ",
178 DMA_gDeviceAttribute[channel->
179 lastDevType].
180 name);
181 }
182
183 len += sprintf(buf + len, "\n");
184 }
185 }
186 up(&gDMA.lock);
187 *eof = 1;
188
189 return len;
190}
191
192/****************************************************************************/
193/**
194* Displays information for /proc/dma/devices
195*/
196/****************************************************************************/
197
198static int dma_proc_read_devices(char *buf, char **start, off_t offset,
199 int count, int *eof, void *data)
200{
201 int limit = count - 200;
202 int len = 0;
203 int devIdx;
204
205 if (down_interruptible(&gDMA.lock) < 0) {
206 return -ERESTARTSYS;
207 }
208
209 for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
210 DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
211
212 if (devAttr->name == NULL) {
213 continue;
214 }
215
216 if (len >= limit) {
217 break;
218 }
219
220 len += sprintf(buf + len, "%-12s ", devAttr->name);
221
222 if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
223 len +=
224 sprintf(buf + len, "Dedicated %d:%d ",
225 devAttr->dedicatedController,
226 devAttr->dedicatedChannel);
227 } else {
228 len += sprintf(buf + len, "Shared DMA:");
229 if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
230 len += sprintf(buf + len, "0");
231 }
232 if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
233 len += sprintf(buf + len, "1");
234 }
235 len += sprintf(buf + len, " ");
236 }
237 if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
238 len += sprintf(buf + len, "NoISR ");
239 }
240 if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
241 len += sprintf(buf + len, "Allow-128 ");
242 }
243
244 len +=
245 sprintf(buf + len,
246 "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
247 devAttr->numTransfers, devAttr->transferTicks,
248 devAttr->transferBytes,
249 devAttr->ring.bytesAllocated);
250
251 }
252
253 up(&gDMA.lock);
254 *eof = 1;
255
256 return len;
257}
258
259/****************************************************************************/
260/**
261* Determines if a DMA_Device_t is "valid".
262*
263* @return
264* TRUE - dma device is valid
265* FALSE - dma device isn't valid
266*/
267/****************************************************************************/
268
269static inline int IsDeviceValid(DMA_Device_t device)
270{
271 return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
272}
273
274/****************************************************************************/
275/**
276* Translates a DMA handle into a pointer to a channel.
277*
278* @return
279* non-NULL - pointer to DMA_Channel_t
280* NULL - DMA Handle was invalid
281*/
282/****************************************************************************/
283
284static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
285{
286 int controllerIdx;
287 int channelIdx;
288
289 controllerIdx = CONTROLLER_FROM_HANDLE(handle);
290 channelIdx = CHANNEL_FROM_HANDLE(handle);
291
292 if ((controllerIdx > DMA_NUM_CONTROLLERS)
293 || (channelIdx > DMA_NUM_CHANNELS)) {
294 return NULL;
295 }
296 return &gDMA.controller[controllerIdx].channel[channelIdx];
297}
298
299/****************************************************************************/
300/**
301* Interrupt handler which is called to process DMA interrupts.
302*/
303/****************************************************************************/
304
305static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
306{
307 DMA_Channel_t *channel;
308 DMA_DeviceAttribute_t *devAttr;
309 int irqStatus;
310
311 channel = (DMA_Channel_t *) dev_id;
312
313 /* Figure out why we were called, and knock down the interrupt */
314
315 irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
316 dmacHw_clearInterrupt(channel->dmacHwHandle);
317
318 if ((channel->devType < 0)
319 || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
320 printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
321 channel->devType);
322 return IRQ_NONE;
323 }
324 devAttr = &DMA_gDeviceAttribute[channel->devType];
325
326 /* Update stats */
327
328 if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
329 devAttr->transferTicks +=
330 (timer_get_tick_count() - devAttr->transferStartTime);
331 }
332
333 if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
334 printk(KERN_ERR
335 "dma_interrupt_handler: devType :%d DMA error (%s)\n",
336 channel->devType, devAttr->name);
337 } else {
338 devAttr->numTransfers++;
339 devAttr->transferBytes += devAttr->numBytes;
340 }
341
342 /* Call any installed handler */
343
344 if (devAttr->devHandler != NULL) {
345 devAttr->devHandler(channel->devType, irqStatus,
346 devAttr->userData);
347 }
348
349 return IRQ_HANDLED;
350}
351
352/****************************************************************************/
353/**
354* Allocates memory to hold a descriptor ring. The descriptor ring then
355* needs to be populated by making one or more calls to
356* dna_add_descriptors.
357*
358* The returned descriptor ring will be automatically initialized.
359*
360* @return
361* 0 Descriptor ring was allocated successfully
362* -EINVAL Invalid parameters passed in
363* -ENOMEM Unable to allocate memory for the desired number of descriptors.
364*/
365/****************************************************************************/
366
367int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */
368 int numDescriptors /* Number of descriptors that need to be allocated. */
369 ) {
370 size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
371
372 if ((ring == NULL) || (numDescriptors <= 0)) {
373 return -EINVAL;
374 }
375
376 ring->physAddr = 0;
377 ring->descriptorsAllocated = 0;
378 ring->bytesAllocated = 0;
379
380 ring->virtAddr = dma_alloc_writecombine(NULL,
381 bytesToAlloc,
382 &ring->physAddr,
383 GFP_KERNEL);
384 if (ring->virtAddr == NULL) {
385 return -ENOMEM;
386 }
387
388 ring->bytesAllocated = bytesToAlloc;
389 ring->descriptorsAllocated = numDescriptors;
390
391 return dma_init_descriptor_ring(ring, numDescriptors);
392}
393
394EXPORT_SYMBOL(dma_alloc_descriptor_ring);
395
396/****************************************************************************/
397/**
398* Releases the memory which was previously allocated for a descriptor ring.
399*/
400/****************************************************************************/
401
402void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */
403 ) {
404 if (ring->virtAddr != NULL) {
405 dma_free_writecombine(NULL,
406 ring->bytesAllocated,
407 ring->virtAddr, ring->physAddr);
408 }
409
410 ring->bytesAllocated = 0;
411 ring->descriptorsAllocated = 0;
412 ring->virtAddr = NULL;
413 ring->physAddr = 0;
414}
415
416EXPORT_SYMBOL(dma_free_descriptor_ring);
417
418/****************************************************************************/
419/**
420* Initializes a descriptor ring, so that descriptors can be added to it.
421* Once a descriptor ring has been allocated, it may be reinitialized for
422* use with additional/different regions of memory.
423*
424* Note that if 7 descriptors are allocated, it's perfectly acceptable to
425* initialize the ring with a smaller number of descriptors. The amount
426* of memory allocated for the descriptor ring will not be reduced, and
427* the descriptor ring may be reinitialized later
428*
429* @return
430* 0 Descriptor ring was initialized successfully
431* -ENOMEM The descriptor which was passed in has insufficient space
432* to hold the desired number of descriptors.
433*/
434/****************************************************************************/
435
436int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */
437 int numDescriptors /* Number of descriptors to initialize. */
438 ) {
439 if (ring->virtAddr == NULL) {
440 return -EINVAL;
441 }
442 if (dmacHw_initDescriptor(ring->virtAddr,
443 ring->physAddr,
444 ring->bytesAllocated, numDescriptors) < 0) {
445 printk(KERN_ERR
446 "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
447 return -ENOMEM;
448 }
449
450 return 0;
451}
452
453EXPORT_SYMBOL(dma_init_descriptor_ring);
454
455/****************************************************************************/
456/**
457* Determines the number of descriptors which would be required for a
458* transfer of the indicated memory region.
459*
460* This function also needs to know which DMA device this transfer will
461* be destined for, so that the appropriate DMA configuration can be retrieved.
462* DMA parameters such as transfer width, and whether this is a memory-to-memory
463* or memory-to-peripheral, etc can all affect the actual number of descriptors
464* required.
465*
466* @return
467* > 0 Returns the number of descriptors required for the indicated transfer
468* -ENODEV - Device handed in is invalid.
469* -EINVAL Invalid parameters
470* -ENOMEM Memory exhausted
471*/
472/****************************************************************************/
473
474int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
475 dma_addr_t srcData, /* Place to get data to write to device */
476 dma_addr_t dstData, /* Pointer to device data address */
477 size_t numBytes /* Number of bytes to transfer to the device */
478 ) {
479 int numDescriptors;
480 DMA_DeviceAttribute_t *devAttr;
481
482 if (!IsDeviceValid(device)) {
483 return -ENODEV;
484 }
485 devAttr = &DMA_gDeviceAttribute[device];
486
487 numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
488 (void *)srcData,
489 (void *)dstData,
490 numBytes);
491 if (numDescriptors < 0) {
492 printk(KERN_ERR
493 "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
494 return -EINVAL;
495 }
496
497 return numDescriptors;
498}
499
500EXPORT_SYMBOL(dma_calculate_descriptor_count);
501
502/****************************************************************************/
503/**
504* Adds a region of memory to the descriptor ring. Note that it may take
505* multiple descriptors for each region of memory. It is the callers
506* responsibility to allocate a sufficiently large descriptor ring.
507*
508* @return
509* 0 Descriptors were added successfully
510* -ENODEV Device handed in is invalid.
511* -EINVAL Invalid parameters
512* -ENOMEM Memory exhausted
513*/
514/****************************************************************************/
515
516int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */
517 DMA_Device_t device, /* DMA Device that descriptors are for */
518 dma_addr_t srcData, /* Place to get data (memory or device) */
519 dma_addr_t dstData, /* Place to put data (memory or device) */
520 size_t numBytes /* Number of bytes to transfer to the device */
521 ) {
522 int rc;
523 DMA_DeviceAttribute_t *devAttr;
524
525 if (!IsDeviceValid(device)) {
526 return -ENODEV;
527 }
528 devAttr = &DMA_gDeviceAttribute[device];
529
530 rc = dmacHw_setDataDescriptor(&devAttr->config,
531 ring->virtAddr,
532 (void *)srcData,
533 (void *)dstData, numBytes);
534 if (rc < 0) {
535 printk(KERN_ERR
536 "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
537 rc);
538 return -ENOMEM;
539 }
540
541 return 0;
542}
543
544EXPORT_SYMBOL(dma_add_descriptors);
545
546/****************************************************************************/
547/**
548* Sets the descriptor ring associated with a device.
549*
550* Once set, the descriptor ring will be associated with the device, even
551* across channel request/free calls. Passing in a NULL descriptor ring
552* will release any descriptor ring currently associated with the device.
553*
554* Note: If you call dma_transfer, or one of the other dma_alloc_ functions
555* the descriptor ring may be released and reallocated.
556*
557* Note: This function will release the descriptor memory for any current
558* descriptor ring associated with this device.
559*
560* @return
561* 0 Descriptors were added successfully
562* -ENODEV Device handed in is invalid.
563*/
564/****************************************************************************/
565
566int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
567 DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */
568 ) {
569 DMA_DeviceAttribute_t *devAttr;
570
571 if (!IsDeviceValid(device)) {
572 return -ENODEV;
573 }
574 devAttr = &DMA_gDeviceAttribute[device];
575
576 /* Free the previously allocated descriptor ring */
577
578 dma_free_descriptor_ring(&devAttr->ring);
579
580 if (ring != NULL) {
581 /* Copy in the new one */
582
583 devAttr->ring = *ring;
584 }
585
586 /* Set things up so that if dma_transfer is called then this descriptor */
587 /* ring will get freed. */
588
589 devAttr->prevSrcData = 0;
590 devAttr->prevDstData = 0;
591 devAttr->prevNumBytes = 0;
592
593 return 0;
594}
595
596EXPORT_SYMBOL(dma_set_device_descriptor_ring);
597
598/****************************************************************************/
599/**
600* Retrieves the descriptor ring associated with a device.
601*
602* @return
603* 0 Descriptors were added successfully
604* -ENODEV Device handed in is invalid.
605*/
606/****************************************************************************/
607
608int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
609 DMA_DescriptorRing_t *ring /* Place to store retrieved ring */
610 ) {
611 DMA_DeviceAttribute_t *devAttr;
612
613 memset(ring, 0, sizeof(*ring));
614
615 if (!IsDeviceValid(device)) {
616 return -ENODEV;
617 }
618 devAttr = &DMA_gDeviceAttribute[device];
619
620 *ring = devAttr->ring;
621
622 return 0;
623}
624
625EXPORT_SYMBOL(dma_get_device_descriptor_ring);
626
627/****************************************************************************/
628/**
629* Configures a DMA channel.
630*
631* @return
632* >= 0 - Initialization was successful.
633*
634* -EBUSY - Device is currently being used.
635* -ENODEV - Device handed in is invalid.
636*/
637/****************************************************************************/
638
639static int ConfigChannel(DMA_Handle_t handle)
640{
641 DMA_Channel_t *channel;
642 DMA_DeviceAttribute_t *devAttr;
643 int controllerIdx;
644
645 channel = HandleToChannel(handle);
646 if (channel == NULL) {
647 return -ENODEV;
648 }
649 devAttr = &DMA_gDeviceAttribute[channel->devType];
650 controllerIdx = CONTROLLER_FROM_HANDLE(handle);
651
652 if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
653 if (devAttr->config.transferType ==
654 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
655 devAttr->config.dstPeripheralPort =
656 devAttr->dmacPort[controllerIdx];
657 } else if (devAttr->config.transferType ==
658 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
659 devAttr->config.srcPeripheralPort =
660 devAttr->dmacPort[controllerIdx];
661 }
662 }
663
664 if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
665 printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
666 return -EIO;
667 }
668
669 return 0;
670}
671
672/****************************************************************************/
673/**
674* Initializes all of the data structures associated with the DMA.
675* @return
676* >= 0 - Initialization was successful.
677*
678* -EBUSY - Device is currently being used.
679* -ENODEV - Device handed in is invalid.
680*/
681/****************************************************************************/
682
683int dma_init(void)
684{
685 int rc = 0;
686 int controllerIdx;
687 int channelIdx;
688 DMA_Device_t devIdx;
689 DMA_Channel_t *channel;
690 DMA_Handle_t dedicatedHandle;
691
692 memset(&gDMA, 0, sizeof(gDMA));
693
694 sema_init(&gDMA.lock, 0);
695 init_waitqueue_head(&gDMA.freeChannelQ);
696
697 /* Initialize the Hardware */
698
699 dmacHw_initDma();
700
701 /* Start off by marking all of the DMA channels as shared. */
702
703 for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
704 controllerIdx++) {
705 for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
706 channelIdx++) {
707 channel =
708 &gDMA.controller[controllerIdx].channel[channelIdx];
709
710 channel->flags = 0;
711 channel->devType = DMA_DEVICE_NONE;
712 channel->lastDevType = DMA_DEVICE_NONE;
713
714#if (DMA_DEBUG_TRACK_RESERVATION)
715 channel->fileName = "";
716 channel->lineNum = 0;
717#endif
718
719 channel->dmacHwHandle =
720 dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
721 (controllerIdx,
722 channelIdx));
723 dmacHw_initChannel(channel->dmacHwHandle);
724 }
725 }
726
727 /* Record any special attributes that channels may have */
728
729 gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
730 gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
731 gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
732 gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
733
734 /* Now walk through and record the dedicated channels. */
735
736 for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
737 DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
738
739 if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
740 && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
741 printk(KERN_ERR
742 "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
743 devAttr->name);
744 rc = -EINVAL;
745 goto out;
746 }
747
748 if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
749 /* This is a dedicated device. Mark the channel as being reserved. */
750
751 if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
752 printk(KERN_ERR
753 "DMA Device: %s DMA Controller %d is out of range\n",
754 devAttr->name,
755 devAttr->dedicatedController);
756 rc = -EINVAL;
757 goto out;
758 }
759
760 if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
761 printk(KERN_ERR
762 "DMA Device: %s DMA Channel %d is out of range\n",
763 devAttr->name,
764 devAttr->dedicatedChannel);
765 rc = -EINVAL;
766 goto out;
767 }
768
769 dedicatedHandle =
770 MAKE_HANDLE(devAttr->dedicatedController,
771 devAttr->dedicatedChannel);
772 channel = HandleToChannel(dedicatedHandle);
773
774 if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
775 0) {
776 printk
777 ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
778 devAttr->name,
779 devAttr->dedicatedController,
780 devAttr->dedicatedChannel,
781 DMA_gDeviceAttribute[channel->devType].
782 name);
783 rc = -EBUSY;
784 goto out;
785 }
786
787 channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
788 channel->devType = devIdx;
789
790 if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
791 channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
792 }
793
794 /* For dedicated channels, we can go ahead and configure the DMA channel now */
795 /* as well. */
796
797 ConfigChannel(dedicatedHandle);
798 }
799 }
800
801 /* Go through and register the interrupt handlers */
802
803 for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
804 controllerIdx++) {
805 for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
806 channelIdx++) {
807 channel =
808 &gDMA.controller[controllerIdx].channel[channelIdx];
809
810 if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
811 snprintf(channel->name, sizeof(channel->name),
812 "dma %d:%d %s", controllerIdx,
813 channelIdx,
814 channel->devType ==
815 DMA_DEVICE_NONE ? "" :
816 DMA_gDeviceAttribute[channel->devType].
817 name);
818
819 rc =
820 request_irq(IRQ_DMA0C0 +
821 (controllerIdx *
822 DMA_NUM_CHANNELS) +
823 channelIdx,
824 dma_interrupt_handler,
825 IRQF_DISABLED, channel->name,
826 channel);
827 if (rc != 0) {
828 printk(KERN_ERR
829 "request_irq for IRQ_DMA%dC%d failed\n",
830 controllerIdx, channelIdx);
831 }
832 }
833 }
834 }
835
836 /* Create /proc/dma/channels and /proc/dma/devices */
837
838 gDmaDir = proc_mkdir("dma", NULL);
839
840 if (gDmaDir == NULL) {
841 printk(KERN_ERR "Unable to create /proc/dma\n");
842 } else {
843 create_proc_read_entry("channels", 0, gDmaDir,
844 dma_proc_read_channels, NULL);
845 create_proc_read_entry("devices", 0, gDmaDir,
846 dma_proc_read_devices, NULL);
847 create_proc_read_entry("mem-type", 0, gDmaDir,
848 dma_proc_read_mem_type, NULL);
849 }
850
851out:
852
853 up(&gDMA.lock);
854
855 return rc;
856}
857
858/****************************************************************************/
859/**
860* Reserves a channel for use with @a dev. If the device is setup to use
861* a shared channel, then this function will block until a free channel
862* becomes available.
863*
864* @return
865* >= 0 - A valid DMA Handle.
866* -EBUSY - Device is currently being used.
867* -ENODEV - Device handed in is invalid.
868*/
869/****************************************************************************/
870
871#if (DMA_DEBUG_TRACK_RESERVATION)
872DMA_Handle_t dma_request_channel_dbg
873 (DMA_Device_t dev, const char *fileName, int lineNum)
874#else
875DMA_Handle_t dma_request_channel(DMA_Device_t dev)
876#endif
877{
878 DMA_Handle_t handle;
879 DMA_DeviceAttribute_t *devAttr;
880 DMA_Channel_t *channel;
881 int controllerIdx;
882 int controllerIdx2;
883 int channelIdx;
884
885 if (down_interruptible(&gDMA.lock) < 0) {
886 return -ERESTARTSYS;
887 }
888
889 if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
890 handle = -ENODEV;
891 goto out;
892 }
893 devAttr = &DMA_gDeviceAttribute[dev];
894
895#if (DMA_DEBUG_TRACK_RESERVATION)
896 {
897 char *s;
898
899 s = strrchr(fileName, '/');
900 if (s != NULL) {
901 fileName = s + 1;
902 }
903 }
904#endif
905 if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
906 /* This device has already been requested and not been freed */
907
908 printk(KERN_ERR "%s: device %s is already requested\n",
909 __func__, devAttr->name);
910 handle = -EBUSY;
911 goto out;
912 }
913
914 if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
915 /* This device has a dedicated channel. */
916
917 channel =
918 &gDMA.controller[devAttr->dedicatedController].
919 channel[devAttr->dedicatedChannel];
920 if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
921 handle = -EBUSY;
922 goto out;
923 }
924
925 channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
926 devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
927
928#if (DMA_DEBUG_TRACK_RESERVATION)
929 channel->fileName = fileName;
930 channel->lineNum = lineNum;
931#endif
932 handle =
933 MAKE_HANDLE(devAttr->dedicatedController,
934 devAttr->dedicatedChannel);
935 goto out;
936 }
937
938 /* This device needs to use one of the shared channels. */
939
940 handle = DMA_INVALID_HANDLE;
941 while (handle == DMA_INVALID_HANDLE) {
942 /* Scan through the shared channels and see if one is available */
943
944 for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
945 controllerIdx2++) {
946 /* Check to see if we should try on controller 1 first. */
947
948 controllerIdx = controllerIdx2;
949 if ((devAttr->
950 flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
951 controllerIdx = 1 - controllerIdx;
952 }
953
954 /* See if the device is available on the controller being tested */
955
956 if ((devAttr->
957 flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
958 != 0) {
959 for (channelIdx = 0;
960 channelIdx < DMA_NUM_CHANNELS;
961 channelIdx++) {
962 channel =
963 &gDMA.controller[controllerIdx].
964 channel[channelIdx];
965
966 if (((channel->
967 flags &
968 DMA_CHANNEL_FLAG_IS_DEDICATED) ==
969 0)
970 &&
971 ((channel->
972 flags & DMA_CHANNEL_FLAG_IN_USE)
973 == 0)) {
974 if (((channel->
975 flags &
976 DMA_CHANNEL_FLAG_LARGE_FIFO)
977 != 0)
978 &&
979 ((devAttr->
980 flags &
981 DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
982 == 0)) {
983 /* This channel is a large fifo - don't tie it up */
984 /* with devices that we don't want using it. */
985
986 continue;
987 }
988
989 channel->flags |=
990 DMA_CHANNEL_FLAG_IN_USE;
991 channel->devType = dev;
992 devAttr->flags |=
993 DMA_DEVICE_FLAG_IN_USE;
994
995#if (DMA_DEBUG_TRACK_RESERVATION)
996 channel->fileName = fileName;
997 channel->lineNum = lineNum;
998#endif
999 handle =
1000 MAKE_HANDLE(controllerIdx,
1001 channelIdx);
1002
1003 /* Now that we've reserved the channel - we can go ahead and configure it */
1004
1005 if (ConfigChannel(handle) != 0) {
1006 handle = -EIO;
1007 printk(KERN_ERR
1008 "dma_request_channel: ConfigChannel failed\n");
1009 }
1010 goto out;
1011 }
1012 }
1013 }
1014 }
1015
1016 /* No channels are currently available. Let's wait for one to free up. */
1017
1018 {
1019 DEFINE_WAIT(wait);
1020
1021 prepare_to_wait(&gDMA.freeChannelQ, &wait,
1022 TASK_INTERRUPTIBLE);
1023 up(&gDMA.lock);
1024 schedule();
1025 finish_wait(&gDMA.freeChannelQ, &wait);
1026
1027 if (signal_pending(current)) {
1028 /* We don't currently hold gDMA.lock, so we return directly */
1029
1030 return -ERESTARTSYS;
1031 }
1032 }
1033
1034 if (down_interruptible(&gDMA.lock)) {
1035 return -ERESTARTSYS;
1036 }
1037 }
1038
1039out:
1040 up(&gDMA.lock);
1041
1042 return handle;
1043}
1044
1045/* Create both _dbg and non _dbg functions for modules. */
1046
1047#if (DMA_DEBUG_TRACK_RESERVATION)
1048#undef dma_request_channel
1049DMA_Handle_t dma_request_channel(DMA_Device_t dev)
1050{
1051 return dma_request_channel_dbg(dev, __FILE__, __LINE__);
1052}
1053
1054EXPORT_SYMBOL(dma_request_channel_dbg);
1055#endif
1056EXPORT_SYMBOL(dma_request_channel);
1057
1058/****************************************************************************/
1059/**
1060* Frees a previously allocated DMA Handle.
1061*/
1062/****************************************************************************/
1063
1064int dma_free_channel(DMA_Handle_t handle /* DMA handle. */
1065 ) {
1066 int rc = 0;
1067 DMA_Channel_t *channel;
1068 DMA_DeviceAttribute_t *devAttr;
1069
1070 if (down_interruptible(&gDMA.lock) < 0) {
1071 return -ERESTARTSYS;
1072 }
1073
1074 channel = HandleToChannel(handle);
1075 if (channel == NULL) {
1076 rc = -EINVAL;
1077 goto out;
1078 }
1079
1080 devAttr = &DMA_gDeviceAttribute[channel->devType];
1081
1082 if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
1083 channel->lastDevType = channel->devType;
1084 channel->devType = DMA_DEVICE_NONE;
1085 }
1086 channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
1087 devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
1088
1089out:
1090 up(&gDMA.lock);
1091
1092 wake_up_interruptible(&gDMA.freeChannelQ);
1093
1094 return rc;
1095}
1096
1097EXPORT_SYMBOL(dma_free_channel);
1098
1099/****************************************************************************/
1100/**
1101* Determines if a given device has been configured as using a shared
1102* channel.
1103*
1104* @return
1105* 0 Device uses a dedicated channel
1106* > zero Device uses a shared channel
1107* < zero Error code
1108*/
1109/****************************************************************************/
1110
1111int dma_device_is_channel_shared(DMA_Device_t device /* Device to check. */
1112 ) {
1113 DMA_DeviceAttribute_t *devAttr;
1114
1115 if (!IsDeviceValid(device)) {
1116 return -ENODEV;
1117 }
1118 devAttr = &DMA_gDeviceAttribute[device];
1119
1120 return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
1121}
1122
1123EXPORT_SYMBOL(dma_device_is_channel_shared);
1124
1125/****************************************************************************/
1126/**
1127* Allocates buffers for the descriptors. This is normally done automatically
1128* but needs to be done explicitly when initiating a dma from interrupt
1129* context.
1130*
1131* @return
1132* 0 Descriptors were allocated successfully
1133* -EINVAL Invalid device type for this kind of transfer
1134* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
1135* -ENOMEM Memory exhausted
1136*/
1137/****************************************************************************/
1138
1139int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */
1140 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
1141 dma_addr_t srcData, /* Place to get data to write to device */
1142 dma_addr_t dstData, /* Pointer to device data address */
1143 size_t numBytes /* Number of bytes to transfer to the device */
1144 ) {
1145 DMA_Channel_t *channel;
1146 DMA_DeviceAttribute_t *devAttr;
1147 int numDescriptors;
1148 size_t ringBytesRequired;
1149 int rc = 0;
1150
1151 channel = HandleToChannel(handle);
1152 if (channel == NULL) {
1153 return -ENODEV;
1154 }
1155
1156 devAttr = &DMA_gDeviceAttribute[channel->devType];
1157
1158 if (devAttr->config.transferType != transferType) {
1159 return -EINVAL;
1160 }
1161
1162 /* Figure out how many descriptors we need. */
1163
1164 /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
1165 /* srcData, dstData, numBytes); */
1166
1167 numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
1168 (void *)srcData,
1169 (void *)dstData,
1170 numBytes);
1171 if (numDescriptors < 0) {
1172 printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
1173 __func__);
1174 return -EINVAL;
1175 }
1176
1177 /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
1178 /* a new one. */
1179
1180 ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
1181
1182 /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
1183
1184 if (ringBytesRequired > devAttr->ring.bytesAllocated) {
1185 /* Make sure that this code path is never taken from interrupt context. */
1186 /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
1187 /* allocation needs to have already been done. */
1188
1189 might_sleep();
1190
1191 /* Free the old descriptor ring and allocate a new one. */
1192
1193 dma_free_descriptor_ring(&devAttr->ring);
1194
1195 /* And allocate a new one. */
1196
1197 rc =
1198 dma_alloc_descriptor_ring(&devAttr->ring,
1199 numDescriptors);
1200 if (rc < 0) {
1201 printk(KERN_ERR
1202 "%s: dma_alloc_descriptor_ring(%d) failed\n",
1203 __func__, numDescriptors);
1204 return rc;
1205 }
1206 /* Setup the descriptor for this transfer */
1207
1208 if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
1209 devAttr->ring.physAddr,
1210 devAttr->ring.bytesAllocated,
1211 numDescriptors) < 0) {
1212 printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
1213 __func__);
1214 return -EINVAL;
1215 }
1216 } else {
1217 /* We've already got enough ring buffer allocated. All we need to do is reset */
1218 /* any control information, just in case the previous DMA was stopped. */
1219
1220 dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
1221 }
1222
1223 /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
1224 /* as last time, then we don't need to call setDataDescriptor again. */
1225
1226 if (dmacHw_setDataDescriptor(&devAttr->config,
1227 devAttr->ring.virtAddr,
1228 (void *)srcData,
1229 (void *)dstData, numBytes) < 0) {
1230 printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
1231 __func__);
1232 return -EINVAL;
1233 }
1234
1235 /* Remember the critical information for this transfer so that we can eliminate */
1236 /* another call to dma_alloc_descriptors if the caller reuses the same buffers */
1237
1238 devAttr->prevSrcData = srcData;
1239 devAttr->prevDstData = dstData;
1240 devAttr->prevNumBytes = numBytes;
1241
1242 return 0;
1243}
1244
1245EXPORT_SYMBOL(dma_alloc_descriptors);
1246
1247/****************************************************************************/
1248/**
1249* Allocates and sets up descriptors for a double buffered circular buffer.
1250*
1251* This is primarily intended to be used for things like the ingress samples
1252* from a microphone.
1253*
1254* @return
1255* > 0 Number of descriptors actually allocated.
1256* -EINVAL Invalid device type for this kind of transfer
1257* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
1258* -ENOMEM Memory exhausted
1259*/
1260/****************************************************************************/
1261
1262int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
1263 dma_addr_t srcData, /* Physical address of source data */
1264 dma_addr_t dstData1, /* Physical address of first destination buffer */
1265 dma_addr_t dstData2, /* Physical address of second destination buffer */
1266 size_t numBytes /* Number of bytes in each destination buffer */
1267 ) {
1268 DMA_Channel_t *channel;
1269 DMA_DeviceAttribute_t *devAttr;
1270 int numDst1Descriptors;
1271 int numDst2Descriptors;
1272 int numDescriptors;
1273 size_t ringBytesRequired;
1274 int rc = 0;
1275
1276 channel = HandleToChannel(handle);
1277 if (channel == NULL) {
1278 return -ENODEV;
1279 }
1280
1281 devAttr = &DMA_gDeviceAttribute[channel->devType];
1282
1283 /* Figure out how many descriptors we need. */
1284
1285 /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
1286 /* srcData, dstData, numBytes); */
1287
1288 numDst1Descriptors =
1289 dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
1290 (void *)dstData1, numBytes);
1291 if (numDst1Descriptors < 0) {
1292 return -EINVAL;
1293 }
1294 numDst2Descriptors =
1295 dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
1296 (void *)dstData2, numBytes);
1297 if (numDst2Descriptors < 0) {
1298 return -EINVAL;
1299 }
1300 numDescriptors = numDst1Descriptors + numDst2Descriptors;
1301 /* printk("numDescriptors: %d\n", numDescriptors); */
1302
1303 /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
1304 /* a new one. */
1305
1306 ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
1307
1308 /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
1309
1310 if (ringBytesRequired > devAttr->ring.bytesAllocated) {
1311 /* Make sure that this code path is never taken from interrupt context. */
1312 /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
1313 /* allocation needs to have already been done. */
1314
1315 might_sleep();
1316
1317 /* Free the old descriptor ring and allocate a new one. */
1318
1319 dma_free_descriptor_ring(&devAttr->ring);
1320
1321 /* And allocate a new one. */
1322
1323 rc =
1324 dma_alloc_descriptor_ring(&devAttr->ring,
1325 numDescriptors);
1326 if (rc < 0) {
1327 printk(KERN_ERR
1328 "%s: dma_alloc_descriptor_ring(%d) failed\n",
1329 __func__, ringBytesRequired);
1330 return rc;
1331 }
1332 }
1333
1334 /* Setup the descriptor for this transfer. Since this function is used with */
1335 /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
1336 /* setDataDescriptor will keep trying to append onto the end. */
1337
1338 if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
1339 devAttr->ring.physAddr,
1340 devAttr->ring.bytesAllocated,
1341 numDescriptors) < 0) {
1342 printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
1343 return -EINVAL;
1344 }
1345
1346 /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
1347 /* as last time, then we don't need to call setDataDescriptor again. */
1348
1349 if (dmacHw_setDataDescriptor(&devAttr->config,
1350 devAttr->ring.virtAddr,
1351 (void *)srcData,
1352 (void *)dstData1, numBytes) < 0) {
1353 printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
1354 __func__);
1355 return -EINVAL;
1356 }
1357 if (dmacHw_setDataDescriptor(&devAttr->config,
1358 devAttr->ring.virtAddr,
1359 (void *)srcData,
1360 (void *)dstData2, numBytes) < 0) {
1361 printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
1362 __func__);
1363 return -EINVAL;
1364 }
1365
1366 /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
1367 /* try to make the 'prev' variables right. */
1368
1369 devAttr->prevSrcData = 0;
1370 devAttr->prevDstData = 0;
1371 devAttr->prevNumBytes = 0;
1372
1373 return numDescriptors;
1374}
1375
1376EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
1377
1378/****************************************************************************/
1379/**
1380* Initiates a transfer when the descriptors have already been setup.
1381*
1382* This is a special case, and normally, the dma_transfer_xxx functions should
1383* be used.
1384*
1385* @return
1386* 0 Transfer was started successfully
1387* -ENODEV Invalid handle
1388*/
1389/****************************************************************************/
1390
1391int dma_start_transfer(DMA_Handle_t handle)
1392{
1393 DMA_Channel_t *channel;
1394 DMA_DeviceAttribute_t *devAttr;
1395
1396 channel = HandleToChannel(handle);
1397 if (channel == NULL) {
1398 return -ENODEV;
1399 }
1400 devAttr = &DMA_gDeviceAttribute[channel->devType];
1401
1402 dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
1403 devAttr->ring.virtAddr);
1404
1405 /* Since we got this far, everything went successfully */
1406
1407 return 0;
1408}
1409
1410EXPORT_SYMBOL(dma_start_transfer);
1411
1412/****************************************************************************/
1413/**
1414* Stops a previously started DMA transfer.
1415*
1416* @return
1417* 0 Transfer was stopped successfully
1418* -ENODEV Invalid handle
1419*/
1420/****************************************************************************/
1421
1422int dma_stop_transfer(DMA_Handle_t handle)
1423{
1424 DMA_Channel_t *channel;
1425
1426 channel = HandleToChannel(handle);
1427 if (channel == NULL) {
1428 return -ENODEV;
1429 }
1430
1431 dmacHw_stopTransfer(channel->dmacHwHandle);
1432
1433 return 0;
1434}
1435
1436EXPORT_SYMBOL(dma_stop_transfer);
1437
1438/****************************************************************************/
1439/**
1440* Waits for a DMA to complete by polling. This function is only intended
1441* to be used for testing. Interrupts should be used for most DMA operations.
1442*/
1443/****************************************************************************/
1444
1445int dma_wait_transfer_done(DMA_Handle_t handle)
1446{
1447 DMA_Channel_t *channel;
1448 dmacHw_TRANSFER_STATUS_e status;
1449
1450 channel = HandleToChannel(handle);
1451 if (channel == NULL) {
1452 return -ENODEV;
1453 }
1454
1455 while ((status =
1456 dmacHw_transferCompleted(channel->dmacHwHandle)) ==
1457 dmacHw_TRANSFER_STATUS_BUSY) {
1458 ;
1459 }
1460
1461 if (status == dmacHw_TRANSFER_STATUS_ERROR) {
1462 printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
1463 return -EIO;
1464 }
1465 return 0;
1466}
1467
1468EXPORT_SYMBOL(dma_wait_transfer_done);
1469
1470/****************************************************************************/
1471/**
1472* Initiates a DMA, allocating the descriptors as required.
1473*
1474* @return
1475* 0 Transfer was started successfully
1476* -EINVAL Invalid device type for this kind of transfer
1477* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
1478*/
1479/****************************************************************************/
1480
1481int dma_transfer(DMA_Handle_t handle, /* DMA Handle */
1482 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
1483 dma_addr_t srcData, /* Place to get data to write to device */
1484 dma_addr_t dstData, /* Pointer to device data address */
1485 size_t numBytes /* Number of bytes to transfer to the device */
1486 ) {
1487 DMA_Channel_t *channel;
1488 DMA_DeviceAttribute_t *devAttr;
1489 int rc = 0;
1490
1491 channel = HandleToChannel(handle);
1492 if (channel == NULL) {
1493 return -ENODEV;
1494 }
1495
1496 devAttr = &DMA_gDeviceAttribute[channel->devType];
1497
1498 if (devAttr->config.transferType != transferType) {
1499 return -EINVAL;
1500 }
1501
1502 /* We keep track of the information about the previous request for this */
1503 /* device, and if the attributes match, then we can use the descriptors we setup */
1504 /* the last time, and not have to reinitialize everything. */
1505
1506 {
1507 rc =
1508 dma_alloc_descriptors(handle, transferType, srcData,
1509 dstData, numBytes);
1510 if (rc != 0) {
1511 return rc;
1512 }
1513 }
1514
1515 /* And kick off the transfer */
1516
1517 devAttr->numBytes = numBytes;
1518 devAttr->transferStartTime = timer_get_tick_count();
1519
1520 dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
1521 devAttr->ring.virtAddr);
1522
1523 /* Since we got this far, everything went successfully */
1524
1525 return 0;
1526}
1527
1528EXPORT_SYMBOL(dma_transfer);
1529
1530/****************************************************************************/
1531/**
1532* Set the callback function which will be called when a transfer completes.
1533* If a NULL callback function is set, then no callback will occur.
1534*
1535* @note @a devHandler will be called from IRQ context.
1536*
1537* @return
1538* 0 - Success
1539* -ENODEV - Device handed in is invalid.
1540*/
1541/****************************************************************************/
1542
1543int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */
1544 DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */
1545 void *userData /* Pointer which will be passed to devHandler. */
1546 ) {
1547 DMA_DeviceAttribute_t *devAttr;
1548 unsigned long flags;
1549
1550 if (!IsDeviceValid(dev)) {
1551 return -ENODEV;
1552 }
1553 devAttr = &DMA_gDeviceAttribute[dev];
1554
1555 local_irq_save(flags);
1556
1557 devAttr->userData = userData;
1558 devAttr->devHandler = devHandler;
1559
1560 local_irq_restore(flags);
1561
1562 return 0;
1563}
1564
1565EXPORT_SYMBOL(dma_set_device_handler);
1566
1567/****************************************************************************/
1568/**
1569* Initializes a memory mapping structure
1570*/
1571/****************************************************************************/
1572
1573int dma_init_mem_map(DMA_MemMap_t *memMap)
1574{
1575 memset(memMap, 0, sizeof(*memMap));
1576
1577 sema_init(&memMap->lock, 1);
1578
1579 return 0;
1580}
1581
1582EXPORT_SYMBOL(dma_init_mem_map);
1583
1584/****************************************************************************/
1585/**
1586* Releases any memory currently being held by a memory mapping structure.
1587*/
1588/****************************************************************************/
1589
1590int dma_term_mem_map(DMA_MemMap_t *memMap)
1591{
1592 down(&memMap->lock); /* Just being paranoid */
1593
1594 /* Free up any allocated memory */
1595
1596 up(&memMap->lock);
1597 memset(memMap, 0, sizeof(*memMap));
1598
1599 return 0;
1600}
1601
1602EXPORT_SYMBOL(dma_term_mem_map);
1603
1604/****************************************************************************/
1605/**
1606* Looks at a memory address and categorizes it.
1607*
1608* @return One of the values from the DMA_MemType_t enumeration.
1609*/
1610/****************************************************************************/
1611
1612DMA_MemType_t dma_mem_type(void *addr)
1613{
1614 unsigned long addrVal = (unsigned long)addr;
1615
1616 if (addrVal >= VMALLOC_END) {
1617 /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
1618
1619 /* dma_alloc_xxx pages are physically and virtually contiguous */
1620
1621 return DMA_MEM_TYPE_DMA;
1622 }
1623
1624 /* Technically, we could add one more classification. Addresses between VMALLOC_END */
1625 /* and the beginning of the DMA virtual address could be considered to be I/O space. */
1626 /* Right now, nobody cares about this particular classification, so we ignore it. */
1627
1628 if (is_vmalloc_addr(addr)) {
1629 /* Address comes from the vmalloc'd region. Pages are virtually */
1630 /* contiguous but NOT physically contiguous */
1631
1632 return DMA_MEM_TYPE_VMALLOC;
1633 }
1634
1635 if (addrVal >= PAGE_OFFSET) {
1636 /* PAGE_OFFSET is typically 0xC0000000 */
1637
1638 /* kmalloc'd pages are physically contiguous */
1639
1640 return DMA_MEM_TYPE_KMALLOC;
1641 }
1642
1643 return DMA_MEM_TYPE_USER;
1644}
1645
1646EXPORT_SYMBOL(dma_mem_type);
1647
1648/****************************************************************************/
1649/**
1650* Looks at a memory address and determines if we support DMA'ing to/from
1651* that type of memory.
1652*
1653* @return boolean -
1654* return value != 0 means dma supported
1655* return value == 0 means dma not supported
1656*/
1657/****************************************************************************/
1658
1659int dma_mem_supports_dma(void *addr)
1660{
1661 DMA_MemType_t memType = dma_mem_type(addr);
1662
1663 return (memType == DMA_MEM_TYPE_DMA)
1664#if ALLOW_MAP_OF_KMALLOC_MEMORY
1665 || (memType == DMA_MEM_TYPE_KMALLOC)
1666#endif
1667 || (memType == DMA_MEM_TYPE_USER);
1668}
1669
1670EXPORT_SYMBOL(dma_mem_supports_dma);
1671
1672/****************************************************************************/
1673/**
1674* Maps in a memory region such that it can be used for performing a DMA.
1675*
1676* @return
1677*/
1678/****************************************************************************/
1679
1680int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
1681 enum dma_data_direction dir /* Direction that the mapping will be going */
1682 ) {
1683 int rc;
1684
1685 down(&memMap->lock);
1686
1687 DMA_MAP_PRINT("memMap: %p\n", memMap);
1688
1689 if (memMap->inUse) {
1690 printk(KERN_ERR "%s: memory map %p is already being used\n",
1691 __func__, memMap);
1692 rc = -EBUSY;
1693 goto out;
1694 }
1695
1696 memMap->inUse = 1;
1697 memMap->dir = dir;
1698 memMap->numRegionsUsed = 0;
1699
1700 rc = 0;
1701
1702out:
1703
1704 DMA_MAP_PRINT("returning %d", rc);
1705
1706 up(&memMap->lock);
1707
1708 return rc;
1709}
1710
1711EXPORT_SYMBOL(dma_map_start);
1712
1713/****************************************************************************/
1714/**
1715* Adds a segment of memory to a memory map. Each segment is both
1716* physically and virtually contiguous.
1717*
1718* @return 0 on success, error code otherwise.
1719*/
1720/****************************************************************************/
1721
1722static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */
1723 DMA_Region_t *region, /* Region that the segment belongs to */
1724 void *virtAddr, /* Virtual address of the segment being added */
1725 dma_addr_t physAddr, /* Physical address of the segment being added */
1726 size_t numBytes /* Number of bytes of the segment being added */
1727 ) {
1728 DMA_Segment_t *segment;
1729
1730 DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr,
1731 physAddr, numBytes);
1732
1733 /* Sanity check */
1734
1735 if (((unsigned long)virtAddr < (unsigned long)region->virtAddr)
1736 || (((unsigned long)virtAddr + numBytes)) >
1737 ((unsigned long)region->virtAddr + region->numBytes)) {
1738 printk(KERN_ERR
1739 "%s: virtAddr %p is outside region @ %p len: %d\n",
1740 __func__, virtAddr, region->virtAddr, region->numBytes);
1741 return -EINVAL;
1742 }
1743
1744 if (region->numSegmentsUsed > 0) {
1745 /* Check to see if this segment is physically contiguous with the previous one */
1746
1747 segment = &region->segment[region->numSegmentsUsed - 1];
1748
1749 if ((segment->physAddr + segment->numBytes) == physAddr) {
1750 /* It is - just add on to the end */
1751
1752 DMA_MAP_PRINT("appending %d bytes to last segment\n",
1753 numBytes);
1754
1755 segment->numBytes += numBytes;
1756
1757 return 0;
1758 }
1759 }
1760
1761 /* Reallocate to hold more segments, if required. */
1762
1763 if (region->numSegmentsUsed >= region->numSegmentsAllocated) {
1764 DMA_Segment_t *newSegment;
1765 size_t oldSize =
1766 region->numSegmentsAllocated * sizeof(*newSegment);
1767 int newAlloc = region->numSegmentsAllocated + 4;
1768 size_t newSize = newAlloc * sizeof(*newSegment);
1769
1770 newSegment = kmalloc(newSize, GFP_KERNEL);
1771 if (newSegment == NULL) {
1772 return -ENOMEM;
1773 }
1774 memcpy(newSegment, region->segment, oldSize);
1775 memset(&((uint8_t *) newSegment)[oldSize], 0,
1776 newSize - oldSize);
1777 kfree(region->segment);
1778
1779 region->numSegmentsAllocated = newAlloc;
1780 region->segment = newSegment;
1781 }
1782
1783 segment = &region->segment[region->numSegmentsUsed];
1784 region->numSegmentsUsed++;
1785
1786 segment->virtAddr = virtAddr;
1787 segment->physAddr = physAddr;
1788 segment->numBytes = numBytes;
1789
1790 DMA_MAP_PRINT("returning success\n");
1791
1792 return 0;
1793}
1794
1795/****************************************************************************/
1796/**
1797* Adds a region of memory to a memory map. Each region is virtually
1798* contiguous, but not necessarily physically contiguous.
1799*
1800* @return 0 on success, error code otherwise.
1801*/
1802/****************************************************************************/
1803
1804int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
1805 void *mem, /* Virtual address that we want to get a map of */
1806 size_t numBytes /* Number of bytes being mapped */
1807 ) {
1808 unsigned long addr = (unsigned long)mem;
1809 unsigned int offset;
1810 int rc = 0;
1811 DMA_Region_t *region;
1812 dma_addr_t physAddr;
1813
1814 down(&memMap->lock);
1815
1816 DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes);
1817
1818 if (!memMap->inUse) {
1819 printk(KERN_ERR "%s: Make sure you call dma_map_start first\n",
1820 __func__);
1821 rc = -EINVAL;
1822 goto out;
1823 }
1824
1825 /* Reallocate to hold more regions. */
1826
1827 if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) {
1828 DMA_Region_t *newRegion;
1829 size_t oldSize =
1830 memMap->numRegionsAllocated * sizeof(*newRegion);
1831 int newAlloc = memMap->numRegionsAllocated + 4;
1832 size_t newSize = newAlloc * sizeof(*newRegion);
1833
1834 newRegion = kmalloc(newSize, GFP_KERNEL);
1835 if (newRegion == NULL) {
1836 rc = -ENOMEM;
1837 goto out;
1838 }
1839 memcpy(newRegion, memMap->region, oldSize);
1840 memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize);
1841
1842 kfree(memMap->region);
1843
1844 memMap->numRegionsAllocated = newAlloc;
1845 memMap->region = newRegion;
1846 }
1847
1848 region = &memMap->region[memMap->numRegionsUsed];
1849 memMap->numRegionsUsed++;
1850
1851 offset = addr & ~PAGE_MASK;
1852
1853 region->memType = dma_mem_type(mem);
1854 region->virtAddr = mem;
1855 region->numBytes = numBytes;
1856 region->numSegmentsUsed = 0;
1857 region->numLockedPages = 0;
1858 region->lockedPages = NULL;
1859
1860 switch (region->memType) {
1861 case DMA_MEM_TYPE_VMALLOC:
1862 {
1863 atomic_inc(&gDmaStatMemTypeVmalloc);
1864
1865 /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */
1866
1867 /* vmalloc'd pages are not physically contiguous */
1868
1869 rc = -EINVAL;
1870 break;
1871 }
1872
1873 case DMA_MEM_TYPE_KMALLOC:
1874 {
1875 atomic_inc(&gDmaStatMemTypeKmalloc);
1876
1877 /* kmalloc'd pages are physically contiguous, so they'll have exactly */
1878 /* one segment */
1879
1880#if ALLOW_MAP_OF_KMALLOC_MEMORY
1881 physAddr =
1882 dma_map_single(NULL, mem, numBytes, memMap->dir);
1883 rc = dma_map_add_segment(memMap, region, mem, physAddr,
1884 numBytes);
1885#else
1886 rc = -EINVAL;
1887#endif
1888 break;
1889 }
1890
1891 case DMA_MEM_TYPE_DMA:
1892 {
1893 /* dma_alloc_xxx pages are physically contiguous */
1894
1895 atomic_inc(&gDmaStatMemTypeCoherent);
1896
1897 physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset;
1898
1899 dma_sync_single_for_cpu(NULL, physAddr, numBytes,
1900 memMap->dir);
1901 rc = dma_map_add_segment(memMap, region, mem, physAddr,
1902 numBytes);
1903 break;
1904 }
1905
1906 case DMA_MEM_TYPE_USER:
1907 {
1908 size_t firstPageOffset;
1909 size_t firstPageSize;
1910 struct page **pages;
1911 struct task_struct *userTask;
1912
1913 atomic_inc(&gDmaStatMemTypeUser);
1914
1915#if 1
1916 /* If the pages are user pages, then the dma_mem_map_set_user_task function */
1917 /* must have been previously called. */
1918
1919 if (memMap->userTask == NULL) {
1920 printk(KERN_ERR
1921 "%s: must call dma_mem_map_set_user_task when using user-mode memory\n",
1922 __func__);
1923 return -EINVAL;
1924 }
1925
1926 /* User pages need to be locked. */
1927
1928 firstPageOffset =
1929 (unsigned long)region->virtAddr & (PAGE_SIZE - 1);
1930 firstPageSize = PAGE_SIZE - firstPageOffset;
1931
1932 region->numLockedPages = (firstPageOffset
1933 + region->numBytes +
1934 PAGE_SIZE - 1) / PAGE_SIZE;
1935 pages =
1936 kmalloc(region->numLockedPages *
1937 sizeof(struct page *), GFP_KERNEL);
1938
1939 if (pages == NULL) {
1940 region->numLockedPages = 0;
1941 return -ENOMEM;
1942 }
1943
1944 userTask = memMap->userTask;
1945
1946 down_read(&userTask->mm->mmap_sem);
1947 rc = get_user_pages(userTask, /* task */
1948 userTask->mm, /* mm */
1949 (unsigned long)region->virtAddr, /* start */
1950 region->numLockedPages, /* len */
1951 memMap->dir == DMA_FROM_DEVICE, /* write */
1952 0, /* force */
1953 pages, /* pages (array of pointers to page) */
1954 NULL); /* vmas */
1955 up_read(&userTask->mm->mmap_sem);
1956
1957 if (rc != region->numLockedPages) {
1958 kfree(pages);
1959 region->numLockedPages = 0;
1960
1961 if (rc >= 0) {
1962 rc = -EINVAL;
1963 }
1964 } else {
1965 uint8_t *virtAddr = region->virtAddr;
1966 size_t bytesRemaining;
1967 int pageIdx;
1968
1969 rc = 0; /* Since get_user_pages returns +ve number */
1970
1971 region->lockedPages = pages;
1972
1973 /* We've locked the user pages. Now we need to walk them and figure */
1974 /* out the physical addresses. */
1975
1976 /* The first page may be partial */
1977
1978 dma_map_add_segment(memMap,
1979 region,
1980 virtAddr,
1981 PFN_PHYS(page_to_pfn
1982 (pages[0])) +
1983 firstPageOffset,
1984 firstPageSize);
1985
1986 virtAddr += firstPageSize;
1987 bytesRemaining =
1988 region->numBytes - firstPageSize;
1989
1990 for (pageIdx = 1;
1991 pageIdx < region->numLockedPages;
1992 pageIdx++) {
1993 size_t bytesThisPage =
1994 (bytesRemaining >
1995 PAGE_SIZE ? PAGE_SIZE :
1996 bytesRemaining);
1997
1998 DMA_MAP_PRINT
1999 ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n",
2000 pageIdx, pages[pageIdx],
2001 page_to_pfn(pages[pageIdx]),
2002 PFN_PHYS(page_to_pfn
2003 (pages[pageIdx])));
2004
2005 dma_map_add_segment(memMap,
2006 region,
2007 virtAddr,
2008 PFN_PHYS(page_to_pfn
2009 (pages
2010 [pageIdx])),
2011 bytesThisPage);
2012
2013 virtAddr += bytesThisPage;
2014 bytesRemaining -= bytesThisPage;
2015 }
2016 }
2017#else
2018 printk(KERN_ERR
2019 "%s: User mode pages are not yet supported\n",
2020 __func__);
2021
2022 /* user pages are not physically contiguous */
2023
2024 rc = -EINVAL;
2025#endif
2026 break;
2027 }
2028
2029 default:
2030 {
2031 printk(KERN_ERR "%s: Unsupported memory type: %d\n",
2032 __func__, region->memType);
2033
2034 rc = -EINVAL;
2035 break;
2036 }
2037 }
2038
2039 if (rc != 0) {
2040 memMap->numRegionsUsed--;
2041 }
2042
2043out:
2044
2045 DMA_MAP_PRINT("returning %d\n", rc);
2046
2047 up(&memMap->lock);
2048
2049 return rc;
2050}
2051
2052EXPORT_SYMBOL(dma_map_add_segment);
2053
2054/****************************************************************************/
2055/**
2056* Maps in a memory region such that it can be used for performing a DMA.
2057*
2058* @return 0 on success, error code otherwise.
2059*/
2060/****************************************************************************/
2061
2062int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
2063 void *mem, /* Virtual address that we want to get a map of */
2064 size_t numBytes, /* Number of bytes being mapped */
2065 enum dma_data_direction dir /* Direction that the mapping will be going */
2066 ) {
2067 int rc;
2068
2069 rc = dma_map_start(memMap, dir);
2070 if (rc == 0) {
2071 rc = dma_map_add_region(memMap, mem, numBytes);
2072 if (rc < 0) {
2073 /* Since the add fails, this function will fail, and the caller won't */
2074 /* call unmap, so we need to do it here. */
2075
2076 dma_unmap(memMap, 0);
2077 }
2078 }
2079
2080 return rc;
2081}
2082
2083EXPORT_SYMBOL(dma_map_mem);
2084
2085/****************************************************************************/
2086/**
2087* Setup a descriptor ring for a given memory map.
2088*
2089* It is assumed that the descriptor ring has already been initialized, and
2090* this routine will only reallocate a new descriptor ring if the existing
2091* one is too small.
2092*
2093* @return 0 on success, error code otherwise.
2094*/
2095/****************************************************************************/
2096
2097int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
2098 DMA_MemMap_t *memMap, /* Memory map that will be used */
2099 dma_addr_t devPhysAddr /* Physical address of device */
2100 ) {
2101 int rc;
2102 int numDescriptors;
2103 DMA_DeviceAttribute_t *devAttr;
2104 DMA_Region_t *region;
2105 DMA_Segment_t *segment;
2106 dma_addr_t srcPhysAddr;
2107 dma_addr_t dstPhysAddr;
2108 int regionIdx;
2109 int segmentIdx;
2110
2111 devAttr = &DMA_gDeviceAttribute[dev];
2112
2113 down(&memMap->lock);
2114
2115 /* Figure out how many descriptors we need */
2116
2117 numDescriptors = 0;
2118 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2119 region = &memMap->region[regionIdx];
2120
2121 for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
2122 segmentIdx++) {
2123 segment = &region->segment[segmentIdx];
2124
2125 if (memMap->dir == DMA_TO_DEVICE) {
2126 srcPhysAddr = segment->physAddr;
2127 dstPhysAddr = devPhysAddr;
2128 } else {
2129 srcPhysAddr = devPhysAddr;
2130 dstPhysAddr = segment->physAddr;
2131 }
2132
2133 rc =
2134 dma_calculate_descriptor_count(dev, srcPhysAddr,
2135 dstPhysAddr,
2136 segment->
2137 numBytes);
2138 if (rc < 0) {
2139 printk(KERN_ERR
2140 "%s: dma_calculate_descriptor_count failed: %d\n",
2141 __func__, rc);
2142 goto out;
2143 }
2144 numDescriptors += rc;
2145 }
2146 }
2147
2148 /* Adjust the size of the ring, if it isn't big enough */
2149
2150 if (numDescriptors > devAttr->ring.descriptorsAllocated) {
2151 dma_free_descriptor_ring(&devAttr->ring);
2152 rc =
2153 dma_alloc_descriptor_ring(&devAttr->ring,
2154 numDescriptors);
2155 if (rc < 0) {
2156 printk(KERN_ERR
2157 "%s: dma_alloc_descriptor_ring failed: %d\n",
2158 __func__, rc);
2159 goto out;
2160 }
2161 } else {
2162 rc =
2163 dma_init_descriptor_ring(&devAttr->ring,
2164 numDescriptors);
2165 if (rc < 0) {
2166 printk(KERN_ERR
2167 "%s: dma_init_descriptor_ring failed: %d\n",
2168 __func__, rc);
2169 goto out;
2170 }
2171 }
2172
2173 /* Populate the descriptors */
2174
2175 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2176 region = &memMap->region[regionIdx];
2177
2178 for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
2179 segmentIdx++) {
2180 segment = &region->segment[segmentIdx];
2181
2182 if (memMap->dir == DMA_TO_DEVICE) {
2183 srcPhysAddr = segment->physAddr;
2184 dstPhysAddr = devPhysAddr;
2185 } else {
2186 srcPhysAddr = devPhysAddr;
2187 dstPhysAddr = segment->physAddr;
2188 }
2189
2190 rc =
2191 dma_add_descriptors(&devAttr->ring, dev,
2192 srcPhysAddr, dstPhysAddr,
2193 segment->numBytes);
2194 if (rc < 0) {
2195 printk(KERN_ERR
2196 "%s: dma_add_descriptors failed: %d\n",
2197 __func__, rc);
2198 goto out;
2199 }
2200 }
2201 }
2202
2203 rc = 0;
2204
2205out:
2206
2207 up(&memMap->lock);
2208 return rc;
2209}
2210
2211EXPORT_SYMBOL(dma_map_create_descriptor_ring);
2212
2213/****************************************************************************/
2214/**
2215* Maps in a memory region such that it can be used for performing a DMA.
2216*
2217* @return
2218*/
2219/****************************************************************************/
2220
2221int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
2222 int dirtied /* non-zero if any of the pages were modified */
2223 ) {
2224
2225 int rc = 0;
2226 int regionIdx;
2227 int segmentIdx;
2228 DMA_Region_t *region;
2229 DMA_Segment_t *segment;
2230
2231 down(&memMap->lock);
2232
2233 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2234 region = &memMap->region[regionIdx];
2235
2236 for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
2237 segmentIdx++) {
2238 segment = &region->segment[segmentIdx];
2239
2240 switch (region->memType) {
2241 case DMA_MEM_TYPE_VMALLOC:
2242 {
2243 printk(KERN_ERR
2244 "%s: vmalloc'd pages are not yet supported\n",
2245 __func__);
2246 rc = -EINVAL;
2247 goto out;
2248 }
2249
2250 case DMA_MEM_TYPE_KMALLOC:
2251 {
2252#if ALLOW_MAP_OF_KMALLOC_MEMORY
2253 dma_unmap_single(NULL,
2254 segment->physAddr,
2255 segment->numBytes,
2256 memMap->dir);
2257#endif
2258 break;
2259 }
2260
2261 case DMA_MEM_TYPE_DMA:
2262 {
2263 dma_sync_single_for_cpu(NULL,
2264 segment->
2265 physAddr,
2266 segment->
2267 numBytes,
2268 memMap->dir);
2269 break;
2270 }
2271
2272 case DMA_MEM_TYPE_USER:
2273 {
2274 /* Nothing to do here. */
2275
2276 break;
2277 }
2278
2279 default:
2280 {
2281 printk(KERN_ERR
2282 "%s: Unsupported memory type: %d\n",
2283 __func__, region->memType);
2284 rc = -EINVAL;
2285 goto out;
2286 }
2287 }
2288
2289 segment->virtAddr = NULL;
2290 segment->physAddr = 0;
2291 segment->numBytes = 0;
2292 }
2293
2294 if (region->numLockedPages > 0) {
2295 int pageIdx;
2296
2297 /* Some user pages were locked. We need to go and unlock them now. */
2298
2299 for (pageIdx = 0; pageIdx < region->numLockedPages;
2300 pageIdx++) {
2301 struct page *page =
2302 region->lockedPages[pageIdx];
2303
2304 if (memMap->dir == DMA_FROM_DEVICE) {
2305 SetPageDirty(page);
2306 }
2307 page_cache_release(page);
2308 }
2309 kfree(region->lockedPages);
2310 region->numLockedPages = 0;
2311 region->lockedPages = NULL;
2312 }
2313
2314 region->memType = DMA_MEM_TYPE_NONE;
2315 region->virtAddr = NULL;
2316 region->numBytes = 0;
2317 region->numSegmentsUsed = 0;
2318 }
2319 memMap->userTask = NULL;
2320 memMap->numRegionsUsed = 0;
2321 memMap->inUse = 0;
2322
2323out:
2324 up(&memMap->lock);
2325
2326 return rc;
2327}
2328
2329EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
new file mode 100644
index 00000000000..ca0ad736870
--- /dev/null
+++ b/arch/arm/mach-bcmring/dma_device.c
@@ -0,0 +1,593 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dma_device.c
18*
19* @brief private array of DMA_DeviceAttribute_t
20*/
21/****************************************************************************/
22
23DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
24 [DMA_DEVICE_MEM_TO_MEM] = /* MEM 2 MEM */
25 {
26 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
27 .name = "mem-to-mem",
28 .config = {
29 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
30 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
31 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
32 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
33 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
34 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
35 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
36 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
37 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
38 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
39 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
40
41 },
42 },
43 [DMA_DEVICE_VPM_MEM_TO_MEM] = /* VPM */
44 {
45 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
46 .name = "vpm",
47 .dedicatedController = 0,
48 .dedicatedChannel = 0,
49 /* reserve DMA0:0 for VPM */
50 },
51 [DMA_DEVICE_NAND_MEM_TO_MEM] = /* NAND */
52 {
53 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
54 .name = "nand",
55 .config = {
56 .srcPeripheralPort = 0,
57 .dstPeripheralPort = 0,
58 .srcStatusRegisterAddress = 0x00000000,
59 .dstStatusRegisterAddress = 0x00000000,
60 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
61 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
62 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
63 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
64 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
65 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
66 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
67 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
68 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
69 .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
70 },
71 },
72 [DMA_DEVICE_PIF_MEM_TO_DEV] = /* PIF TX */
73 {
74 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
75 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
76 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
77 .name = "pif_tx",
78 .dmacPort = {14, 5},
79 .config = {
80 .srcPeripheralPort = 0, /* SRC: memory */
81 /* dstPeripheralPort = 5 or 14 */
82 .srcStatusRegisterAddress = 0x00000000,
83 .dstStatusRegisterAddress = 0x00000000,
84 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
85 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
86 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
87 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
88 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
89 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
90 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
91 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
92 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
93 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
94 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
95 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
96 .maxDataPerBlock = 16256,
97 },
98 },
99 [DMA_DEVICE_PIF_DEV_TO_MEM] = /* PIF RX */
100 {
101 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
102 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
103 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
104 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
105 .name = "pif_rx",
106 .dmacPort = {14, 5},
107 .config = {
108 /* srcPeripheralPort = 5 or 14 */
109 .dstPeripheralPort = 0, /* DST: memory */
110 .srcStatusRegisterAddress = 0x00000000,
111 .dstStatusRegisterAddress = 0x00000000,
112 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
113 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
114 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
115 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
116 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
117 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
118 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
119 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
120 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
121 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
122 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
123 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
124 .maxDataPerBlock = 16256,
125 },
126 },
127 [DMA_DEVICE_I2S0_DEV_TO_MEM] = /* I2S RX */
128 {
129 .flags = DMA_DEVICE_FLAG_ON_DMA0,
130 .name = "i2s0_rx",
131 .config = {
132 .srcPeripheralPort = 0, /* SRC: I2S0 */
133 .dstPeripheralPort = 0, /* DST: memory */
134 .srcStatusRegisterAddress = 0,
135 .dstStatusRegisterAddress = 0,
136 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
137 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
138 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
139 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
140 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
141 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
142 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
143 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
144 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
145 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
146 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
147 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
148 },
149 },
150 [DMA_DEVICE_I2S0_MEM_TO_DEV] = /* I2S TX */
151 {
152 .flags = DMA_DEVICE_FLAG_ON_DMA0,
153 .name = "i2s0_tx",
154 .config = {
155 .srcPeripheralPort = 0, /* SRC: memory */
156 .dstPeripheralPort = 1, /* DST: I2S0 */
157 .srcStatusRegisterAddress = 0,
158 .dstStatusRegisterAddress = 0,
159 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
160 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
161 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
162 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
163 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
164 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
165 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
166 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
167 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
168 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
169 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
170 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
171 },
172 },
173 [DMA_DEVICE_I2S1_DEV_TO_MEM] = /* I2S1 RX */
174 {
175 .flags = DMA_DEVICE_FLAG_ON_DMA1,
176 .name = "i2s1_rx",
177 .config = {
178 .srcPeripheralPort = 2, /* SRC: I2S1 */
179 .dstPeripheralPort = 0, /* DST: memory */
180 .srcStatusRegisterAddress = 0,
181 .dstStatusRegisterAddress = 0,
182 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
183 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
184 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
185 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
186 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
187 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
188 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
189 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
190 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
191 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
192 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
193 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
194 },
195 },
196 [DMA_DEVICE_I2S1_MEM_TO_DEV] = /* I2S1 TX */
197 {
198 .flags = DMA_DEVICE_FLAG_ON_DMA1,
199 .name = "i2s1_tx",
200 .config = {
201 .srcPeripheralPort = 0, /* SRC: memory */
202 .dstPeripheralPort = 3, /* DST: I2S1 */
203 .srcStatusRegisterAddress = 0,
204 .dstStatusRegisterAddress = 0,
205 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
206 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
207 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
208 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
209 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
210 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
211 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
212 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
213 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
214 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
215 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
216 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
217 },
218 },
219 [DMA_DEVICE_ESW_MEM_TO_DEV] = /* ESW TX */
220 {
221 .name = "esw_tx",
222 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
223 .dedicatedController = 1,
224 .dedicatedChannel = 3,
225 .config = {
226 .srcPeripheralPort = 0, /* SRC: memory */
227 .dstPeripheralPort = 1, /* DST: ESW (MTP) */
228 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
229 .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
230 /* DMAx_AHB_SSTATARy */
231 .srcStatusRegisterAddress = 0x00000000,
232 /* DMAx_AHB_DSTATARy */
233 .dstStatusRegisterAddress = 0x30490010,
234 /* DMAx_AHB_CFGy */
235 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
236 /* DMAx_AHB_CTLy */
237 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
238 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
239 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
240 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
241 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
242 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
243 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
244 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
245 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
246 },
247 },
248 [DMA_DEVICE_ESW_DEV_TO_MEM] = /* ESW RX */
249 {
250 .name = "esw_rx",
251 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
252 .dedicatedController = 1,
253 .dedicatedChannel = 2,
254 .config = {
255 .srcPeripheralPort = 0, /* SRC: ESW (PTM) */
256 .dstPeripheralPort = 0, /* DST: memory */
257 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
258 .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
259 /* DMAx_AHB_SSTATARy */
260 .srcStatusRegisterAddress = 0x30480010,
261 /* DMAx_AHB_DSTATARy */
262 .dstStatusRegisterAddress = 0x00000000,
263 /* DMAx_AHB_CFGy */
264 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
265 /* DMAx_AHB_CTLy */
266 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
267 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
268 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
269 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
270 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
271 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
272 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
273 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
274 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
275 },
276 },
277 [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] = /* APM Codec A Ingress */
278 {
279 .flags = DMA_DEVICE_FLAG_ON_DMA0,
280 .name = "apm_a_rx",
281 .config = {
282 .srcPeripheralPort = 2, /* SRC: Codec A Ingress FIFO */
283 .dstPeripheralPort = 0, /* DST: memory */
284 .srcStatusRegisterAddress = 0x00000000,
285 .dstStatusRegisterAddress = 0x00000000,
286 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
287 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
288 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
289 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
290 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
291 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
292 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
293 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
294 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
295 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
296 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
297 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
298 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
299 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
300 },
301 },
302 [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] = /* APM Codec A Egress */
303 {
304 .flags = DMA_DEVICE_FLAG_ON_DMA0,
305 .name = "apm_a_tx",
306 .config = {
307 .srcPeripheralPort = 0, /* SRC: memory */
308 .dstPeripheralPort = 3, /* DST: Codec A Egress FIFO */
309 .srcStatusRegisterAddress = 0x00000000,
310 .dstStatusRegisterAddress = 0x00000000,
311 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
312 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
313 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
314 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
315 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
316 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
317 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
318 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
319 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
320 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
321 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
322 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
323 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
324 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
325 },
326 },
327 [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] = /* APM Codec B Ingress */
328 {
329 .flags = DMA_DEVICE_FLAG_ON_DMA0,
330 .name = "apm_b_rx",
331 .config = {
332 .srcPeripheralPort = 4, /* SRC: Codec B Ingress FIFO */
333 .dstPeripheralPort = 0, /* DST: memory */
334 .srcStatusRegisterAddress = 0x00000000,
335 .dstStatusRegisterAddress = 0x00000000,
336 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
337 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
338 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
339 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
340 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
341 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
342 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
343 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
344 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
345 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
346 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
347 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
348 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
349 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
350 },
351 },
352 [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] = /* APM Codec B Egress */
353 {
354 .flags = DMA_DEVICE_FLAG_ON_DMA0,
355 .name = "apm_b_tx",
356 .config = {
357 .srcPeripheralPort = 0, /* SRC: memory */
358 .dstPeripheralPort = 5, /* DST: Codec B Egress FIFO */
359 .srcStatusRegisterAddress = 0x00000000,
360 .dstStatusRegisterAddress = 0x00000000,
361 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
362 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
363 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
364 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
365 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
366 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
367 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
368 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
369 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
370 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
371 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
372 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
373 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
374 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
375 },
376 },
377 [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] = /* APM Codec C Ingress */
378 {
379 .flags = DMA_DEVICE_FLAG_ON_DMA1,
380 .name = "apm_c_rx",
381 .config = {
382 .srcPeripheralPort = 4, /* SRC: Codec C Ingress FIFO */
383 .dstPeripheralPort = 0, /* DST: memory */
384 .srcStatusRegisterAddress = 0x00000000,
385 .dstStatusRegisterAddress = 0x00000000,
386 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
387 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
388 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
389 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
390 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
391 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
392 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
393 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
394 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
395 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
396 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
397 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
398 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
399 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
400 },
401 },
402 [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] = /* PCM0 RX */
403 {
404 .flags = DMA_DEVICE_FLAG_ON_DMA0,
405 .name = "pcm0_rx",
406 .config = {
407 .srcPeripheralPort = 12, /* SRC: PCM0 */
408 .dstPeripheralPort = 0, /* DST: memory */
409 .srcStatusRegisterAddress = 0,
410 .dstStatusRegisterAddress = 0,
411 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
412 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
413 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
414 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
415 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
416 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
417 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
418 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
419 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
420 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
421 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
422 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
423 },
424 },
425 [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] = /* PCM0 TX */
426 {
427 .flags = DMA_DEVICE_FLAG_ON_DMA0,
428 .name = "pcm0_tx",
429 .config = {
430 .srcPeripheralPort = 0, /* SRC: memory */
431 .dstPeripheralPort = 13, /* DST: PCM0 */
432 .srcStatusRegisterAddress = 0,
433 .dstStatusRegisterAddress = 0,
434 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
435 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
436 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
437 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
438 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
439 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
440 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
441 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
442 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
443 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
444 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
445 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
446 },
447 },
448 [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] = /* PCM1 RX */
449 {
450 .flags = DMA_DEVICE_FLAG_ON_DMA1,
451 .name = "pcm1_rx",
452 .config = {
453 .srcPeripheralPort = 14, /* SRC: PCM1 */
454 .dstPeripheralPort = 0, /* DST: memory */
455 .srcStatusRegisterAddress = 0,
456 .dstStatusRegisterAddress = 0,
457 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
458 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
459 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
460 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
461 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
462 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
463 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
464 .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
465 .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
466 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
467 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
468 .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
469 },
470 },
471 [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] = /* PCM1 TX */
472 {
473 .flags = DMA_DEVICE_FLAG_ON_DMA1,
474 .name = "pcm1_tx",
475 .config = {
476 .srcPeripheralPort = 0, /* SRC: memory */
477 .dstPeripheralPort = 15, /* DST: PCM1 */
478 .srcStatusRegisterAddress = 0,
479 .dstStatusRegisterAddress = 0,
480 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
481 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
482 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
483 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
484 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
485 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
486 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
487 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
488 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
489 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
490 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
491 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
492 },
493 },
494 [DMA_DEVICE_SPUM_DEV_TO_MEM] = /* SPUM RX */
495 {
496 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
497 .name = "spum_rx",
498 .config = {
499 .srcPeripheralPort = 6, /* SRC: Codec A Ingress FIFO */
500 .dstPeripheralPort = 0, /* DST: memory */
501 .srcStatusRegisterAddress = 0x00000000,
502 .dstStatusRegisterAddress = 0x00000000,
503 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
504 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
505 .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
506 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
507 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
508 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
509 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
510 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
511 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
512 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
513 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
514 /* Busrt size **MUST** be 16 for SPUM to work */
515 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
516 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
517 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
518 /* on the RX side, SPU needs to be the flow controller */
519 .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
520 },
521 },
522 [DMA_DEVICE_SPUM_MEM_TO_DEV] = /* SPUM TX */
523 {
524 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
525 .name = "spum_tx",
526 .config = {
527 .srcPeripheralPort = 0, /* SRC: memory */
528 .dstPeripheralPort = 7, /* DST: SPUM */
529 .srcStatusRegisterAddress = 0x00000000,
530 .dstStatusRegisterAddress = 0x00000000,
531 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
532 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
533 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
534 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
535 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
536 .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
537 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
538 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
539 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
540 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
541 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
542 /* Busrt size **MUST** be 16 for SPUM to work */
543 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
544 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
545 .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
546 },
547 },
548 [DMA_DEVICE_MEM_TO_VRAM] = /* MEM 2 VRAM */
549 {
550 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
551 .name = "mem-to-vram",
552 .config = {
553 .srcPeripheralPort = 0, /* SRC: memory */
554 .srcStatusRegisterAddress = 0x00000000,
555 .dstStatusRegisterAddress = 0x00000000,
556 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
557 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
558 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
559 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
560 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
561 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
562 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
563 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
564 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
565 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
566 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
567 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
568 },
569 },
570 [DMA_DEVICE_VRAM_TO_MEM] = /* VRAM 2 MEM */
571 {
572 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
573 .name = "vram-to-mem",
574 .config = {
575 .dstPeripheralPort = 0, /* DST: memory */
576 .srcStatusRegisterAddress = 0x00000000,
577 .dstStatusRegisterAddress = 0x00000000,
578 .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
579 .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
580 .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
581 .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
582 .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
583 .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
584 .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
585 .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
586 .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
587 .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
588 .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
589 .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
590 },
591 },
592};
593EXPORT_SYMBOL(DMA_gDeviceAttribute); /* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
new file mode 100644
index 00000000000..f01da877148
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/cfg_global.h
@@ -0,0 +1,13 @@
1#ifndef _CFG_GLOBAL_H_
2#define _CFG_GLOBAL_H_
3
4#include <cfg_global_defines.h>
5
6#define CFG_GLOBAL_CHIP BCM11107
7#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
8#define CFG_GLOBAL_CHIP_REV 0xB0
9#define CFG_GLOBAL_RAM_SIZE 0x10000000
10#define CFG_GLOBAL_RAM_BASE 0x00000000
11#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
12
13#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h
new file mode 100644
index 00000000000..b5beb0b3073
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/cfg_global_defines.h
@@ -0,0 +1,40 @@
1/*****************************************************************************
2* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CFG_GLOBAL_DEFINES_H
16#define CFG_GLOBAL_DEFINES_H
17
18/* CHIP */
19#define BCM1103 1
20
21#define BCM1191 4
22#define BCM2153 5
23#define BCM2820 6
24
25#define BCM2826 8
26#define FPGA11107 9
27#define BCM11107 10
28#define BCM11109 11
29#define BCM11170 12
30#define BCM11110 13
31#define BCM11211 14
32
33/* CFG_GLOBAL_CHIP_FAMILY types */
34#define CFG_GLOBAL_CHIP_FAMILY_NONE 0
35#define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2
36#define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4
37#define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8
38
39#define IMAGE_HEADER_SIZE_CHECKSUM 4
40#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
new file mode 100644
index 00000000000..caa20e59db9
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/cache.h
@@ -0,0 +1,35 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CSP_CACHE_H
16#define CSP_CACHE_H
17
18/* ---- Include Files ---------------------------------------------------- */
19
20#include <csp/stdint.h>
21
22/* ---- Public Constants and Types --------------------------------------- */
23
24#if defined(__KERNEL__) && !defined(STANDALONE)
25#include <asm/cacheflush.h>
26
27#define CSP_CACHE_FLUSH_ALL flush_cache_all()
28
29#else
30
31#define CSP_CACHE_FLUSH_ALL
32
33#endif
34
35#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
new file mode 100644
index 00000000000..8b3d8036729
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/delay.h
@@ -0,0 +1,36 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_DELAY_H
17#define CSP_DELAY_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21/* Some CSP routines require use of the following delay routines. Use the OS */
22/* version if available, otherwise use a CSP specific definition. */
23/* void udelay(unsigned long usecs); */
24/* void mdelay(unsigned long msecs); */
25
26#if defined(__KERNEL__) && !defined(STANDALONE)
27 #include <linux/delay.h>
28#else
29 #include <mach/csp/delay.h>
30#endif
31
32/* ---- Public Constants and Types --------------------------------------- */
33/* ---- Public Variable Externs ------------------------------------------ */
34/* ---- Public Function Prototypes --------------------------------------- */
35
36#endif /* CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
new file mode 100644
index 00000000000..e6a1dc484ca
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -0,0 +1,596 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw.h
18*
19* @brief API definitions for low level DMA controller driver
20*
21*/
22/****************************************************************************/
23#ifndef _DMACHW_H
24#define _DMACHW_H
25
26#include <stddef.h>
27
28#include <csp/stdint.h>
29#include <mach/csp/dmacHw_reg.h>
30
31/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
32
33 System specific channel ID should be defined as follows
34
35 For example:
36
37 #include <dmacHw.h>
38 ...
39 #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5)
40 #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0)
41 #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1)
42 #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3)
43 #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4)
44 ...
45 #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4)
46 #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5)
47 #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6)
48 ...
49*/
50#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c)
51
52typedef enum {
53 dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */
54 dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */
55 dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */
56 dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */
57 dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */
58 dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */
59 dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */
60 dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */
61} dmacHw_CHANNEL_PRIORITY_e;
62
63/* Source destination master interface */
64typedef enum {
65 dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */
66 dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */
67 dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */
68 dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */
69} dmacHw_MASTER_INTERFACE_e;
70
71typedef enum {
72 dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */
73 dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */
74 dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */
75 dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */
76 dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */
77 dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */
78 dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */
79 dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */
80} dmacHw_TRANSACTION_WIDTH_e;
81
82typedef enum {
83 dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */
84 dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
85 dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
86 dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
87 dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */
88 dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
89 dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
90 dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
91} dmacHw_BURST_WIDTH_e;
92
93typedef enum {
94 dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */
95 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */
96 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */
97 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */
98} dmacHw_TRANSFER_TYPE_e;
99
100typedef enum {
101 dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */
102 dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */
103 dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */
104} dmacHw_TRANSFER_MODE_e;
105
106typedef enum {
107 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */
108 dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */
109 dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */
110 dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */
111 dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */
112 dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */
113} dmacHw_ADDRESS_UPDATE_MODE_e;
114
115typedef enum {
116 dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */
117 dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */
118} dmacHw_FLOW_CONTROL_e;
119
120typedef enum {
121 dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */
122 dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */
123 dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */
124} dmacHw_TRANSFER_STATUS_e;
125
126typedef enum {
127 dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */
128 dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
129} dmacHw_INTERRUPT_e;
130
131typedef enum {
132 dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */
133 dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */
134 dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */
135 dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */
136} dmacHw_INTERRUPT_STATUS_e;
137
138typedef enum {
139 dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */
140 dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */
141 dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */
142 dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */
143 dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */
144} dmacHw_CONTROLLER_ATTRIB_e;
145
146typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */
147typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using
148 "dmacHw_MAKE_CHANNEL_ID" macro
149 */
150/* DMA channel configuration parameters */
151typedef struct {
152 uint32_t srcPeripheralPort; /* Source peripheral port */
153 uint32_t dstPeripheralPort; /* Destination peripheral port */
154 uint32_t srcStatusRegisterAddress; /* Source status register address */
155 uint32_t dstStatusRegisterAddress; /* Destination status register address of type */
156
157 uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */
158 uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
159 uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */
160 uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */
161 uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor.
162 0 = Maximum possible.
163 */
164
165 dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
166 dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
167 dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */
168 dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */
169 dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */
170 dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */
171 dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */
172 dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */
173 dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */
174 dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */
175 dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */
176 dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */
177 dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */
178 dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */
179 dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */
180} dmacHw_CONFIG_t;
181
182/****************************************************************************/
183/**
184* @brief Initializes DMA
185*
186* This function initializes DMA CSP driver
187*
188* @note
189* Must be called before using any DMA channel
190*/
191/****************************************************************************/
192void dmacHw_initDma(void);
193
194/****************************************************************************/
195/**
196* @brief Exit function for DMA
197*
198* This function isolates DMA from the system
199*
200*/
201/****************************************************************************/
202void dmacHw_exitDma(void);
203
204/****************************************************************************/
205/**
206* @brief Gets a handle to a DMA channel
207*
208* This function returns a handle, representing a control block of a particular DMA channel
209*
210* @return -1 - On Failure
211* handle - On Success, representing a channel control block
212*
213* @note
214* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
215*/
216/****************************************************************************/
217dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
218 );
219
220/****************************************************************************/
221/**
222* @brief Initializes a DMA channel for use
223*
224* This function initializes and resets a DMA channel for use
225*
226* @return -1 - On Failure
227* 0 - On Success
228*
229* @note
230* None
231*/
232/****************************************************************************/
233int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
234 );
235
236/****************************************************************************/
237/**
238* @brief Estimates number of descriptor needed to perform certain DMA transfer
239*
240*
241* @return On failure : -1
242* On success : Number of descriptor count
243*
244*
245*/
246/****************************************************************************/
247int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
248 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
249 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
250 size_t dataLen /* [ IN ] Data length in bytes */
251 );
252
253/****************************************************************************/
254/**
255* @brief Initializes descriptor ring
256*
257* This function will initializes the descriptor ring of a DMA channel
258*
259*
260* @return -1 - On failure
261* 0 - On success
262* @note
263* - "len" parameter should be obtained from "dmacHw_descriptorLen"
264* - Descriptor buffer MUST be 32 bit aligned and uncached as it
265* is accessed by ARM and DMA
266*/
267/****************************************************************************/
268int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
269 uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
270 uint32_t len, /* [ IN ] Size of the pBuf */
271 uint32_t num /* [ IN ] Number of descriptor in the ring */
272 );
273
274/****************************************************************************/
275/**
276* @brief Finds amount of memory required to form a descriptor ring
277*
278*
279* @return Number of bytes required to form a descriptor ring
280*
281*
282* @note
283* None
284*/
285/****************************************************************************/
286uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
287 );
288
289/****************************************************************************/
290/**
291* @brief Configure DMA channel
292*
293* @return 0 : On success
294* -1 : On failure
295*/
296/****************************************************************************/
297int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
298 dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
299 );
300
301/****************************************************************************/
302/**
303* @brief Set descriptors for known data length
304*
305* When DMA has to work as a flow controller, this function prepares the
306* descriptor chain to transfer data
307*
308* from:
309* - Memory to memory
310* - Peripheral to memory
311* - Memory to Peripheral
312* - Peripheral to Peripheral
313*
314* @return -1 - On failure
315* 0 - On success
316*
317*/
318/****************************************************************************/
319int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
320 void *pDescriptor, /* [ IN ] Descriptor buffer */
321 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
322 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
323 size_t dataLen /* [ IN ] Length in bytes */
324 );
325
326/****************************************************************************/
327/**
328* @brief Indicates whether DMA transfer is in progress or completed
329*
330* @return DMA transfer status
331* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
332* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
333* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
334*
335*/
336/****************************************************************************/
337dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
338 );
339
340/****************************************************************************/
341/**
342* @brief Set descriptor carrying control information
343*
344* This function will be used to send specific control information to the device
345* using the DMA channel
346*
347*
348* @return -1 - On failure
349* 0 - On success
350*
351* @note
352* None
353*/
354/****************************************************************************/
355int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
356 void *pDescriptor, /* [ IN ] Descriptor buffer */
357 uint32_t ctlAddress, /* [ IN ] Address of the device control register */
358 uint32_t control /* [ IN ] Device control information */
359 );
360
361/****************************************************************************/
362/**
363* @brief Read data DMA transferred to memory
364*
365* This function will read data that has been DMAed to memory while transferring from:
366* - Memory to memory
367* - Peripheral to memory
368*
369* @return 0 - No more data is available to read
370* 1 - More data might be available to read
371*
372*/
373/****************************************************************************/
374int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
375 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
376 void *pDescriptor, /* [ IN ] Descriptor buffer */
377 void **ppBbuf, /* [ OUT ] Data received */
378 size_t *pLlen /* [ OUT ] Length of the data received */
379 );
380
381/****************************************************************************/
382/**
383* @brief Prepares descriptor ring, when source peripheral working as a flow controller
384*
385* This function will form the descriptor ring by allocating buffers, when source peripheral
386* has to work as a flow controller to transfer data from:
387* - Peripheral to memory.
388*
389* @return -1 - On failure
390* 0 - On success
391*
392*
393* @note
394* None
395*/
396/****************************************************************************/
397int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
398 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
399 void *pDescriptor, /* [ IN ] Descriptor buffer */
400 uint32_t srcAddr, /* [ IN ] Source peripheral address */
401 void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
402 int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
403 int num /* [ IN ] Number of descriptor to set */
404 );
405
406/****************************************************************************/
407/**
408* @brief Program channel register to initiate transfer
409*
410* @return void
411*
412*
413* @note
414* - Descriptor buffer MUST ALWAYS be flushed before calling this function
415* - This function should also be called from ISR to program the channel with
416* pending descriptors
417*/
418/****************************************************************************/
419void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
420 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
421 void *pDescriptor /* [ IN ] Descriptor buffer */
422 );
423
424/****************************************************************************/
425/**
426* @brief Resets descriptor control information
427*
428* @return void
429*/
430/****************************************************************************/
431void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
432 );
433
434/****************************************************************************/
435/**
436* @brief Program channel register to stop transfer
437*
438* Ensures the channel is not doing any transfer after calling this function
439*
440* @return void
441*
442*/
443/****************************************************************************/
444void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
445 );
446
447/****************************************************************************/
448/**
449* @brief Check the existence of pending descriptor
450*
451* This function confirmes if there is any pending descriptor in the chain
452* to program the channel
453*
454* @return 1 : Channel need to be programmed with pending descriptor
455* 0 : No more pending descriptor to programe the channel
456*
457* @note
458* - This function should be called from ISR in case there are pending
459* descriptor to program the channel.
460*
461* Example:
462*
463* dmac_isr ()
464* {
465* ...
466* if (dmacHw_descriptorPending (handle))
467* {
468* dmacHw_initiateTransfer (handle);
469* }
470* }
471*
472*/
473/****************************************************************************/
474uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
475 void *pDescriptor /* [ IN ] Descriptor buffer */
476 );
477
478/****************************************************************************/
479/**
480* @brief Deallocates source or destination memory, allocated
481*
482* This function can be called to deallocate data memory that was DMAed successfully
483*
484* @return -1 - On failure
485* 0 - On success
486*
487* @note
488* This function will be called ONLY, when source OR destination address is pointing
489* to dynamic memory
490*/
491/****************************************************************************/
492int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
493 void *pDescriptor, /* [ IN ] Descriptor buffer */
494 void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
495 );
496
497/****************************************************************************/
498/**
499* @brief Clears the interrupt
500*
501* This function clears the DMA channel specific interrupt
502*
503* @return N/A
504*
505* @note
506* Must be called under the context of ISR
507*/
508/****************************************************************************/
509void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
510 );
511
512/****************************************************************************/
513/**
514* @brief Returns the cause of channel specific DMA interrupt
515*
516* This function returns the cause of interrupt
517*
518* @return Interrupt status, each bit representing a specific type of interrupt
519* of type dmacHw_INTERRUPT_STATUS_e
520* @note
521* This function should be called under the context of ISR
522*/
523/****************************************************************************/
524dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
525 );
526
527/****************************************************************************/
528/**
529* @brief Indentifies a DMA channel causing interrupt
530*
531* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
532*
533* @return NULL : No channel causing DMA interrupt
534* ! NULL : Handle to a channel causing DMA interrupt
535* @note
536* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
537*/
538/****************************************************************************/
539dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
540
541/****************************************************************************/
542/**
543* @brief Sets channel specific user data
544*
545* This function associates user data to a specific DMA channel
546*
547*/
548/****************************************************************************/
549void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
550 void *userData /* [ IN ] User data */
551 );
552
553/****************************************************************************/
554/**
555* @brief Gets channel specific user data
556*
557* This function returns user data specific to a DMA channel
558*
559* @return user data
560*/
561/****************************************************************************/
562void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
563 );
564
565/****************************************************************************/
566/**
567* @brief Displays channel specific registers and other control parameters
568*
569*
570* @return void
571*
572* @note
573* None
574*/
575/****************************************************************************/
576void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
577 void *pDescriptor, /* [ IN ] Descriptor buffer */
578 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
579 );
580
581/****************************************************************************/
582/**
583* @brief Provides DMA controller attributes
584*
585*
586* @return DMA controller attributes
587*
588* @note
589* None
590*/
591/****************************************************************************/
592uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
593 dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
594 );
595
596#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
new file mode 100644
index 00000000000..51357dd5b66
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/errno.h
@@ -0,0 +1,32 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CSP_ERRNO_H
16#define CSP_ERRNO_H
17
18/* ---- Include Files ---------------------------------------------------- */
19
20#if defined(__KERNEL__)
21#include <linux/errno.h>
22#elif defined(CSP_SIMULATION)
23#include <asm-generic/errno.h>
24#else
25#include <errno.h>
26#endif
27
28/* ---- Public Constants and Types --------------------------------------- */
29/* ---- Public Variable Externs ------------------------------------------ */
30/* ---- Public Function Prototypes --------------------------------------- */
31
32#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
new file mode 100644
index 00000000000..1c639c8ee08
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -0,0 +1,40 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16/****************************************************************************/
17/**
18* @file intcHw.h
19*
20* @brief generic interrupt controller API
21*
22* @note
23* None
24*/
25/****************************************************************************/
26
27#ifndef _INTCHW_H
28#define _INTCHW_H
29
30/* ---- Include Files ---------------------------------------------------- */
31#include <mach/csp/intcHw_reg.h>
32
33/* ---- Public Constants and Types --------------------------------------- */
34/* ---- Public Variable Externs ------------------------------------------ */
35/* ---- Public Function Prototypes --------------------------------------- */
36static inline void intcHw_irq_disable(void *basep, uint32_t mask);
37static inline void intcHw_irq_enable(void *basep, uint32_t mask);
38
39#endif /* _INTCHW_H */
40
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
new file mode 100644
index 00000000000..c30d2a5975a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/module.h
@@ -0,0 +1,32 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_MODULE_H
17#define CSP_MODULE_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21#ifdef __KERNEL__
22 #include <linux/module.h>
23#else
24 #define EXPORT_SYMBOL(symbol)
25#endif
26
27/* ---- Public Constants and Types --------------------------------------- */
28/* ---- Public Variable Externs ------------------------------------------ */
29/* ---- Public Function Prototypes --------------------------------------- */
30
31
32#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
new file mode 100644
index 00000000000..56654d23c3d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -0,0 +1,114 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file reg.h
18*
19* @brief Generic register definitions used in CSP
20*/
21/****************************************************************************/
22
23#ifndef CSP_REG_H
24#define CSP_REG_H
25
26/* ---- Include Files ---------------------------------------------------- */
27
28#include <csp/stdint.h>
29
30/* ---- Public Constants and Types --------------------------------------- */
31
32#define __REG32(x) (*((volatile uint32_t *)(x)))
33#define __REG16(x) (*((volatile uint16_t *)(x)))
34#define __REG8(x) (*((volatile uint8_t *) (x)))
35
36/* Macros used to define a sequence of reserved registers. The start / end */
37/* are byte offsets in the particular register definition, with the "end" */
38/* being the offset of the next un-reserved register. E.g. if offsets */
39/* 0x10 through to 0x1f are reserved, then this reserved area could be */
40/* specified as follows. */
41/* typedef struct */
42/* { */
43/* uint32_t reg1; offset 0x00 */
44/* uint32_t reg2; offset 0x04 */
45/* uint32_t reg3; offset 0x08 */
46/* uint32_t reg4; offset 0x0c */
47/* REG32_RSVD(0x10, 0x20); */
48/* uint32_t reg5; offset 0x20 */
49/* ... */
50/* } EXAMPLE_REG_t; */
51#define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
52#define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
53#define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
54
55/* ---- Public Variable Externs ------------------------------------------ */
56/* ---- Public Function Prototypes --------------------------------------- */
57
58/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
59/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */
60/* flags variable to be declared locally. */
61/* e.g. */
62/* statement1; */
63/* { */
64/* REG_LOCAL_IRQ_SAVE; */
65/* <multiple statements here> */
66/* REG_LOCAL_IRQ_RESTORE; */
67/* } */
68/* statement2; */
69/* */
70
71#if defined(__KERNEL__) && !defined(STANDALONE)
72#include <mach/hardware.h>
73#include <linux/interrupt.h>
74
75#define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \
76 unsigned long flags; HW_IRQ_SAVE(reg32, flags)
77
78#define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags)
79
80#else
81
82#define REG_LOCAL_IRQ_SAVE
83#define REG_LOCAL_IRQ_RESTORE
84
85#endif
86
87static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
88{
89 REG_LOCAL_IRQ_SAVE;
90 *reg &= value;
91 REG_LOCAL_IRQ_RESTORE;
92}
93
94static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
95{
96 REG_LOCAL_IRQ_SAVE;
97 *reg |= value;
98 REG_LOCAL_IRQ_RESTORE;
99}
100
101static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
102 uint32_t value)
103{
104 REG_LOCAL_IRQ_SAVE;
105 *reg = (*reg & mask) | value;
106 REG_LOCAL_IRQ_RESTORE;
107}
108
109static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
110{
111 *reg = value;
112}
113
114#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
new file mode 100644
index 00000000000..b9d7e0732df
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/secHw.h
@@ -0,0 +1,65 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw.h
18*
19* @brief Definitions for accessing low level security features
20*
21*/
22/****************************************************************************/
23#ifndef SECHW_H
24#define SECHW_H
25
26typedef void (*secHw_FUNC_t) (void);
27
28typedef enum {
29 secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */
30 secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */
31} secHw_MODE;
32
33/****************************************************************************/
34/**
35* @brief Requesting to execute the function in secure mode
36*
37* This function requests the given function to run in secure mode
38*
39*/
40/****************************************************************************/
41void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */
42 );
43
44/****************************************************************************/
45/**
46* @brief Sets the mode
47*
48* his function sets the processor mode (secure/non-secure)
49*
50*/
51/****************************************************************************/
52void secHw_SetMode(secHw_MODE /* Processor mode */
53 );
54
55/****************************************************************************/
56/**
57* @brief Get the current mode
58*
59* This function retieves the processor mode (secure/non-secure)
60*
61*/
62/****************************************************************************/
63void secHw_GetMode(secHw_MODE *);
64
65#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
new file mode 100644
index 00000000000..3a8718bbf70
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/stdint.h
@@ -0,0 +1,30 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CSP_STDINT_H
16#define CSP_STDINT_H
17
18/* ---- Include Files ---------------------------------------------------- */
19
20#ifdef __KERNEL__
21#include <linux/types.h>
22#else
23#include <stdint.h>
24#endif
25
26/* ---- Public Constants and Types --------------------------------------- */
27/* ---- Public Variable Externs ------------------------------------------ */
28/* ---- Public Function Prototypes --------------------------------------- */
29
30#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
new file mode 100644
index 00000000000..ad9e4005f14
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/string.h
@@ -0,0 +1,34 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16
17#ifndef CSP_STRING_H
18#define CSP_STRING_H
19
20/* ---- Include Files ---------------------------------------------------- */
21
22#ifdef __KERNEL__
23 #include <linux/string.h>
24#else
25 #include <string.h>
26#endif
27
28/* ---- Public Constants and Types --------------------------------------- */
29/* ---- Public Variable Externs ------------------------------------------ */
30/* ---- Public Function Prototypes --------------------------------------- */
31
32
33#endif /* CSP_STRING_H */
34
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h
new file mode 100644
index 00000000000..2cbb530db8e
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/tmrHw.h
@@ -0,0 +1,263 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw.h
18*
19* @brief API definitions for low level Timer driver
20*
21*/
22/****************************************************************************/
23#ifndef _TMRHW_H
24#define _TMRHW_H
25
26#include <csp/stdint.h>
27
28typedef uint32_t tmrHw_ID_t; /* Timer ID */
29typedef uint32_t tmrHw_COUNT_t; /* Timer count */
30typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */
31typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */
32
33typedef enum {
34 tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */
35 tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */
36} tmrHw_INTERRUPT_STATUS_e;
37
38typedef enum {
39 tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
40 tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */
41} tmrHw_CAPABILITY_e;
42
43/****************************************************************************/
44/**
45* @brief Get timer capability
46*
47* This function returns various capabilities/attributes of a timer
48*
49* @return Numeric capability
50*
51*/
52/****************************************************************************/
53uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
54 tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */
55);
56
57/****************************************************************************/
58/**
59* @brief Configures a periodic timer in terms of timer interrupt rate
60*
61* This function initializes a periodic timer to generate specific number of
62* timer interrupt per second
63*
64* @return On success: Effective timer frequency
65* On failure: 0
66*
67*/
68/****************************************************************************/
69tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
70 tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */
71);
72
73/****************************************************************************/
74/**
75* @brief Configures a periodic timer to generate timer interrupt after
76* certain time interval
77*
78* This function initializes a periodic timer to generate timer interrupt
79* after every time interval in millisecond
80*
81* @return On success: Effective interval set in mili-second
82* On failure: 0
83*
84*/
85/****************************************************************************/
86tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
87 tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */
88);
89
90/****************************************************************************/
91/**
92* @brief Configures a periodic timer to generate timer interrupt just once
93* after certain time interval
94*
95* This function initializes a periodic timer to generate a single ticks after
96* certain time interval in millisecond
97*
98* @return On success: Effective interval set in mili-second
99* On failure: 0
100*
101*/
102/****************************************************************************/
103tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
104 tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */
105);
106
107/****************************************************************************/
108/**
109* @brief Configures a timer to run as a free running timer
110*
111* This function initializes a timer to run as a free running timer
112*
113* @return Timer resolution (count / sec)
114*
115*/
116/****************************************************************************/
117tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */
118 uint32_t divider /* [ IN ] Dividing the clock frequency */
119) __attribute__ ((section(".aramtext")));
120
121/****************************************************************************/
122/**
123* @brief Starts a timer
124*
125* This function starts a preconfigured timer
126*
127* @return -1 - On Failure
128* 0 - On Success
129*/
130/****************************************************************************/
131int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
132) __attribute__ ((section(".aramtext")));
133
134/****************************************************************************/
135/**
136* @brief Stops a timer
137*
138* This function stops a running timer
139*
140* @return -1 - On Failure
141* 0 - On Success
142*/
143/****************************************************************************/
144int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */
145);
146
147/****************************************************************************/
148/**
149* @brief Gets current timer count
150*
151* This function returns the current timer value
152*
153* @return Current downcounting timer value
154*
155*/
156/****************************************************************************/
157tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */
158) __attribute__ ((section(".aramtext")));
159
160/****************************************************************************/
161/**
162* @brief Gets timer count rate
163*
164* This function returns the number of counts per second
165*
166* @return Count rate
167*
168*/
169/****************************************************************************/
170tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */
171) __attribute__ ((section(".aramtext")));
172
173/****************************************************************************/
174/**
175* @brief Enables timer interrupt
176*
177* This function enables the timer interrupt
178*
179* @return N/A
180*
181*/
182/****************************************************************************/
183void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
184);
185
186/****************************************************************************/
187/**
188* @brief Disables timer interrupt
189*
190* This function disable the timer interrupt
191*
192* @return N/A
193*/
194/****************************************************************************/
195void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
196);
197
198/****************************************************************************/
199/**
200* @brief Clears the interrupt
201*
202* This function clears the timer interrupt
203*
204* @return N/A
205*
206* @note
207* Must be called under the context of ISR
208*/
209/****************************************************************************/
210void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */
211);
212
213/****************************************************************************/
214/**
215* @brief Gets the interrupt status
216*
217* This function returns timer interrupt status
218*
219* @return Interrupt status
220*/
221/****************************************************************************/
222tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */
223);
224
225/****************************************************************************/
226/**
227* @brief Indentifies a timer causing interrupt
228*
229* This functions returns a timer causing interrupt
230*
231* @return 0xFFFFFFFF : No timer causing an interrupt
232* ! 0xFFFFFFFF : timer causing an interrupt
233* @note
234* tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
235*/
236/****************************************************************************/
237tmrHw_ID_t tmrHw_getInterruptSource(void);
238
239/****************************************************************************/
240/**
241* @brief Displays specific timer registers
242*
243*
244* @return void
245*
246*/
247/****************************************************************************/
248void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */
249 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
250);
251
252/****************************************************************************/
253/**
254* @brief Use a timer to perform a busy wait delay for a number of usecs.
255*
256* @return N/A
257*/
258/****************************************************************************/
259void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */
260 unsigned long usecs /* [ IN ] usec to delay */
261) __attribute__ ((section(".aramtext")));
262
263#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
new file mode 100644
index 00000000000..30fa2d54063
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap.h
@@ -0,0 +1,63 @@
1/*****************************************************************************
2* Copyright 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CAP_H
16#define CAP_H
17
18/* ---- Include Files ---------------------------------------------------- */
19/* ---- Public Constants and Types --------------------------------------- */
20typedef enum {
21 CAP_NOT_PRESENT = 0,
22 CAP_PRESENT
23} CAP_RC_T;
24
25typedef enum {
26 CAP_VPM,
27 CAP_ETH_PHY,
28 CAP_ETH_GMII,
29 CAP_ETH_SGMII,
30 CAP_USB,
31 CAP_TSC,
32 CAP_EHSS,
33 CAP_SDIO,
34 CAP_UARTB,
35 CAP_KEYPAD,
36 CAP_CLCD,
37 CAP_GE,
38 CAP_LEDM,
39 CAP_BBL,
40 CAP_VDEC,
41 CAP_PIF,
42 CAP_APM,
43 CAP_SPU,
44 CAP_PKA,
45 CAP_RNG,
46} CAP_CAPABILITY_T;
47
48typedef enum {
49 CAP_LCD_WVGA = 0,
50 CAP_LCD_VGA = 0x1,
51 CAP_LCD_WQVGA = 0x2,
52 CAP_LCD_QVGA = 0x3
53} CAP_LCD_RES_T;
54
55/* ---- Public Variable Externs ------------------------------------------ */
56/* ---- Public Function Prototypes --------------------------------------- */
57
58static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
59static inline uint32_t cap_getMaxArmSpeedHz(void);
60static inline uint32_t cap_getMaxVpmSpeedHz(void);
61static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
62
63#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
new file mode 100644
index 00000000000..933ce68ed90
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -0,0 +1,409 @@
1/*****************************************************************************
2* Copyright 2009 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CAP_INLINE_H
16#define CAP_INLINE_H
17
18/* ---- Include Files ---------------------------------------------------- */
19#include <mach/csp/cap.h>
20#include <cfg_global.h>
21
22/* ---- Public Constants and Types --------------------------------------- */
23#define CAP_CONFIG0_VPM_DIS 0x00000001
24#define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002
25#define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004
26#define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008
27#define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010
28#define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020
29#define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040
30#define CAP_CONFIG0_USB0_DIS 0x00000080
31#define CAP_CONFIG0_USB1_DIS 0x00000100
32#define CAP_CONFIG0_TSC_DIS 0x00000200
33#define CAP_CONFIG0_EHSS0_DIS 0x00000400
34#define CAP_CONFIG0_EHSS1_DIS 0x00000800
35#define CAP_CONFIG0_SDIO0_DIS 0x00001000
36#define CAP_CONFIG0_SDIO1_DIS 0x00002000
37#define CAP_CONFIG0_UARTB_DIS 0x00004000
38#define CAP_CONFIG0_KEYPAD_DIS 0x00008000
39#define CAP_CONFIG0_CLCD_DIS 0x00010000
40#define CAP_CONFIG0_GE_DIS 0x00020000
41#define CAP_CONFIG0_LEDM_DIS 0x00040000
42#define CAP_CONFIG0_BBL_DIS 0x00080000
43#define CAP_CONFIG0_VDEC_DIS 0x00100000
44#define CAP_CONFIG0_PIF_DIS 0x00200000
45#define CAP_CONFIG0_RESERVED1_DIS 0x00400000
46#define CAP_CONFIG0_RESERVED2_DIS 0x00800000
47
48#define CAP_CONFIG1_APMA_DIS 0x00000001
49#define CAP_CONFIG1_APMB_DIS 0x00000002
50#define CAP_CONFIG1_APMC_DIS 0x00000004
51#define CAP_CONFIG1_CLCD_RES_MASK 0x00000600
52#define CAP_CONFIG1_CLCD_RES_SHIFT 9
53#define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
54#define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
55#define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
56#define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
57
58#define CAP_CONFIG2_SPU_DIS 0x00000010
59#define CAP_CONFIG2_PKA_DIS 0x00000020
60#define CAP_CONFIG2_RNG_DIS 0x00000080
61
62#if (CFG_GLOBAL_CHIP == BCM11107)
63#define capConfig0 0
64#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
65#define capConfig2 0
66#define CAP_APM_MAX_NUM_CHANS 3
67#elif (CFG_GLOBAL_CHIP == FPGA11107)
68#define capConfig0 0
69#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
70#define capConfig2 0
71#define CAP_APM_MAX_NUM_CHANS 3
72#elif (CFG_GLOBAL_CHIP == BCM11109)
73#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
74#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
75#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
76#define CAP_APM_MAX_NUM_CHANS 2
77#elif (CFG_GLOBAL_CHIP == BCM11170)
78#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
79#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
80#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
81#define CAP_APM_MAX_NUM_CHANS 2
82#elif (CFG_GLOBAL_CHIP == BCM11110)
83#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
84#define capConfig1 CAP_CONFIG1_APMC_DIS
85#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
86#define CAP_APM_MAX_NUM_CHANS 2
87#elif (CFG_GLOBAL_CHIP == BCM11211)
88#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
89#define capConfig1 CAP_CONFIG1_APMC_DIS
90#define capConfig2 0
91#define CAP_APM_MAX_NUM_CHANS 2
92#else
93#error CFG_GLOBAL_CHIP type capabilities not defined
94#endif
95
96#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
97#define CAP_HW_CFG_ARM_CLK_HZ 500000000
98#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
99#define CAP_HW_CFG_ARM_CLK_HZ 300000000
100#elif (CFG_GLOBAL_CHIP == BCM11211)
101#define CAP_HW_CFG_ARM_CLK_HZ 666666666
102#else
103#error CFG_GLOBAL_CHIP type capabilities not defined
104#endif
105
106#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
107#define CAP_HW_CFG_VPM_CLK_HZ 333333333
108#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
109#define CAP_HW_CFG_VPM_CLK_HZ 200000000
110#else
111#error CFG_GLOBAL_CHIP type capabilities not defined
112#endif
113
114/* ---- Public Variable Externs ------------------------------------------ */
115/* ---- Public Function Prototypes --------------------------------------- */
116
117/****************************************************************************
118* cap_isPresent -
119*
120* PURPOSE:
121* Determines if the chip has a certain capability present
122*
123* PARAMETERS:
124* capability - type of capability to determine if present
125*
126* RETURNS:
127* CAP_PRESENT or CAP_NOT_PRESENT
128****************************************************************************/
129static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
130{
131 CAP_RC_T returnVal = CAP_NOT_PRESENT;
132
133 switch (capability) {
134 case CAP_VPM:
135 {
136 if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
137 returnVal = CAP_PRESENT;
138 }
139 }
140 break;
141
142 case CAP_ETH_PHY:
143 {
144 if ((index == 0)
145 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
146 returnVal = CAP_PRESENT;
147 }
148 if ((index == 1)
149 && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
150 returnVal = CAP_PRESENT;
151 }
152 }
153 break;
154
155 case CAP_ETH_GMII:
156 {
157 if ((index == 0)
158 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
159 returnVal = CAP_PRESENT;
160 }
161 if ((index == 1)
162 && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
163 returnVal = CAP_PRESENT;
164 }
165 }
166 break;
167
168 case CAP_ETH_SGMII:
169 {
170 if ((index == 0)
171 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
172 returnVal = CAP_PRESENT;
173 }
174 if ((index == 1)
175 && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
176 returnVal = CAP_PRESENT;
177 }
178 }
179 break;
180
181 case CAP_USB:
182 {
183 if ((index == 0)
184 && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
185 returnVal = CAP_PRESENT;
186 }
187 if ((index == 1)
188 && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
189 returnVal = CAP_PRESENT;
190 }
191 }
192 break;
193
194 case CAP_TSC:
195 {
196 if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
197 returnVal = CAP_PRESENT;
198 }
199 }
200 break;
201
202 case CAP_EHSS:
203 {
204 if ((index == 0)
205 && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
206 returnVal = CAP_PRESENT;
207 }
208 if ((index == 1)
209 && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
210 returnVal = CAP_PRESENT;
211 }
212 }
213 break;
214
215 case CAP_SDIO:
216 {
217 if ((index == 0)
218 && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
219 returnVal = CAP_PRESENT;
220 }
221 if ((index == 1)
222 && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
223 returnVal = CAP_PRESENT;
224 }
225 }
226 break;
227
228 case CAP_UARTB:
229 {
230 if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
231 returnVal = CAP_PRESENT;
232 }
233 }
234 break;
235
236 case CAP_KEYPAD:
237 {
238 if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
239 returnVal = CAP_PRESENT;
240 }
241 }
242 break;
243
244 case CAP_CLCD:
245 {
246 if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
247 returnVal = CAP_PRESENT;
248 }
249 }
250 break;
251
252 case CAP_GE:
253 {
254 if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
255 returnVal = CAP_PRESENT;
256 }
257 }
258 break;
259
260 case CAP_LEDM:
261 {
262 if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
263 returnVal = CAP_PRESENT;
264 }
265 }
266 break;
267
268 case CAP_BBL:
269 {
270 if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
271 returnVal = CAP_PRESENT;
272 }
273 }
274 break;
275
276 case CAP_VDEC:
277 {
278 if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
279 returnVal = CAP_PRESENT;
280 }
281 }
282 break;
283
284 case CAP_PIF:
285 {
286 if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
287 returnVal = CAP_PRESENT;
288 }
289 }
290 break;
291
292 case CAP_APM:
293 {
294 if ((index == 0)
295 && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
296 returnVal = CAP_PRESENT;
297 }
298 if ((index == 1)
299 && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
300 returnVal = CAP_PRESENT;
301 }
302 if ((index == 2)
303 && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
304 returnVal = CAP_PRESENT;
305 }
306 }
307 break;
308
309 case CAP_SPU:
310 {
311 if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
312 returnVal = CAP_PRESENT;
313 }
314 }
315 break;
316
317 case CAP_PKA:
318 {
319 if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
320 returnVal = CAP_PRESENT;
321 }
322 }
323 break;
324
325 case CAP_RNG:
326 {
327 if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
328 returnVal = CAP_PRESENT;
329 }
330 }
331 break;
332
333 default:
334 {
335 }
336 break;
337 }
338 return returnVal;
339}
340
341/****************************************************************************
342* cap_getMaxArmSpeedHz -
343*
344* PURPOSE:
345* Determines the maximum speed of the ARM CPU
346*
347* PARAMETERS:
348* none
349*
350* RETURNS:
351* clock speed in Hz that the ARM processor is able to run at
352****************************************************************************/
353static inline uint32_t cap_getMaxArmSpeedHz(void)
354{
355#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
356 return 500000000;
357#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
358 return 300000000;
359#elif (CFG_GLOBAL_CHIP == BCM11211)
360 return 666666666;
361#else
362#error CFG_GLOBAL_CHIP type capabilities not defined
363#endif
364}
365
366/****************************************************************************
367* cap_getMaxVpmSpeedHz -
368*
369* PURPOSE:
370* Determines the maximum speed of the VPM
371*
372* PARAMETERS:
373* none
374*
375* RETURNS:
376* clock speed in Hz that the VPM is able to run at
377****************************************************************************/
378static inline uint32_t cap_getMaxVpmSpeedHz(void)
379{
380#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
381 return 333333333;
382#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
383 return 200000000;
384#else
385#error CFG_GLOBAL_CHIP type capabilities not defined
386#endif
387}
388
389/****************************************************************************
390* cap_getMaxLcdRes -
391*
392* PURPOSE:
393* Determines the maximum LCD resolution capabilities
394*
395* PARAMETERS:
396* none
397*
398* RETURNS:
399* CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
400*
401****************************************************************************/
402static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
403{
404 return (CAP_LCD_RES_T)
405 ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
406 CAP_CONFIG1_CLCD_RES_SHIFT);
407}
408
409#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
new file mode 100644
index 00000000000..161973385fa
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -0,0 +1,1123 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CHIPC_DEF_H
16#define CHIPC_DEF_H
17
18/* ---- Include Files ----------------------------------------------------- */
19
20#include <csp/stdint.h>
21#include <csp/errno.h>
22#include <csp/reg.h>
23#include <mach/csp/chipcHw_reg.h>
24
25/* ---- Public Constants and Types ---------------------------------------- */
26
27/* Set 1 to configure DDR/VPM phase alignment by HW */
28#define chipcHw_DDR_HW_PHASE_ALIGN 0
29#define chipcHw_VPM_HW_PHASE_ALIGN 0
30
31typedef uint32_t chipcHw_freq;
32
33/* Configurable miscellaneous clocks */
34typedef enum {
35 chipcHw_CLOCK_DDR, /* DDR PHY Clock */
36 chipcHw_CLOCK_ARM, /* ARM Clock */
37 chipcHw_CLOCK_ESW, /* Ethernet Switch Clock */
38 chipcHw_CLOCK_VPM, /* VPM Clock */
39 chipcHw_CLOCK_ESW125, /* Ethernet MII Clock */
40 chipcHw_CLOCK_UART, /* UART Clock */
41 chipcHw_CLOCK_SDIO0, /* SDIO 0 Clock */
42 chipcHw_CLOCK_SDIO1, /* SDIO 1 Clock */
43 chipcHw_CLOCK_SPI, /* SPI Clock */
44 chipcHw_CLOCK_ETM, /* ARM ETM Clock */
45
46 chipcHw_CLOCK_BUS, /* BUS Clock */
47 chipcHw_CLOCK_OTP, /* OTP Clock */
48 chipcHw_CLOCK_I2C, /* I2C Host Clock */
49 chipcHw_CLOCK_I2S0, /* I2S 0 Host Clock */
50 chipcHw_CLOCK_RTBUS, /* DDR PHY Configuration Clock */
51 chipcHw_CLOCK_APM100, /* APM100 Clock */
52 chipcHw_CLOCK_TSC, /* Touch screen Clock */
53 chipcHw_CLOCK_LED, /* LED Clock */
54
55 chipcHw_CLOCK_USB, /* USB Clock */
56 chipcHw_CLOCK_LCD, /* LCD CLock */
57 chipcHw_CLOCK_APM, /* APM Clock */
58
59 chipcHw_CLOCK_I2S1, /* I2S 1 Host Clock */
60} chipcHw_CLOCK_e;
61
62/* System booting strap options */
63typedef enum {
64 chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
65 chipcHw_BOOT_DEVICE_SERIAL_FLASH =
66 chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
67 chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
68 chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
69 chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
70 chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
71 chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
72 chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
73} chipcHw_BOOT_DEVICE_e;
74
75/* System booting modes */
76typedef enum {
77 chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
78 chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
79 chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
80 chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
81} chipcHw_BOOT_MODE_e;
82
83/* NAND Flash page size strap options */
84typedef enum {
85 chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
86 chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
87 chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
88 chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
89} chipcHw_NAND_PAGESIZE_e;
90
91/* GPIO Pin function */
92typedef enum {
93 chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
94 chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
95 chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
96 chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
97 chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
98 chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
99 chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
100 chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
101 chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
102 chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
103 chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
104 chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
105 chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
106 chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
107} chipcHw_GPIO_FUNCTION_e;
108
109/* PIN Output slew rate */
110typedef enum {
111 chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
112 chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
113} chipcHw_PIN_SLEW_RATE_e;
114
115/* PIN Current drive strength */
116typedef enum {
117 chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
118 chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
119 chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
120 chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
121 chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
122 chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
123} chipcHw_PIN_CURRENT_STRENGTH_e;
124
125/* PIN Pull up register settings */
126typedef enum {
127 chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
128 chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
129 chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
130} chipcHw_PIN_PULL_e;
131
132/* PIN input type settings */
133typedef enum {
134 chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
135 chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
136} chipcHw_PIN_INPUTTYPE_e;
137
138/* Allow/Disalow the support of spread spectrum */
139typedef enum {
140 chipcHw_SPREAD_SPECTRUM_DISALLOW, /* Spread spectrum support is not allowed */
141 chipcHw_SPREAD_SPECTRUM_ALLOW /* Spread spectrum support is allowed */
142} chipcHw_SPREAD_SPECTRUM_e;
143
144typedef struct {
145 chipcHw_SPREAD_SPECTRUM_e ssSupport; /* Allow/Disalow to support spread spectrum.
146 If supported, call chipcHw_enableSpreadSpectrum ()
147 to activate the spread spectrum with desired spread. */
148 uint32_t pllVcoFreqHz; /* PLL VCO frequency in Hz */
149 uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
150 uint32_t busClockFreqHz; /* Bus clock frequency in Hz */
151 uint32_t armBusRatio; /* ARM clock : Bus clock */
152 uint32_t vpmBusRatio; /* VPM clock : Bus clock */
153 uint32_t ddrBusRatio; /* DDR clock : Bus clock */
154} chipcHw_INIT_PARAM_t;
155
156/* CHIP revision number */
157typedef enum {
158 chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
159 chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
160} chipcHw_REV_NUMBER_e;
161
162typedef enum {
163 chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
164 chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
165 chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
166 chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
167} chipcHw_VPM_HW_PHASE_INTR_e;
168
169typedef enum {
170 chipcHw_DDR_HW_PHASE_MARGIN_STRICT, /* Strict margin for DDR phase align condition */
171 chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for DDR phase align condition */
172 chipcHw_DDR_HW_PHASE_MARGIN_WIDE /* Wider margin for DDR phase align condition */
173} chipcHw_DDR_HW_PHASE_MARGIN_e;
174
175typedef enum {
176 chipcHw_VPM_HW_PHASE_MARGIN_STRICT, /* Strict margin for VPM phase align condition */
177 chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for VPM phase align condition */
178 chipcHw_VPM_HW_PHASE_MARGIN_WIDE /* Wider margin for VPM phase align condition */
179} chipcHw_VPM_HW_PHASE_MARGIN_e;
180
181#define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */
182
183/* Programmable pin defines */
184#define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
185 /* GPIO pin 0 - 60 */
186#define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */
187#define chipcHw_PIN_NVI_A (chipcHw_GPIO_COUNT + 1) /* NVI Interface */
188#define chipcHw_PIN_NVI_D (chipcHw_GPIO_COUNT + 2) /* NVI Interface */
189#define chipcHw_PIN_NVI_OEB (chipcHw_GPIO_COUNT + 3) /* NVI Interface */
190#define chipcHw_PIN_NVI_WEB (chipcHw_GPIO_COUNT + 4) /* NVI Interface */
191#define chipcHw_PIN_NVI_CS (chipcHw_GPIO_COUNT + 5) /* NVI Interface */
192#define chipcHw_PIN_NVI_NAND_CSB (chipcHw_GPIO_COUNT + 6) /* NVI Interface */
193#define chipcHw_PIN_NVI_FLASHWP (chipcHw_GPIO_COUNT + 7) /* NVI Interface */
194#define chipcHw_PIN_NVI_NAND_RDYB (chipcHw_GPIO_COUNT + 8) /* NVI Interface */
195#define chipcHw_PIN_CL_DATA_0_17 (chipcHw_GPIO_COUNT + 9) /* LCD Data 0 - 17 */
196#define chipcHw_PIN_CL_DATA_18_20 (chipcHw_GPIO_COUNT + 10) /* LCD Data 18 - 20 */
197#define chipcHw_PIN_CL_DATA_21_23 (chipcHw_GPIO_COUNT + 11) /* LCD Data 21 - 23 */
198#define chipcHw_PIN_CL_POWER (chipcHw_GPIO_COUNT + 12) /* LCD Power */
199#define chipcHw_PIN_CL_ACK (chipcHw_GPIO_COUNT + 13) /* LCD Ack */
200#define chipcHw_PIN_CL_FP (chipcHw_GPIO_COUNT + 14) /* LCD FP */
201#define chipcHw_PIN_CL_LP (chipcHw_GPIO_COUNT + 15) /* LCD LP */
202#define chipcHw_PIN_UARTRXD (chipcHw_GPIO_COUNT + 16) /* UART Receive */
203
204/* ---- Public Variable Externs ------------------------------------------ */
205/* ---- Public Function Prototypes --------------------------------------- */
206
207/****************************************************************************/
208/**
209* @brief Initializes the clock module
210*
211*/
212/****************************************************************************/
213void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
214 ) __attribute__ ((section(".aramtext")));
215
216/****************************************************************************/
217/**
218* @brief Enables the PLL1
219*
220* This function enables the PLL1
221*
222*/
223/****************************************************************************/
224void chipcHw_pll1Enable(uint32_t vcoFreqHz, /* [ IN ] VCO frequency in Hz */
225 chipcHw_SPREAD_SPECTRUM_e ssSupport /* [ IN ] SS status */
226 ) __attribute__ ((section(".aramtext")));
227
228/****************************************************************************/
229/**
230* @brief Enables the PLL2
231*
232* This function enables the PLL2
233*
234*/
235/****************************************************************************/
236void chipcHw_pll2Enable(uint32_t vcoFreqHz /* [ IN ] VCO frequency in Hz */
237 ) __attribute__ ((section(".aramtext")));
238
239/****************************************************************************/
240/**
241* @brief Disable the PLL1
242*
243*/
244/****************************************************************************/
245static inline void chipcHw_pll1Disable(void);
246
247/****************************************************************************/
248/**
249* @brief Disable the PLL2
250*
251*/
252/****************************************************************************/
253static inline void chipcHw_pll2Disable(void);
254
255/****************************************************************************/
256/**
257* @brief Set clock fequency for miscellaneous configurable clocks
258*
259* This function sets clock frequency
260*
261* @return Configured clock frequency in KHz
262*
263*/
264/****************************************************************************/
265chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
266 ) __attribute__ ((section(".aramtext")));
267
268/****************************************************************************/
269/**
270* @brief Set clock fequency for miscellaneous configurable clocks
271*
272* This function sets clock frequency
273*
274* @return Configured clock frequency in Hz
275*
276*/
277/****************************************************************************/
278chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
279 uint32_t freq /* [ IN ] Clock frequency in Hz */
280 ) __attribute__ ((section(".aramtext")));
281
282/****************************************************************************/
283/**
284* @brief Set VPM clock in sync with BUS clock
285*
286* This function does the phase adjustment between VPM and BUS clock
287*
288* @return >= 0 : On success ( # of adjustment required )
289* -1 : On failure
290*/
291/****************************************************************************/
292int chipcHw_vpmPhaseAlign(void);
293
294/****************************************************************************/
295/**
296* @brief Enables core a clock of a certain device
297*
298* This function enables a core clock
299*
300* @return void
301*
302* @note Doesnot affect the bus interface clock
303*/
304/****************************************************************************/
305static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
306 );
307
308/****************************************************************************/
309/**
310* @brief Disabled a core clock of a certain device
311*
312* This function disables a core clock
313*
314* @return void
315*
316* @note Doesnot affect the bus interface clock
317*/
318/****************************************************************************/
319static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
320 );
321
322/****************************************************************************/
323/**
324* @brief Enables bypass clock of a certain device
325*
326* This function enables bypass clock
327*
328* @note Doesnot affect the bus interface clock
329*/
330/****************************************************************************/
331static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
332 );
333
334/****************************************************************************/
335/**
336* @brief Disabled bypass clock of a certain device
337*
338* This function disables bypass clock
339*
340* @note Doesnot affect the bus interface clock
341*/
342/****************************************************************************/
343static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
344 );
345
346/****************************************************************************/
347/**
348* @brief Get Numeric Chip ID
349*
350* This function returns Chip ID that includes the revison number
351*
352* @return Complete numeric Chip ID
353*
354*/
355/****************************************************************************/
356static inline uint32_t chipcHw_getChipId(void);
357
358/****************************************************************************/
359/**
360* @brief Get Chip Product ID
361*
362* This function returns Chip Product ID
363*
364* @return Chip Product ID
365*/
366/****************************************************************************/
367static inline uint32_t chipcHw_getChipProductId(void);
368
369/****************************************************************************/
370/**
371* @brief Get revision number
372*
373* This function returns revision number of the chip
374*
375* @return Revision number
376*/
377/****************************************************************************/
378static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
379
380/****************************************************************************/
381/**
382* @brief Enables bus interface clock
383*
384* Enables bus interface clock of various device
385*
386* @return void
387*
388* @note use chipcHw_REG_BUS_CLOCK_XXXX
389*/
390/****************************************************************************/
391static inline void chipcHw_busInterfaceClockEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */
392 );
393
394/****************************************************************************/
395/**
396* @brief Disables bus interface clock
397*
398* Disables bus interface clock of various device
399*
400* @return void
401*
402* @note use chipcHw_REG_BUS_CLOCK_XXXX
403*/
404/****************************************************************************/
405static inline void chipcHw_busInterfaceClockDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */
406 );
407
408/****************************************************************************/
409/**
410* @brief Enables various audio channels
411*
412* Enables audio channel
413*
414* @return void
415*
416* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
417*/
418/****************************************************************************/
419static inline void chipcHw_audioChannelEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
420 );
421
422/****************************************************************************/
423/**
424* @brief Disables various audio channels
425*
426* Disables audio channel
427*
428* @return void
429*
430* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
431*/
432/****************************************************************************/
433static inline void chipcHw_audioChannelDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
434 );
435
436/****************************************************************************/
437/**
438* @brief Soft resets devices
439*
440* Soft resets various devices
441*
442* @return void
443*
444* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
445*/
446/****************************************************************************/
447static inline void chipcHw_softReset(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
448 );
449
450static inline void chipcHw_softResetDisable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
451 );
452
453static inline void chipcHw_softResetEnable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
454 );
455
456/****************************************************************************/
457/**
458* @brief Configures misc CHIP functionality
459*
460* Configures CHIP functionality
461*
462* @return void
463*
464* @note use chipcHw_REG_MISC_CTRL_XXXXXX
465*/
466/****************************************************************************/
467static inline void chipcHw_miscControl(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
468 );
469
470static inline void chipcHw_miscControlDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
471 );
472
473static inline void chipcHw_miscControlEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
474 );
475
476/****************************************************************************/
477/**
478* @brief Set OTP options
479*
480* Set OTP options
481*
482* @return void
483*
484* @note use chipcHw_REG_OTP_XXXXXX
485*/
486/****************************************************************************/
487static inline void chipcHw_setOTPOption(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
488 );
489
490/****************************************************************************/
491/**
492* @brief Get sticky bits
493*
494* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
495*
496*/
497/****************************************************************************/
498static inline uint32_t chipcHw_getStickyBits(void);
499
500/****************************************************************************/
501/**
502* @brief Set sticky bits
503*
504* @return void
505*
506* @note use chipcHw_REG_STICKY_XXXXXX
507*/
508/****************************************************************************/
509static inline void chipcHw_setStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
510 );
511
512/****************************************************************************/
513/**
514* @brief Clear sticky bits
515*
516* @return void
517*
518* @note use chipcHw_REG_STICKY_XXXXXX
519*/
520/****************************************************************************/
521static inline void chipcHw_clearStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
522 );
523
524/****************************************************************************/
525/**
526* @brief Get software override strap options
527*
528* Retrieves software override strap options
529*
530* @return Software override strap value
531*
532*/
533/****************************************************************************/
534static inline uint32_t chipcHw_getSoftStraps(void);
535
536/****************************************************************************/
537/**
538* @brief Set software override strap options
539*
540* set software override strap options
541*
542* @return nothing
543*
544*/
545/****************************************************************************/
546static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
547
548/****************************************************************************/
549/**
550* @brief Get pin strap options
551*
552* Retrieves pin strap options
553*
554* @return Pin strap value
555*
556*/
557/****************************************************************************/
558static inline uint32_t chipcHw_getPinStraps(void);
559
560/****************************************************************************/
561/**
562* @brief Get valid pin strap options
563*
564* Retrieves valid pin strap options
565*
566* @return valid Pin strap value
567*
568*/
569/****************************************************************************/
570static inline uint32_t chipcHw_getValidStraps(void);
571
572/****************************************************************************/
573/**
574* @brief Initialize valid pin strap options
575*
576* Retrieves valid pin strap options by copying HW strap options to soft register
577* (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
578*
579* @return nothing
580*
581*/
582/****************************************************************************/
583static inline void chipcHw_initValidStraps(void);
584
585/****************************************************************************/
586/**
587* @brief Get status (enabled/disabled) of bus interface clock
588*
589* This function returns the status of devices' bus interface clock
590*
591* @return Bus interface clock
592*
593*/
594/****************************************************************************/
595static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
596
597/****************************************************************************/
598/**
599* @brief Get boot device
600*
601* This function returns the device type used in booting the system
602*
603* @return Boot device of type chipcHw_BOOT_DEVICE_e
604*
605*/
606/****************************************************************************/
607static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
608
609/****************************************************************************/
610/**
611* @brief Get boot mode
612*
613* This function returns the way the system was booted
614*
615* @return Boot mode of type chipcHw_BOOT_MODE_e
616*
617*/
618/****************************************************************************/
619static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
620
621/****************************************************************************/
622/**
623* @brief Get NAND flash page size
624*
625* This function returns the NAND device page size
626*
627* @return Boot NAND device page size
628*
629*/
630/****************************************************************************/
631static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
632
633/****************************************************************************/
634/**
635* @brief Get NAND flash address cycle configuration
636*
637* This function returns the NAND flash address cycle configuration
638*
639* @return 0 = Do not extra address cycle, 1 = Add extra cycle
640*
641*/
642/****************************************************************************/
643static inline int chipcHw_getNandExtraCycle(void);
644
645/****************************************************************************/
646/**
647* @brief Activates PIF interface
648*
649* This function activates PIF interface by taking control of LCD pins
650*
651* @note
652* When activated, LCD pins will be defined as follows for PIF operation
653*
654* CLD[17:0] = pif_data[17:0]
655* CLD[23:18] = pif_address[5:0]
656* CLPOWER = pif_wr_str
657* CLCP = pif_rd_str
658* CLAC = pif_hat1
659* CLFP = pif_hrdy1
660* CLLP = pif_hat2
661* GPIO[42] = pif_hrdy2
662*
663* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
664*
665*/
666/****************************************************************************/
667static inline void chipcHw_activatePifInterface(void);
668
669/****************************************************************************/
670/**
671* @brief Activates LCD interface
672*
673* This function activates LCD interface
674*
675* @note
676* When activated, LCD pins will be defined as follows
677*
678* CLD[17:0] = LCD data
679* CLD[23:18] = LCD data
680* CLPOWER = LCD power
681* CLCP =
682* CLAC = LCD ack
683* CLFP =
684* CLLP =
685*/
686/****************************************************************************/
687static inline void chipcHw_activateLcdInterface(void);
688
689/****************************************************************************/
690/**
691* @brief Deactivates PIF/LCD interface
692*
693* This function deactivates PIF/LCD interface
694*
695* @note
696* When deactivated LCD pins will be in rti-stated
697*
698*/
699/****************************************************************************/
700static inline void chipcHw_deactivatePifLcdInterface(void);
701
702/****************************************************************************/
703/**
704* @brief Get to know the configuration of GPIO pin
705*
706*/
707/****************************************************************************/
708static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin /* GPIO Pin number */
709 );
710
711/****************************************************************************/
712/**
713* @brief Configure GPIO pin function
714*
715*/
716/****************************************************************************/
717static inline void chipcHw_setGpioPinFunction(int pin, /* GPIO Pin number */
718 chipcHw_GPIO_FUNCTION_e func /* Configuration function */
719 );
720
721/****************************************************************************/
722/**
723* @brief Set Pin slew rate
724*
725* This function sets the slew of individual pin
726*
727*/
728/****************************************************************************/
729static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
730 chipcHw_PIN_SLEW_RATE_e slewRate /* Pin slew rate */
731 );
732
733/****************************************************************************/
734/**
735* @brief Set Pin output drive current
736*
737* This function sets output drive current of individual pin
738*
739* Note: Avoid the use of the word 'current' since linux headers define this
740* to be the current task.
741*/
742/****************************************************************************/
743static inline void chipcHw_setPinOutputCurrent(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
744 chipcHw_PIN_CURRENT_STRENGTH_e curr /* Pin current rating */
745 );
746
747/****************************************************************************/
748/**
749* @brief Set Pin pullup register
750*
751* This function sets pullup register of individual pin
752*
753*/
754/****************************************************************************/
755static inline void chipcHw_setPinPullup(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
756 chipcHw_PIN_PULL_e pullup /* Pullup register settings */
757 );
758
759/****************************************************************************/
760/**
761* @brief Set Pin input type
762*
763* This function sets input type of individual Pin
764*
765*/
766/****************************************************************************/
767static inline void chipcHw_setPinInputType(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
768 chipcHw_PIN_INPUTTYPE_e inputType /* Pin input type */
769 );
770
771/****************************************************************************/
772/**
773* @brief Retrieves a string representation of the mux setting for a pin.
774*
775* @return Pointer to a character string.
776*/
777/****************************************************************************/
778
779const char *chipcHw_getGpioPinFunctionStr(int pin);
780
781/****************************************************************************/
782/** @brief issue warmReset
783 */
784/****************************************************************************/
785void chipcHw_reset(uint32_t mask);
786
787/****************************************************************************/
788/** @brief clock reconfigure
789 */
790/****************************************************************************/
791void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
792 uint32_t ddrRatio);
793
794/****************************************************************************/
795/**
796* @brief Enable Spread Spectrum
797*
798* @note chipcHw_Init() must be called earlier
799*/
800/****************************************************************************/
801static inline void chipcHw_enableSpreadSpectrum(void);
802
803/****************************************************************************/
804/**
805* @brief Disable Spread Spectrum
806*
807*/
808/****************************************************************************/
809static inline void chipcHw_disableSpreadSpectrum(void);
810
811/****************************************************************************/
812/** @brief Checks if software strap is enabled
813 *
814 * @return 1 : When enable
815 * 0 : When disable
816 */
817/****************************************************************************/
818static inline int chipcHw_isSoftwareStrapsEnable(void);
819
820/****************************************************************************/
821/** @brief Enable software strap
822 */
823/****************************************************************************/
824static inline void chipcHw_softwareStrapsEnable(void);
825
826/****************************************************************************/
827/** @brief Disable software strap
828 */
829/****************************************************************************/
830static inline void chipcHw_softwareStrapsDisable(void);
831
832/****************************************************************************/
833/** @brief PLL test enable
834 */
835/****************************************************************************/
836static inline void chipcHw_pllTestEnable(void);
837
838/****************************************************************************/
839/** @brief PLL2 test enable
840 */
841/****************************************************************************/
842static inline void chipcHw_pll2TestEnable(void);
843
844/****************************************************************************/
845/** @brief PLL test disable
846 */
847/****************************************************************************/
848static inline void chipcHw_pllTestDisable(void);
849
850/****************************************************************************/
851/** @brief PLL2 test disable
852 */
853/****************************************************************************/
854static inline void chipcHw_pll2TestDisable(void);
855
856/****************************************************************************/
857/** @brief Get PLL test status
858 */
859/****************************************************************************/
860static inline int chipcHw_isPllTestEnable(void);
861
862/****************************************************************************/
863/** @brief Get PLL2 test status
864 */
865/****************************************************************************/
866static inline int chipcHw_isPll2TestEnable(void);
867
868/****************************************************************************/
869/** @brief PLL test select
870 */
871/****************************************************************************/
872static inline void chipcHw_pllTestSelect(uint32_t val);
873
874/****************************************************************************/
875/** @brief PLL2 test select
876 */
877/****************************************************************************/
878static inline void chipcHw_pll2TestSelect(uint32_t val);
879
880/****************************************************************************/
881/** @brief Get PLL test selected option
882 */
883/****************************************************************************/
884static inline uint8_t chipcHw_getPllTestSelected(void);
885
886/****************************************************************************/
887/** @brief Get PLL2 test selected option
888 */
889/****************************************************************************/
890static inline uint8_t chipcHw_getPll2TestSelected(void);
891
892/****************************************************************************/
893/**
894* @brief Enables DDR SW phase alignment interrupt
895*/
896/****************************************************************************/
897static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
898
899/****************************************************************************/
900/**
901* @brief Disables DDR SW phase alignment interrupt
902*/
903/****************************************************************************/
904static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
905
906/****************************************************************************/
907/**
908* @brief Set VPM SW phase alignment interrupt mode
909*
910* This function sets VPM phase alignment interrupt
911*
912*/
913/****************************************************************************/
914static inline void
915chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
916
917/****************************************************************************/
918/**
919* @brief Enable DDR phase alignment in software
920*
921*/
922/****************************************************************************/
923static inline void chipcHw_ddrSwPhaseAlignEnable(void);
924
925/****************************************************************************/
926/**
927* @brief Disable DDR phase alignment in software
928*
929*/
930/****************************************************************************/
931static inline void chipcHw_ddrSwPhaseAlignDisable(void);
932
933/****************************************************************************/
934/**
935* @brief Enable DDR phase alignment in hardware
936*
937*/
938/****************************************************************************/
939static inline void chipcHw_ddrHwPhaseAlignEnable(void);
940
941/****************************************************************************/
942/**
943* @brief Disable DDR phase alignment in hardware
944*
945*/
946/****************************************************************************/
947static inline void chipcHw_ddrHwPhaseAlignDisable(void);
948
949/****************************************************************************/
950/**
951* @brief Enable VPM phase alignment in software
952*
953*/
954/****************************************************************************/
955static inline void chipcHw_vpmSwPhaseAlignEnable(void);
956
957/****************************************************************************/
958/**
959* @brief Disable VPM phase alignment in software
960*
961*/
962/****************************************************************************/
963static inline void chipcHw_vpmSwPhaseAlignDisable(void);
964
965/****************************************************************************/
966/**
967* @brief Enable VPM phase alignment in hardware
968*
969*/
970/****************************************************************************/
971static inline void chipcHw_vpmHwPhaseAlignEnable(void);
972
973/****************************************************************************/
974/**
975* @brief Disable VPM phase alignment in hardware
976*
977*/
978/****************************************************************************/
979static inline void chipcHw_vpmHwPhaseAlignDisable(void);
980
981/****************************************************************************/
982/**
983* @brief Set DDR phase alignment margin in hardware
984*
985*/
986/****************************************************************************/
987static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin /* Margin alinging DDR phase */
988 );
989
990/****************************************************************************/
991/**
992* @brief Set VPM phase alignment margin in hardware
993*
994*/
995/****************************************************************************/
996static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin /* Margin alinging VPM phase */
997 );
998
999/****************************************************************************/
1000/**
1001* @brief Checks DDR phase aligned status done by HW
1002*
1003* @return 1: When aligned
1004* 0: When not aligned
1005*/
1006/****************************************************************************/
1007static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
1008
1009/****************************************************************************/
1010/**
1011* @brief Checks VPM phase aligned status done by HW
1012*
1013* @return 1: When aligned
1014* 0: When not aligned
1015*/
1016/****************************************************************************/
1017static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
1018
1019/****************************************************************************/
1020/**
1021* @brief Get DDR phase aligned status done by HW
1022*
1023*/
1024/****************************************************************************/
1025static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
1026
1027/****************************************************************************/
1028/**
1029* @brief Get VPM phase aligned status done by HW
1030*
1031*/
1032/****************************************************************************/
1033static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
1034
1035/****************************************************************************/
1036/**
1037* @brief Get DDR phase control value
1038*
1039*/
1040/****************************************************************************/
1041static inline uint32_t chipcHw_getDdrPhaseControl(void);
1042
1043/****************************************************************************/
1044/**
1045* @brief Get VPM phase control value
1046*
1047*/
1048/****************************************************************************/
1049static inline uint32_t chipcHw_getVpmPhaseControl(void);
1050
1051/****************************************************************************/
1052/**
1053* @brief DDR phase alignment timeout count
1054*
1055* @note If HW fails to perform the phase alignment, it will trigger
1056* a DDR phase alignment timeout interrupt.
1057*/
1058/****************************************************************************/
1059static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */
1060 );
1061
1062/****************************************************************************/
1063/**
1064* @brief VPM phase alignment timeout count
1065*
1066* @note If HW fails to perform the phase alignment, it will trigger
1067* a VPM phase alignment timeout interrupt.
1068*/
1069/****************************************************************************/
1070static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */
1071 );
1072
1073/****************************************************************************/
1074/**
1075* @brief DDR phase alignment timeout interrupt enable
1076*
1077*/
1078/****************************************************************************/
1079static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
1080
1081/****************************************************************************/
1082/**
1083* @brief VPM phase alignment timeout interrupt enable
1084*
1085*/
1086/****************************************************************************/
1087static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
1088
1089/****************************************************************************/
1090/**
1091* @brief DDR phase alignment timeout interrupt disable
1092*
1093*/
1094/****************************************************************************/
1095static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
1096
1097/****************************************************************************/
1098/**
1099* @brief VPM phase alignment timeout interrupt disable
1100*
1101*/
1102/****************************************************************************/
1103static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
1104
1105/****************************************************************************/
1106/**
1107* @brief Clear DDR phase alignment timeout interrupt
1108*
1109*/
1110/****************************************************************************/
1111static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
1112
1113/****************************************************************************/
1114/**
1115* @brief Clear VPM phase alignment timeout interrupt
1116*
1117*/
1118/****************************************************************************/
1119static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
1120
1121/* ---- Private Constants and Types -------------------------------------- */
1122
1123#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
new file mode 100644
index 00000000000..03238c29900
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -0,0 +1,1673 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef CHIPC_INLINE_H
16#define CHIPC_INLINE_H
17
18/* ---- Include Files ----------------------------------------------------- */
19
20#include <csp/errno.h>
21#include <csp/reg.h>
22#include <mach/csp/chipcHw_reg.h>
23#include <mach/csp/chipcHw_def.h>
24
25/* ---- Private Constants and Types --------------------------------------- */
26typedef enum {
27 chipcHw_OPTYPE_BYPASS, /* Bypass operation */
28 chipcHw_OPTYPE_OUTPUT /* Output operation */
29} chipcHw_OPTYPE_e;
30
31/* ---- Public Constants and Types ---------------------------------------- */
32/* ---- Public Variable Externs ------------------------------------------- */
33/* ---- Public Function Prototypes ---------------------------------------- */
34/* ---- Private Function Prototypes --------------------------------------- */
35static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
36 chipcHw_OPTYPE_e type, int mode);
37
38/****************************************************************************/
39/**
40* @brief Get Numeric Chip ID
41*
42* This function returns Chip ID that includes the revison number
43*
44* @return Complete numeric Chip ID
45*
46*/
47/****************************************************************************/
48static inline uint32_t chipcHw_getChipId(void)
49{
50 return pChipcHw->ChipId;
51}
52
53/****************************************************************************/
54/**
55* @brief Enable Spread Spectrum
56*
57* @note chipcHw_Init() must be called earlier
58*/
59/****************************************************************************/
60static inline void chipcHw_enableSpreadSpectrum(void)
61{
62 if ((pChipcHw->
63 PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
64 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
65 ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
66 (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
67 (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
68 ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
69 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
70 ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
71 }
72}
73
74/****************************************************************************/
75/**
76* @brief Disable Spread Spectrum
77*
78*/
79/****************************************************************************/
80static inline void chipcHw_disableSpreadSpectrum(void)
81{
82 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
83}
84
85/****************************************************************************/
86/**
87* @brief Get Chip Product ID
88*
89* This function returns Chip Product ID
90*
91* @return Chip Product ID
92*/
93/****************************************************************************/
94static inline uint32_t chipcHw_getChipProductId(void)
95{
96 return (pChipcHw->
97 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
98 chipcHw_REG_CHIPID_BASE_SHIFT;
99}
100
101/****************************************************************************/
102/**
103* @brief Get revision number
104*
105* This function returns revision number of the chip
106*
107* @return Revision number
108*/
109/****************************************************************************/
110static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
111{
112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
113}
114
115/****************************************************************************/
116/**
117* @brief Enables bus interface clock
118*
119* Enables bus interface clock of various device
120*
121* @return void
122*
123* @note use chipcHw_REG_BUS_CLOCK_XXXX for mask
124*/
125/****************************************************************************/
126static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
127{
128 reg32_modify_or(&pChipcHw->BusIntfClock, mask);
129}
130
131/****************************************************************************/
132/**
133* @brief Disables bus interface clock
134*
135* Disables bus interface clock of various device
136*
137* @return void
138*
139* @note use chipcHw_REG_BUS_CLOCK_XXXX
140*/
141/****************************************************************************/
142static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
143{
144 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
145}
146
147/****************************************************************************/
148/**
149* @brief Get status (enabled/disabled) of bus interface clock
150*
151* This function returns the status of devices' bus interface clock
152*
153* @return Bus interface clock
154*
155*/
156/****************************************************************************/
157static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
158{
159 return pChipcHw->BusIntfClock;
160}
161
162/****************************************************************************/
163/**
164* @brief Enables various audio channels
165*
166* Enables audio channel
167*
168* @return void
169*
170* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
171*/
172/****************************************************************************/
173static inline void chipcHw_audioChannelEnable(uint32_t mask)
174{
175 reg32_modify_or(&pChipcHw->AudioEnable, mask);
176}
177
178/****************************************************************************/
179/**
180* @brief Disables various audio channels
181*
182* Disables audio channel
183*
184* @return void
185*
186* @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
187*/
188/****************************************************************************/
189static inline void chipcHw_audioChannelDisable(uint32_t mask)
190{
191 reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
192}
193
194/****************************************************************************/
195/**
196* @brief Soft resets devices
197*
198* Soft resets various devices
199*
200* @return void
201*
202* @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
203*/
204/****************************************************************************/
205static inline void chipcHw_softReset(uint64_t mask)
206{
207 chipcHw_softResetEnable(mask);
208 chipcHw_softResetDisable(mask);
209}
210
211static inline void chipcHw_softResetDisable(uint64_t mask)
212{
213 uint32_t ctrl1 = (uint32_t) mask;
214 uint32_t ctrl2 = (uint32_t) (mask >> 32);
215
216 /* Deassert module soft reset */
217 REG_LOCAL_IRQ_SAVE;
218 pChipcHw->SoftReset1 ^= ctrl1;
219 pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
220 REG_LOCAL_IRQ_RESTORE;
221}
222
223static inline void chipcHw_softResetEnable(uint64_t mask)
224{
225 uint32_t ctrl1 = (uint32_t) mask;
226 uint32_t ctrl2 = (uint32_t) (mask >> 32);
227 uint32_t unhold = 0;
228
229 REG_LOCAL_IRQ_SAVE;
230 pChipcHw->SoftReset1 |= ctrl1;
231 /* Mask out unhold request bits */
232 pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
233
234 /* Process unhold requests */
235 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
236 unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
237 }
238
239 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
240 unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
241 }
242
243 if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
244 unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
245 }
246
247 if (unhold) {
248 /* Make sure unhold request is effective */
249 pChipcHw->SoftReset1 &= ~unhold;
250 }
251 REG_LOCAL_IRQ_RESTORE;
252}
253
254/****************************************************************************/
255/**
256* @brief Configures misc CHIP functionality
257*
258* Configures CHIP functionality
259*
260* @return void
261*
262* @note use chipcHw_REG_MISC_CTRL_XXXXXX
263*/
264/****************************************************************************/
265static inline void chipcHw_miscControl(uint32_t mask)
266{
267 reg32_write(&pChipcHw->MiscCtrl, mask);
268}
269
270static inline void chipcHw_miscControlDisable(uint32_t mask)
271{
272 reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
273}
274
275static inline void chipcHw_miscControlEnable(uint32_t mask)
276{
277 reg32_modify_or(&pChipcHw->MiscCtrl, mask);
278}
279
280/****************************************************************************/
281/**
282* @brief Set OTP options
283*
284* Set OTP options
285*
286* @return void
287*
288* @note use chipcHw_REG_OTP_XXXXXX
289*/
290/****************************************************************************/
291static inline void chipcHw_setOTPOption(uint64_t mask)
292{
293 uint32_t ctrl1 = (uint32_t) mask;
294 uint32_t ctrl2 = (uint32_t) (mask >> 32);
295
296 reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
297 reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
298}
299
300/****************************************************************************/
301/**
302* @brief Get sticky bits
303*
304* @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
305*
306*/
307/****************************************************************************/
308static inline uint32_t chipcHw_getStickyBits(void)
309{
310 return pChipcHw->Sticky;
311}
312
313/****************************************************************************/
314/**
315* @brief Set sticky bits
316*
317* @return void
318*
319* @note use chipcHw_REG_STICKY_XXXXXX
320*/
321/****************************************************************************/
322static inline void chipcHw_setStickyBits(uint32_t mask)
323{
324 uint32_t bits = 0;
325
326 REG_LOCAL_IRQ_SAVE;
327 if (mask & chipcHw_REG_STICKY_POR_BROM) {
328 bits |= chipcHw_REG_STICKY_POR_BROM;
329 } else {
330 uint32_t sticky;
331 sticky = pChipcHw->Sticky;
332
333 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
334 && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
335 bits |= chipcHw_REG_STICKY_BOOT_DONE;
336 }
337 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
338 && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
339 bits |= chipcHw_REG_STICKY_GENERAL_1;
340 }
341 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
342 && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
343 bits |= chipcHw_REG_STICKY_GENERAL_2;
344 }
345 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
346 && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
347 bits |= chipcHw_REG_STICKY_GENERAL_3;
348 }
349 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
350 && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
351 bits |= chipcHw_REG_STICKY_GENERAL_4;
352 }
353 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
354 && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
355 bits |= chipcHw_REG_STICKY_GENERAL_5;
356 }
357 }
358 pChipcHw->Sticky = bits;
359 REG_LOCAL_IRQ_RESTORE;
360}
361
362/****************************************************************************/
363/**
364* @brief Clear sticky bits
365*
366* @return void
367*
368* @note use chipcHw_REG_STICKY_XXXXXX
369*/
370/****************************************************************************/
371static inline void chipcHw_clearStickyBits(uint32_t mask)
372{
373 uint32_t bits = 0;
374
375 REG_LOCAL_IRQ_SAVE;
376 if (mask &
377 (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
378 chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
379 chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
380 uint32_t sticky = pChipcHw->Sticky;
381
382 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
383 && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
384 bits = chipcHw_REG_STICKY_BOOT_DONE;
385 mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
386 }
387 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
388 && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
389 bits |= chipcHw_REG_STICKY_GENERAL_1;
390 mask &= ~chipcHw_REG_STICKY_GENERAL_1;
391 }
392 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
393 && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
394 bits |= chipcHw_REG_STICKY_GENERAL_2;
395 mask &= ~chipcHw_REG_STICKY_GENERAL_2;
396 }
397 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
398 && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
399 bits |= chipcHw_REG_STICKY_GENERAL_3;
400 mask &= ~chipcHw_REG_STICKY_GENERAL_3;
401 }
402 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
403 && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
404 bits |= chipcHw_REG_STICKY_GENERAL_4;
405 mask &= ~chipcHw_REG_STICKY_GENERAL_4;
406 }
407 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
408 && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
409 bits |= chipcHw_REG_STICKY_GENERAL_5;
410 mask &= ~chipcHw_REG_STICKY_GENERAL_5;
411 }
412 }
413 pChipcHw->Sticky = bits | mask;
414 REG_LOCAL_IRQ_RESTORE;
415}
416
417/****************************************************************************/
418/**
419* @brief Get software strap value
420*
421* Retrieves software strap value
422*
423* @return Software strap value
424*
425*/
426/****************************************************************************/
427static inline uint32_t chipcHw_getSoftStraps(void)
428{
429 return pChipcHw->SoftStraps;
430}
431
432/****************************************************************************/
433/**
434* @brief Set software override strap options
435*
436* set software override strap options
437*
438* @return nothing
439*
440*/
441/****************************************************************************/
442static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
443{
444 reg32_write(&pChipcHw->SoftStraps, strapOptions);
445}
446
447/****************************************************************************/
448/**
449* @brief Get Pin Strap Options
450*
451* This function returns the raw boot strap options
452*
453* @return strap options
454*
455*/
456/****************************************************************************/
457static inline uint32_t chipcHw_getPinStraps(void)
458{
459 return pChipcHw->PinStraps;
460}
461
462/****************************************************************************/
463/**
464* @brief Get Valid Strap Options
465*
466* This function returns the valid raw boot strap options
467*
468* @return strap options
469*
470*/
471/****************************************************************************/
472static inline uint32_t chipcHw_getValidStraps(void)
473{
474 uint32_t softStraps;
475
476 /*
477 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
478 ** which copies HW straps to soft straps if there is no override
479 */
480 softStraps = chipcHw_getSoftStraps();
481
482 return softStraps;
483}
484
485/****************************************************************************/
486/**
487* @brief Initialize valid pin strap options
488*
489* Retrieves valid pin strap options by copying HW strap options to soft register
490* (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
491*
492* @return nothing
493*
494*/
495/****************************************************************************/
496static inline void chipcHw_initValidStraps(void)
497{
498 uint32_t softStraps;
499
500 REG_LOCAL_IRQ_SAVE;
501 softStraps = chipcHw_getSoftStraps();
502
503 if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
504 /* Copy HW straps to software straps */
505 chipcHw_setSoftStraps(chipcHw_getPinStraps());
506 }
507 REG_LOCAL_IRQ_RESTORE;
508}
509
510/****************************************************************************/
511/**
512* @brief Get boot device
513*
514* This function returns the device type used in booting the system
515*
516* @return Boot device of type chipcHw_BOOT_DEVICE
517*
518*/
519/****************************************************************************/
520static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
521{
522 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
523}
524
525/****************************************************************************/
526/**
527* @brief Get boot mode
528*
529* This function returns the way the system was booted
530*
531* @return Boot mode of type chipcHw_BOOT_MODE
532*
533*/
534/****************************************************************************/
535static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
536{
537 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
538}
539
540/****************************************************************************/
541/**
542* @brief Get NAND flash page size
543*
544* This function returns the NAND device page size
545*
546* @return Boot NAND device page size
547*
548*/
549/****************************************************************************/
550static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
551{
552 return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
553}
554
555/****************************************************************************/
556/**
557* @brief Get NAND flash address cycle configuration
558*
559* This function returns the NAND flash address cycle configuration
560*
561* @return 0 = Do not extra address cycle, 1 = Add extra cycle
562*
563*/
564/****************************************************************************/
565static inline int chipcHw_getNandExtraCycle(void)
566{
567 if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
568 return 1;
569 } else {
570 return 0;
571 }
572}
573
574/****************************************************************************/
575/**
576* @brief Activates PIF interface
577*
578* This function activates PIF interface by taking control of LCD pins
579*
580* @note
581* When activated, LCD pins will be defined as follows for PIF operation
582*
583* CLD[17:0] = pif_data[17:0]
584* CLD[23:18] = pif_address[5:0]
585* CLPOWER = pif_wr_str
586* CLCP = pif_rd_str
587* CLAC = pif_hat1
588* CLFP = pif_hrdy1
589* CLLP = pif_hat2
590* GPIO[42] = pif_hrdy2
591*
592* In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
593*
594*/
595/****************************************************************************/
596static inline void chipcHw_activatePifInterface(void)
597{
598 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
599}
600
601/****************************************************************************/
602/**
603* @brief Activates LCD interface
604*
605* This function activates LCD interface
606*
607* @note
608* When activated, LCD pins will be defined as follows
609*
610* CLD[17:0] = LCD data
611* CLD[23:18] = LCD data
612* CLPOWER = LCD power
613* CLCP =
614* CLAC = LCD ack
615* CLFP =
616* CLLP =
617*/
618/****************************************************************************/
619static inline void chipcHw_activateLcdInterface(void)
620{
621 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
622}
623
624/****************************************************************************/
625/**
626* @brief Deactivates PIF/LCD interface
627*
628* This function deactivates PIF/LCD interface
629*
630* @note
631* When deactivated LCD pins will be in rti-stated
632*
633*/
634/****************************************************************************/
635static inline void chipcHw_deactivatePifLcdInterface(void)
636{
637 reg32_write(&pChipcHw->LcdPifMode, 0);
638}
639
640/****************************************************************************/
641/**
642* @brief Select GE2
643*
644* This function select GE2 as the graphic engine
645*
646*/
647/****************************************************************************/
648static inline void chipcHw_selectGE2(void)
649{
650 reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
651}
652
653/****************************************************************************/
654/**
655* @brief Select GE3
656*
657* This function select GE3 as the graphic engine
658*
659*/
660/****************************************************************************/
661static inline void chipcHw_selectGE3(void)
662{
663 reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
664}
665
666/****************************************************************************/
667/**
668* @brief Get to know the configuration of GPIO pin
669*
670*/
671/****************************************************************************/
672static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
673{
674 return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
675 (chipcHw_REG_GPIO_MUX_MASK <<
676 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
677 chipcHw_REG_GPIO_MUX_POSITION(pin);
678}
679
680/****************************************************************************/
681/**
682* @brief Configure GPIO pin function
683*
684*/
685/****************************************************************************/
686static inline void chipcHw_setGpioPinFunction(int pin,
687 chipcHw_GPIO_FUNCTION_e func)
688{
689 REG_LOCAL_IRQ_SAVE;
690 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
691 ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
692 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
693 func << chipcHw_REG_GPIO_MUX_POSITION(pin);
694 REG_LOCAL_IRQ_RESTORE;
695}
696
697/****************************************************************************/
698/**
699* @brief Set Pin slew rate
700*
701* This function sets the slew of individual pin
702*
703*/
704/****************************************************************************/
705static inline void chipcHw_setPinSlewRate(uint32_t pin,
706 chipcHw_PIN_SLEW_RATE_e slewRate)
707{
708 REG_LOCAL_IRQ_SAVE;
709 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
710 ~(chipcHw_REG_SLEW_RATE_MASK <<
711 chipcHw_REG_SLEW_RATE_POSITION(pin));
712 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
713 (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
714 REG_LOCAL_IRQ_RESTORE;
715}
716
717/****************************************************************************/
718/**
719* @brief Set Pin output drive current
720*
721* This function sets output drive current of individual pin
722*
723* Note: Avoid the use of the word 'current' since linux headers define this
724* to be the current task.
725*/
726/****************************************************************************/
727static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
728 chipcHw_PIN_CURRENT_STRENGTH_e
729 curr)
730{
731 REG_LOCAL_IRQ_SAVE;
732 *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
733 ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
734 *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
735 (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
736 REG_LOCAL_IRQ_RESTORE;
737}
738
739/****************************************************************************/
740/**
741* @brief Set Pin pullup register
742*
743* This function sets pullup register of individual pin
744*
745*/
746/****************************************************************************/
747static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
748{
749 REG_LOCAL_IRQ_SAVE;
750 *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
751 ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
752 *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
753 (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
754 REG_LOCAL_IRQ_RESTORE;
755}
756
757/****************************************************************************/
758/**
759* @brief Set Pin input type
760*
761* This function sets input type of individual pin
762*
763*/
764/****************************************************************************/
765static inline void chipcHw_setPinInputType(uint32_t pin,
766 chipcHw_PIN_INPUTTYPE_e inputType)
767{
768 REG_LOCAL_IRQ_SAVE;
769 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
770 ~(chipcHw_REG_INPUTTYPE_MASK <<
771 chipcHw_REG_INPUTTYPE_POSITION(pin));
772 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
773 (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
774 REG_LOCAL_IRQ_RESTORE;
775}
776
777/****************************************************************************/
778/**
779* @brief Power up the USB PHY
780*
781* This function powers up the USB PHY
782*
783*/
784/****************************************************************************/
785static inline void chipcHw_powerUpUsbPhy(void)
786{
787 reg32_modify_and(&pChipcHw->MiscCtrl,
788 chipcHw_REG_MISC_CTRL_USB_POWERON);
789}
790
791/****************************************************************************/
792/**
793* @brief Power down the USB PHY
794*
795* This function powers down the USB PHY
796*
797*/
798/****************************************************************************/
799static inline void chipcHw_powerDownUsbPhy(void)
800{
801 reg32_modify_or(&pChipcHw->MiscCtrl,
802 chipcHw_REG_MISC_CTRL_USB_POWEROFF);
803}
804
805/****************************************************************************/
806/**
807* @brief Set the 2nd USB as host
808*
809* This function sets the 2nd USB as host
810*
811*/
812/****************************************************************************/
813static inline void chipcHw_setUsbHost(void)
814{
815 reg32_modify_or(&pChipcHw->MiscCtrl,
816 chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
817}
818
819/****************************************************************************/
820/**
821* @brief Set the 2nd USB as device
822*
823* This function sets the 2nd USB as device
824*
825*/
826/****************************************************************************/
827static inline void chipcHw_setUsbDevice(void)
828{
829 reg32_modify_and(&pChipcHw->MiscCtrl,
830 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
831}
832
833/****************************************************************************/
834/**
835* @brief Lower layer function to enable/disable a clock of a certain device
836*
837* This function enables/disables a core clock
838*
839*/
840/****************************************************************************/
841static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
842 chipcHw_OPTYPE_e type, int mode)
843{
844 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
845 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
846
847 switch (clock) {
848 case chipcHw_CLOCK_DDR:
849 pPLLReg = &pChipcHw->DDRClock;
850 break;
851 case chipcHw_CLOCK_ARM:
852 pPLLReg = &pChipcHw->ARMClock;
853 break;
854 case chipcHw_CLOCK_ESW:
855 pPLLReg = &pChipcHw->ESWClock;
856 break;
857 case chipcHw_CLOCK_VPM:
858 pPLLReg = &pChipcHw->VPMClock;
859 break;
860 case chipcHw_CLOCK_ESW125:
861 pPLLReg = &pChipcHw->ESW125Clock;
862 break;
863 case chipcHw_CLOCK_UART:
864 pPLLReg = &pChipcHw->UARTClock;
865 break;
866 case chipcHw_CLOCK_SDIO0:
867 pPLLReg = &pChipcHw->SDIO0Clock;
868 break;
869 case chipcHw_CLOCK_SDIO1:
870 pPLLReg = &pChipcHw->SDIO1Clock;
871 break;
872 case chipcHw_CLOCK_SPI:
873 pPLLReg = &pChipcHw->SPIClock;
874 break;
875 case chipcHw_CLOCK_ETM:
876 pPLLReg = &pChipcHw->ETMClock;
877 break;
878 case chipcHw_CLOCK_USB:
879 pPLLReg = &pChipcHw->USBClock;
880 if (type == chipcHw_OPTYPE_OUTPUT) {
881 if (mode) {
882 reg32_modify_and(pPLLReg,
883 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
884 } else {
885 reg32_modify_or(pPLLReg,
886 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
887 }
888 }
889 break;
890 case chipcHw_CLOCK_LCD:
891 pPLLReg = &pChipcHw->LCDClock;
892 if (type == chipcHw_OPTYPE_OUTPUT) {
893 if (mode) {
894 reg32_modify_and(pPLLReg,
895 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
896 } else {
897 reg32_modify_or(pPLLReg,
898 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
899 }
900 }
901 break;
902 case chipcHw_CLOCK_APM:
903 pPLLReg = &pChipcHw->APMClock;
904 if (type == chipcHw_OPTYPE_OUTPUT) {
905 if (mode) {
906 reg32_modify_and(pPLLReg,
907 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
908 } else {
909 reg32_modify_or(pPLLReg,
910 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
911 }
912 }
913 break;
914 case chipcHw_CLOCK_BUS:
915 pClockCtrl = &pChipcHw->ACLKClock;
916 break;
917 case chipcHw_CLOCK_OTP:
918 pClockCtrl = &pChipcHw->OTPClock;
919 break;
920 case chipcHw_CLOCK_I2C:
921 pClockCtrl = &pChipcHw->I2CClock;
922 break;
923 case chipcHw_CLOCK_I2S0:
924 pClockCtrl = &pChipcHw->I2S0Clock;
925 break;
926 case chipcHw_CLOCK_RTBUS:
927 pClockCtrl = &pChipcHw->RTBUSClock;
928 break;
929 case chipcHw_CLOCK_APM100:
930 pClockCtrl = &pChipcHw->APM100Clock;
931 break;
932 case chipcHw_CLOCK_TSC:
933 pClockCtrl = &pChipcHw->TSCClock;
934 break;
935 case chipcHw_CLOCK_LED:
936 pClockCtrl = &pChipcHw->LEDClock;
937 break;
938 case chipcHw_CLOCK_I2S1:
939 pClockCtrl = &pChipcHw->I2S1Clock;
940 break;
941 }
942
943 if (pPLLReg) {
944 switch (type) {
945 case chipcHw_OPTYPE_OUTPUT:
946 /* PLL clock output enable/disable */
947 if (mode) {
948 if (clock == chipcHw_CLOCK_DDR) {
949 /* DDR clock enable is inverted */
950 reg32_modify_and(pPLLReg,
951 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
952 } else {
953 reg32_modify_or(pPLLReg,
954 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
955 }
956 } else {
957 if (clock == chipcHw_CLOCK_DDR) {
958 /* DDR clock disable is inverted */
959 reg32_modify_or(pPLLReg,
960 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
961 } else {
962 reg32_modify_and(pPLLReg,
963 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
964 }
965 }
966 break;
967 case chipcHw_OPTYPE_BYPASS:
968 /* PLL clock bypass enable/disable */
969 if (mode) {
970 reg32_modify_or(pPLLReg,
971 chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
972 } else {
973 reg32_modify_and(pPLLReg,
974 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
975 }
976 break;
977 }
978 } else if (pClockCtrl) {
979 switch (type) {
980 case chipcHw_OPTYPE_OUTPUT:
981 if (mode) {
982 reg32_modify_or(pClockCtrl,
983 chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
984 } else {
985 reg32_modify_and(pClockCtrl,
986 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
987 }
988 break;
989 case chipcHw_OPTYPE_BYPASS:
990 if (mode) {
991 reg32_modify_or(pClockCtrl,
992 chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
993 } else {
994 reg32_modify_and(pClockCtrl,
995 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
996 }
997 break;
998 }
999 }
1000}
1001
1002/****************************************************************************/
1003/**
1004* @brief Disables a core clock of a certain device
1005*
1006* This function disables a core clock
1007*
1008* @note no change in power consumption
1009*/
1010/****************************************************************************/
1011static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
1012{
1013
1014 /* Disable output of the clock */
1015 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
1016}
1017
1018/****************************************************************************/
1019/**
1020* @brief Enable a core clock of a certain device
1021*
1022* This function enables a core clock
1023*
1024* @note no change in power consumption
1025*/
1026/****************************************************************************/
1027static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
1028{
1029
1030 /* Enable output of the clock */
1031 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
1032}
1033
1034/****************************************************************************/
1035/**
1036* @brief Enables bypass clock of a certain device
1037*
1038* This function enables bypass clock
1039*
1040* @note Doesnot affect the bus interface clock
1041*/
1042/****************************************************************************/
1043static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
1044{
1045 /* Enable bypass clock */
1046 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
1047}
1048
1049/****************************************************************************/
1050/**
1051* @brief Disabled bypass clock of a certain device
1052*
1053* This function disables bypass clock
1054*
1055* @note Doesnot affect the bus interface clock
1056*/
1057/****************************************************************************/
1058static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
1059{
1060 /* Disable bypass clock */
1061 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
1062
1063}
1064
1065/****************************************************************************/
1066/** @brief Checks if software strap is enabled
1067 *
1068 * @return 1 : When enable
1069 * 0 : When disable
1070 */
1071/****************************************************************************/
1072static inline int chipcHw_isSoftwareStrapsEnable(void)
1073{
1074 return pChipcHw->SoftStraps & 0x00000001;
1075}
1076
1077/****************************************************************************/
1078/** @brief Enable software strap
1079 */
1080/****************************************************************************/
1081static inline void chipcHw_softwareStrapsEnable(void)
1082{
1083 reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
1084}
1085
1086/****************************************************************************/
1087/** @brief Disable software strap
1088 */
1089/****************************************************************************/
1090static inline void chipcHw_softwareStrapsDisable(void)
1091{
1092 reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
1093}
1094
1095/****************************************************************************/
1096/** @brief PLL test enable
1097 */
1098/****************************************************************************/
1099static inline void chipcHw_pllTestEnable(void)
1100{
1101 reg32_modify_or(&pChipcHw->PLLConfig,
1102 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1103}
1104
1105/****************************************************************************/
1106/** @brief PLL2 test enable
1107 */
1108/****************************************************************************/
1109static inline void chipcHw_pll2TestEnable(void)
1110{
1111 reg32_modify_or(&pChipcHw->PLLConfig2,
1112 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1113}
1114
1115/****************************************************************************/
1116/** @brief PLL test disable
1117 */
1118/****************************************************************************/
1119static inline void chipcHw_pllTestDisable(void)
1120{
1121 reg32_modify_and(&pChipcHw->PLLConfig,
1122 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1123}
1124
1125/****************************************************************************/
1126/** @brief PLL2 test disable
1127 */
1128/****************************************************************************/
1129static inline void chipcHw_pll2TestDisable(void)
1130{
1131 reg32_modify_and(&pChipcHw->PLLConfig2,
1132 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1133}
1134
1135/****************************************************************************/
1136/** @brief Get PLL test status
1137 */
1138/****************************************************************************/
1139static inline int chipcHw_isPllTestEnable(void)
1140{
1141 return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1142}
1143
1144/****************************************************************************/
1145/** @brief Get PLL2 test status
1146 */
1147/****************************************************************************/
1148static inline int chipcHw_isPll2TestEnable(void)
1149{
1150 return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1151}
1152
1153/****************************************************************************/
1154/** @brief PLL test select
1155 */
1156/****************************************************************************/
1157static inline void chipcHw_pllTestSelect(uint32_t val)
1158{
1159 REG_LOCAL_IRQ_SAVE;
1160 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1161 pChipcHw->PLLConfig |=
1162 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1163 REG_LOCAL_IRQ_RESTORE;
1164}
1165
1166/****************************************************************************/
1167/** @brief PLL2 test select
1168 */
1169/****************************************************************************/
1170static inline void chipcHw_pll2TestSelect(uint32_t val)
1171{
1172
1173 REG_LOCAL_IRQ_SAVE;
1174 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1175 pChipcHw->PLLConfig2 |=
1176 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1177 REG_LOCAL_IRQ_RESTORE;
1178}
1179
1180/****************************************************************************/
1181/** @brief Get PLL test selected option
1182 */
1183/****************************************************************************/
1184static inline uint8_t chipcHw_getPllTestSelected(void)
1185{
1186 return (uint8_t) ((pChipcHw->
1187 PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1188 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1189}
1190
1191/****************************************************************************/
1192/** @brief Get PLL2 test selected option
1193 */
1194/****************************************************************************/
1195static inline uint8_t chipcHw_getPll2TestSelected(void)
1196{
1197 return (uint8_t) ((pChipcHw->
1198 PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1199 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1200}
1201
1202/****************************************************************************/
1203/**
1204* @brief Disable the PLL1
1205*
1206*/
1207/****************************************************************************/
1208static inline void chipcHw_pll1Disable(void)
1209{
1210 REG_LOCAL_IRQ_SAVE;
1211 pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1212 REG_LOCAL_IRQ_RESTORE;
1213}
1214
1215/****************************************************************************/
1216/**
1217* @brief Disable the PLL2
1218*
1219*/
1220/****************************************************************************/
1221static inline void chipcHw_pll2Disable(void)
1222{
1223 REG_LOCAL_IRQ_SAVE;
1224 pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1225 REG_LOCAL_IRQ_RESTORE;
1226}
1227
1228/****************************************************************************/
1229/**
1230* @brief Enables DDR SW phase alignment interrupt
1231*/
1232/****************************************************************************/
1233static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1234{
1235 REG_LOCAL_IRQ_SAVE;
1236 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1237 REG_LOCAL_IRQ_RESTORE;
1238}
1239
1240/****************************************************************************/
1241/**
1242* @brief Disables DDR SW phase alignment interrupt
1243*/
1244/****************************************************************************/
1245static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
1246{
1247 REG_LOCAL_IRQ_SAVE;
1248 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1249 REG_LOCAL_IRQ_RESTORE;
1250}
1251
1252/****************************************************************************/
1253/**
1254* @brief Set VPM SW phase alignment interrupt mode
1255*
1256* This function sets VPM phase alignment interrupt
1257*/
1258/****************************************************************************/
1259static inline void
1260chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
1261{
1262 REG_LOCAL_IRQ_SAVE;
1263 if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
1264 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1265 } else {
1266 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1267 }
1268 pChipcHw->VPMPhaseCtrl2 =
1269 (pChipcHw->
1270 VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
1271 chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
1272 REG_LOCAL_IRQ_RESTORE;
1273}
1274
1275/****************************************************************************/
1276/**
1277* @brief Enable DDR phase alignment in software
1278*
1279*/
1280/****************************************************************************/
1281static inline void chipcHw_ddrSwPhaseAlignEnable(void)
1282{
1283 REG_LOCAL_IRQ_SAVE;
1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1285 REG_LOCAL_IRQ_RESTORE;
1286}
1287
1288/****************************************************************************/
1289/**
1290* @brief Disable DDR phase alignment in software
1291*
1292*/
1293/****************************************************************************/
1294static inline void chipcHw_ddrSwPhaseAlignDisable(void)
1295{
1296 REG_LOCAL_IRQ_SAVE;
1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1298 REG_LOCAL_IRQ_RESTORE;
1299}
1300
1301/****************************************************************************/
1302/**
1303* @brief Enable DDR phase alignment in hardware
1304*
1305*/
1306/****************************************************************************/
1307static inline void chipcHw_ddrHwPhaseAlignEnable(void)
1308{
1309 REG_LOCAL_IRQ_SAVE;
1310 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1311 REG_LOCAL_IRQ_RESTORE;
1312}
1313
1314/****************************************************************************/
1315/**
1316* @brief Disable DDR phase alignment in hardware
1317*
1318*/
1319/****************************************************************************/
1320static inline void chipcHw_ddrHwPhaseAlignDisable(void)
1321{
1322 REG_LOCAL_IRQ_SAVE;
1323 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1324 REG_LOCAL_IRQ_RESTORE;
1325}
1326
1327/****************************************************************************/
1328/**
1329* @brief Enable VPM phase alignment in software
1330*
1331*/
1332/****************************************************************************/
1333static inline void chipcHw_vpmSwPhaseAlignEnable(void)
1334{
1335 REG_LOCAL_IRQ_SAVE;
1336 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1337 REG_LOCAL_IRQ_RESTORE;
1338}
1339
1340/****************************************************************************/
1341/**
1342* @brief Disable VPM phase alignment in software
1343*
1344*/
1345/****************************************************************************/
1346static inline void chipcHw_vpmSwPhaseAlignDisable(void)
1347{
1348 REG_LOCAL_IRQ_SAVE;
1349 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1350 REG_LOCAL_IRQ_RESTORE;
1351}
1352
1353/****************************************************************************/
1354/**
1355* @brief Enable VPM phase alignment in hardware
1356*
1357*/
1358/****************************************************************************/
1359static inline void chipcHw_vpmHwPhaseAlignEnable(void)
1360{
1361 REG_LOCAL_IRQ_SAVE;
1362 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1363 REG_LOCAL_IRQ_RESTORE;
1364}
1365
1366/****************************************************************************/
1367/**
1368* @brief Disable VPM phase alignment in hardware
1369*
1370*/
1371/****************************************************************************/
1372static inline void chipcHw_vpmHwPhaseAlignDisable(void)
1373{
1374 REG_LOCAL_IRQ_SAVE;
1375 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1376 REG_LOCAL_IRQ_RESTORE;
1377}
1378
1379/****************************************************************************/
1380/**
1381* @brief Set DDR phase alignment margin in hardware
1382*
1383*/
1384/****************************************************************************/
1385static inline void
1386chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
1387{
1388 uint32_t ge = 0;
1389 uint32_t le = 0;
1390
1391 switch (margin) {
1392 case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
1393 ge = 0x0F;
1394 le = 0x0F;
1395 break;
1396 case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
1397 ge = 0x03;
1398 le = 0x3F;
1399 break;
1400 case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
1401 ge = 0x01;
1402 le = 0x7F;
1403 break;
1404 }
1405
1406 {
1407 REG_LOCAL_IRQ_SAVE;
1408
1409 pChipcHw->DDRPhaseCtrl1 &=
1410 ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
1411 chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1412 || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
1413 chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1414
1415 pChipcHw->DDRPhaseCtrl1 |=
1416 ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1417 || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1418
1419 REG_LOCAL_IRQ_RESTORE;
1420 }
1421}
1422
1423/****************************************************************************/
1424/**
1425* @brief Set VPM phase alignment margin in hardware
1426*
1427*/
1428/****************************************************************************/
1429static inline void
1430chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
1431{
1432 uint32_t ge = 0;
1433 uint32_t le = 0;
1434
1435 switch (margin) {
1436 case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
1437 ge = 0x0F;
1438 le = 0x0F;
1439 break;
1440 case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
1441 ge = 0x03;
1442 le = 0x3F;
1443 break;
1444 case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
1445 ge = 0x01;
1446 le = 0x7F;
1447 break;
1448 }
1449
1450 {
1451 REG_LOCAL_IRQ_SAVE;
1452
1453 pChipcHw->VPMPhaseCtrl1 &=
1454 ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
1455 chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1456 || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
1457 chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1458
1459 pChipcHw->VPMPhaseCtrl1 |=
1460 ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1461 || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1462
1463 REG_LOCAL_IRQ_RESTORE;
1464 }
1465}
1466
1467/****************************************************************************/
1468/**
1469* @brief Checks DDR phase aligned status done by HW
1470*
1471* @return 1: When aligned
1472* 0: When not aligned
1473*/
1474/****************************************************************************/
1475static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1476{
1477 return (pChipcHw->
1478 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
1479}
1480
1481/****************************************************************************/
1482/**
1483* @brief Checks VPM phase aligned status done by HW
1484*
1485* @return 1: When aligned
1486* 0: When not aligned
1487*/
1488/****************************************************************************/
1489static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1490{
1491 return (pChipcHw->
1492 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
1493}
1494
1495/****************************************************************************/
1496/**
1497* @brief Get DDR phase aligned status done by HW
1498*
1499*/
1500/****************************************************************************/
1501static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1502{
1503 return (pChipcHw->
1504 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
1505 chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
1506}
1507
1508/****************************************************************************/
1509/**
1510* @brief Get VPM phase aligned status done by HW
1511*
1512*/
1513/****************************************************************************/
1514static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1515{
1516 return (pChipcHw->
1517 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
1518 chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
1519}
1520
1521/****************************************************************************/
1522/**
1523* @brief Get DDR phase control value
1524*
1525*/
1526/****************************************************************************/
1527static inline uint32_t chipcHw_getDdrPhaseControl(void)
1528{
1529 return (pChipcHw->
1530 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
1531 chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
1532}
1533
1534/****************************************************************************/
1535/**
1536* @brief Get VPM phase control value
1537*
1538*/
1539/****************************************************************************/
1540static inline uint32_t chipcHw_getVpmPhaseControl(void)
1541{
1542 return (pChipcHw->
1543 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
1544 chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
1545}
1546
1547/****************************************************************************/
1548/**
1549* @brief DDR phase alignment timeout count
1550*
1551* @note If HW fails to perform the phase alignment, it will trigger
1552* a DDR phase alignment timeout interrupt.
1553*/
1554/****************************************************************************/
1555static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
1556{
1557 REG_LOCAL_IRQ_SAVE;
1558 pChipcHw->DDRPhaseCtrl2 &=
1559 ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
1560 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
1561 pChipcHw->DDRPhaseCtrl2 |=
1562 (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
1563 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
1564 REG_LOCAL_IRQ_RESTORE;
1565}
1566
1567/****************************************************************************/
1568/**
1569* @brief VPM phase alignment timeout count
1570*
1571* @note If HW fails to perform the phase alignment, it will trigger
1572* a VPM phase alignment timeout interrupt.
1573*/
1574/****************************************************************************/
1575static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
1576{
1577 REG_LOCAL_IRQ_SAVE;
1578 pChipcHw->VPMPhaseCtrl2 &=
1579 ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
1580 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
1581 pChipcHw->VPMPhaseCtrl2 |=
1582 (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
1583 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
1584 REG_LOCAL_IRQ_RESTORE;
1585}
1586
1587/****************************************************************************/
1588/**
1589* @brief Clear DDR phase alignment timeout interrupt
1590*
1591*/
1592/****************************************************************************/
1593static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
1594{
1595 REG_LOCAL_IRQ_SAVE;
1596 /* Clear timeout interrupt service bit */
1597 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
1598 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
1599 REG_LOCAL_IRQ_RESTORE;
1600}
1601
1602/****************************************************************************/
1603/**
1604* @brief Clear VPM phase alignment timeout interrupt
1605*
1606*/
1607/****************************************************************************/
1608static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
1609{
1610 REG_LOCAL_IRQ_SAVE;
1611 /* Clear timeout interrupt service bit */
1612 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
1613 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
1614 REG_LOCAL_IRQ_RESTORE;
1615}
1616
1617/****************************************************************************/
1618/**
1619* @brief DDR phase alignment timeout interrupt enable
1620*
1621*/
1622/****************************************************************************/
1623static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
1624{
1625 REG_LOCAL_IRQ_SAVE;
1626 chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1627 /* Enable timeout interrupt */
1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1629 REG_LOCAL_IRQ_RESTORE;
1630}
1631
1632/****************************************************************************/
1633/**
1634* @brief VPM phase alignment timeout interrupt enable
1635*
1636*/
1637/****************************************************************************/
1638static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
1639{
1640 REG_LOCAL_IRQ_SAVE;
1641 chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1642 /* Enable timeout interrupt */
1643 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1644 REG_LOCAL_IRQ_RESTORE;
1645}
1646
1647/****************************************************************************/
1648/**
1649* @brief DDR phase alignment timeout interrupt disable
1650*
1651*/
1652/****************************************************************************/
1653static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
1654{
1655 REG_LOCAL_IRQ_SAVE;
1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1657 REG_LOCAL_IRQ_RESTORE;
1658}
1659
1660/****************************************************************************/
1661/**
1662* @brief VPM phase alignment timeout interrupt disable
1663*
1664*/
1665/****************************************************************************/
1666static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
1667{
1668 REG_LOCAL_IRQ_SAVE;
1669 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1670 REG_LOCAL_IRQ_RESTORE;
1671}
1672
1673#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
new file mode 100644
index 00000000000..b162448f613
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -0,0 +1,530 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file chipcHw_reg.h
18*
19* @brief Definitions for low level chip control registers
20*
21*/
22/****************************************************************************/
23#ifndef CHIPCHW_REG_H
24#define CHIPCHW_REG_H
25
26#include <mach/csp/mm_io.h>
27#include <csp/reg.h>
28#include <mach/csp/ddrcReg.h>
29
30#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC
31
32typedef struct {
33 uint32_t ChipId; /* Chip ID */
34 uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */
35 uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */
36 uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */
37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */
38 uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */
39 uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */
40 uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */
41 uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */
42 uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */
43 uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */
44
45 uint32_t ACLKClock; /* ACLK Clock (Divider) */
46 uint32_t OTPClock; /* OTP Clock (Divider) */
47 uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */
48 uint32_t I2S0Clock; /* I2S0 Clock (Divider) */
49 uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */
50 uint32_t pad1;
51 uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */
52 uint32_t TSCClock; /* TSC Clock (Divider) */
53 uint32_t LEDClock; /* LED Clock (Divider) */
54
55 uint32_t USBClock; /* PLL2 Channel 1 for USB clock */
56 uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */
57 uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */
58
59 uint32_t BusIntfClock; /* Bus interface clock */
60
61 uint32_t PLLStatus; /* PLL status register (PLL1) */
62 uint32_t PLLConfig; /* PLL configuration register (PLL1) */
63 uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
64 uint32_t PLLDivider; /* PLL divider control register (PLL1) */
65 uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */
66 uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */
67
68 uint32_t I2S1Clock; /* I2S1 Clock */
69 uint32_t AudioEnable; /* Enable/ disable audio channel */
70 uint32_t SoftReset1; /* Reset blocks */
71 uint32_t SoftReset2; /* Reset blocks */
72 uint32_t Spare1; /* Phase align interrupts */
73 uint32_t Sticky; /* Sticky bits */
74 uint32_t MiscCtrl; /* Misc. control */
75 uint32_t pad3[3];
76
77 uint32_t PLLStatus2; /* PLL status register (PLL2) */
78 uint32_t PLLConfig2; /* PLL configuration register (PLL2) */
79 uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */
80 uint32_t PLLDivider2; /* PLL divider control register (PLL2) */
81 uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */
82 uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */
83
84 uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
85 uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
86 uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */
87 uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
88 uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
89 uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
90 uint32_t pad4[9];
91
92 uint32_t SoftOTP1; /* Software OTP control */
93 uint32_t SoftOTP2; /* Software OTP control */
94 uint32_t SoftStraps; /* Software strap */
95 uint32_t PinStraps; /* Pin Straps */
96 uint32_t DiffOscCtrl; /* Diff oscillator control */
97 uint32_t DiagsCtrl; /* Diagnostic control */
98 uint32_t DiagsOutputCtrl; /* Diagnostic output enable */
99 uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */
100
101 uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */
102
103 uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */
104 uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */
105 uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
106 uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
107 uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
108 uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
109 uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
110 uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
111
112 uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */
113 uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */
114 uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */
115 uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */
116 uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */
117 uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */
118 uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */
119 uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */
120 uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */
121 uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */
122
123 uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
124 uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */
125 uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */
126 uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */
127 uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
128
129 uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */
130 uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */
131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
132} chipcHw_REG_t;
133
134#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
135#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
136
137#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
138#define chipcHw_REG_CHIPID_BASE_SHIFT 12
139#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF
140#define chipcHw_REG_REV_A0 0xA00
141#define chipcHw_REG_REV_B0 0x0B0
142
143#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */
144#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */
145#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */
146#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */
147#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */
148#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */
149#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */
150#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */
151#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */
152#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */
153#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */
154#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */
155#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17
156
157#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */
158#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */
159#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */
160#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */
161#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */
162#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */
163#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */
164#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */
165#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */
166#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */
167#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask
168
169 00000000 = divide-by-256
170 00000001 = divide-by-1
171 00000010 = divide-by-2
172 00000011 = divide-by-3
173 00000100 = divide-by-4
174 00000101 = divide-by-5
175 00000110 = divide-by-6
176 .
177 .
178 11111011 = divide-by-251
179 11111100 = divide-by-252
180 11111101 = divide-by-253
181 11111110 = divide-by-254
182 */
183
184#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */
185#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */
186#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */
187#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */
188#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */
189
190#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0
191#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4
192#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8
193#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00
194#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000
195#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */
196#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */
197#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */
198#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */
199#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */
200#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */
201
202#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz)
203#define chipcHw_REG_PLL_PREDIVIDER_P1 1
204#define chipcHw_REG_PLL_PREDIVIDER_P2 1
205
206#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000
207#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */
208
209#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */
210
211#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
212 chipcHw_REG_PLL_DIVIDER_FRAC
213 = 0, when SS is disable
214 */
215
216#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
217
218#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3
219
220/* System booting strap options */
221#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */
222
223#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */
224#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */
225#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */
226#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */
227#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */
228#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */
229
230/* System boot option */
231#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */
232#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */
233#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */
234
235/* NAND Flash page size strap options */
236#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */
237#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */
238#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */
239#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */
240#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */
241
242#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */
243#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */
244
245/* Secure boot mode strap options */
246#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */
247#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */
248#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */
249#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */
250#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */
251
252/* Slave Mode straps */
253#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */
254#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */
255
256/* Strap pin options */
257#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
258
259/* PIF/LCD pin sharing defines */
260#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */
261#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */
262
263#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */
264
265/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
266#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */
267#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */
268#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */
269#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */
270#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */
271#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */
272#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */
273#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */
274#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */
275#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */
276#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */
277#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */
278#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */
279#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */
280#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
281#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2)
282#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */
283
284#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */
285#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */
286 /* Pins beyond 42 are defined by skipping 8 bits within the register */
287#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
288#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
289#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */
290
291#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */
292#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */
293#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */
294#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */
295#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */
296#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */
297#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */
298 /* Pins beyond 42 are defined by skipping 8 bits */
299#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
300#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
301
302#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */
303#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */
304#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */
305#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */
306 /* Pins beyond 42 are defined by skipping 4 bits */
307#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
308#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
309
310#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */
311#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */
312#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */
313 /* Pins beyond 42 are defined by skipping 2 bits */
314#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
315#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
316
317/* Device connected to the bus clock */
318#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */
319#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */
320#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */
321#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */
322#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */
323#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */
324#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */
325#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */
326#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */
327#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */
328#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */
329#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */
330#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */
331#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */
332#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */
333#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */
334#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */
335#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */
336#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */
337#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */
338#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */
339#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */
340#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */
341#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */
342#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */
343#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */
344#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */
345#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */
346#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */
347#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */
348#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */
349#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */
350
351/* Software resets defines */
352#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */
353#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */
354#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */
355#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */
356#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */
357#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */
358#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */
359#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */
360#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */
361#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */
362#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */
363#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */
364#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */
365#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */
366#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */
367#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */
368#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */
369#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */
370#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */
371#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */
372#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */
373#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */
374#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */
375#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */
376#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */
377#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */
378#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */
379#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */
380#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */
381#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */
382#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */
383#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */
384#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */
385#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */
386#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */
387#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */
388#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */
389#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */
390#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */
391#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */
392#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */
393#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */
394#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */
395#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */
396#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */
397
398#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */
399#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */
400#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */
401#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */
402
403/* Audio channel control defines */
404#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */
405#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */
406#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */
407#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */
408#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */
409#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */
410#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */
411#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */
412
413/* Misc. chip control defines */
414#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */
415#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */
416#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */
417#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */
418#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */
419#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */
420#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */
421#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */
422#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */
423#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */
424#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */
425#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */
426
427/* OTP configuration defines */
428#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */
429#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */
430#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */
431#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */
432#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */
433#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */
434#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */
435#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */
436#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */
437#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */
438#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */
439#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */
440#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */
441#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */
442#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */
443#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */
444#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */
445#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */
446#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */
447#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */
448#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */
449#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */
450#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */
451
452/* Sticky bit defines */
453#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */
454#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */
455#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */
456#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */
457#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */
458#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */
459#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */
460#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */
461#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */
462#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */
463#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */
464#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */
465#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */
466
467 /* HW phase alignment defines *//* Spare1 register definitions */
468#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */
469#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */
470#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */
471#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */
472 /* DDRPhaseCtrl1 register definitions */
473#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */
474#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */
475#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */
476#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23
477#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */
478#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16
479#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */
480#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
481 /* VPMPhaseCtrl1 register definitions */
482#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */
483#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */
484#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */
485#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23
486#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */
487#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16
488#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */
489#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0
490 /* PhaseAlignStatus register definitions */
491#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */
492#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */
493#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24
494#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */
495#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */
496#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */
497#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16
498#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */
499#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */
500#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8
501#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */
502#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */
503#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */
504#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0
505 /* DDRPhaseCtrl2 register definitions */
506#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
507#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
508#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
509#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20
510#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */
511#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
512#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */
513#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0
514 /* VPMPhaseCtrl2 register definitions */
515#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */
516#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26
517#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000
518#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
519#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
520#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
521#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */
522#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */
523#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */
524#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20
525#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */
526#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16
527#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */
528#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0
529
530#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
new file mode 100644
index 00000000000..f1b68e26fa6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -0,0 +1,872 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file ddrcReg.h
18*
19* @brief Register definitions for BCMRING DDR2 Controller and PHY
20*
21*/
22/****************************************************************************/
23
24#ifndef DDRC_REG_H
25#define DDRC_REG_H
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/* ---- Include Files ---------------------------------------------------- */
32
33#include <csp/reg.h>
34#include <csp/stdint.h>
35
36#include <mach/csp/mm_io.h>
37
38/* ---- Public Constants and Types --------------------------------------- */
39
40/*********************************************************************/
41/* DDR2 Controller (ARM PL341) register definitions */
42/*********************************************************************/
43
44/* -------------------------------------------------------------------- */
45/* -------------------------------------------------------------------- */
46/* ARM PL341 DDR2 configuration registers, offset 0x000 */
47/* -------------------------------------------------------------------- */
48/* -------------------------------------------------------------------- */
49
50 typedef struct {
51 uint32_t memcStatus;
52 uint32_t memcCmd;
53 uint32_t directCmd;
54 uint32_t memoryCfg;
55 uint32_t refreshPrd;
56 uint32_t casLatency;
57 uint32_t writeLatency;
58 uint32_t tMrd;
59 uint32_t tRas;
60 uint32_t tRc;
61 uint32_t tRcd;
62 uint32_t tRfc;
63 uint32_t tRp;
64 uint32_t tRrd;
65 uint32_t tWr;
66 uint32_t tWtr;
67 uint32_t tXp;
68 uint32_t tXsr;
69 uint32_t tEsr;
70 uint32_t memoryCfg2;
71 uint32_t memoryCfg3;
72 uint32_t tFaw;
73 } ddrcReg_CTLR_MEMC_REG_t;
74
75#define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000
76#define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
77
78/* ----------------------------------------------------- */
79
80#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12)
81#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12)
82#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12)
83
84#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10)
85#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10)
86#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10)
87#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10)
88#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10)
89
90#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7)
91#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7)
92#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7)
93#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7)
94#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7)
95
96#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4)
97#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4)
98
99#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2)
100#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2)
101#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2)
102#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2)
103#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2)
104
105#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0)
106#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0)
107#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0)
108#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0)
109#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0)
110
111/* ----------------------------------------------------- */
112
113#define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0)
114#define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0)
115#define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0)
116#define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0)
117#define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0)
118#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0)
119#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0)
120
121/* ----------------------------------------------------- */
122
123#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20
124#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
125
126#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18)
127#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18)
128#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18)
129#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18)
130
131#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16
132#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
133
134#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0
135#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
136
137/* ----------------------------------------------------- */
138
139#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21)
140#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21)
141#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21)
142#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21)
143#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21)
144
145#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18)
146#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18)
147#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18)
148#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18)
149#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18)
150#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18)
151#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18)
152#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18)
153#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18)
154
155#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15)
156#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15)
157#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */
158
159#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13)
160
161#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7
162#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
163
164#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3)
165#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3)
166#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3)
167#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3)
168#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3)
169#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3)
170#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3)
171
172#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0)
173#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0)
174#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0)
175#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0)
176
177/* ----------------------------------------------------- */
178
179#define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0
180#define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
181
182/* ----------------------------------------------------- */
183
184#define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1
185#define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
186
187/* ----------------------------------------------------- */
188
189#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0
190#define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
191
192/* ----------------------------------------------------- */
193
194#define ddrcReg_CTLR_T_MRD_SHIFT 0
195#define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
196
197/* ----------------------------------------------------- */
198
199#define ddrcReg_CTLR_T_RAS_SHIFT 0
200#define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
201
202/* ----------------------------------------------------- */
203
204#define ddrcReg_CTLR_T_RC_SHIFT 0
205#define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
206
207/* ----------------------------------------------------- */
208
209#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8
210#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
211
212#define ddrcReg_CTLR_T_RCD_SHIFT 0
213#define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
214
215/* ----------------------------------------------------- */
216
217#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8
218#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
219
220#define ddrcReg_CTLR_T_RFC_SHIFT 0
221#define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
222
223/* ----------------------------------------------------- */
224
225#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8
226#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
227
228#define ddrcReg_CTLR_T_RP_SHIFT 0
229#define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT)
230
231/* ----------------------------------------------------- */
232
233#define ddrcReg_CTLR_T_RRD_SHIFT 0
234#define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
235
236/* ----------------------------------------------------- */
237
238#define ddrcReg_CTLR_T_WR_SHIFT 0
239#define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
240
241/* ----------------------------------------------------- */
242
243#define ddrcReg_CTLR_T_WTR_SHIFT 0
244#define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
245
246/* ----------------------------------------------------- */
247
248#define ddrcReg_CTLR_T_XP_SHIFT 0
249#define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT)
250
251/* ----------------------------------------------------- */
252
253#define ddrcReg_CTLR_T_XSR_SHIFT 0
254#define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
255
256/* ----------------------------------------------------- */
257
258#define ddrcReg_CTLR_T_ESR_SHIFT 0
259#define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
260
261/* ----------------------------------------------------- */
262
263#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6)
264#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6)
265#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6)
266#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6)
267
268#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4)
269#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4)
270#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4)
271
272#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3)
273#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3)
274
275#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2)
276#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2)
277
278#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0)
279#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0)
280#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0)
281#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0)
282
283/* ----------------------------------------------------- */
284
285#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0
286#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
287
288/* ----------------------------------------------------- */
289
290#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8
291#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
292
293#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0
294#define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
295
296/* -------------------------------------------------------------------- */
297/* -------------------------------------------------------------------- */
298/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
299/* -------------------------------------------------------------------- */
300/* -------------------------------------------------------------------- */
301
302#define ddrcReg_CTLR_QOS_CNT 16
303#define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1)
304
305 typedef struct {
306 uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
307 } ddrcReg_CTLR_QOS_REG_t;
308
309#define ddrcReg_CTLR_QOS_REG_OFFSET 0x100
310#define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
311
312/* ----------------------------------------------------- */
313
314#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2
315#define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
316
317#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1
318#define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
319
320#define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0)
321
322/* -------------------------------------------------------------------- */
323/* -------------------------------------------------------------------- */
324/* ARM PL341 Memory chip configuration registers, offset 0x200 */
325/* -------------------------------------------------------------------- */
326/* -------------------------------------------------------------------- */
327
328#define ddrcReg_CTLR_CHIP_CNT 4
329#define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1)
330
331 typedef struct {
332 uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
333 } ddrcReg_CTLR_CHIP_REG_t;
334
335#define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200
336#define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
337
338/* ----------------------------------------------------- */
339
340#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16)
341#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16)
342#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16)
343
344#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8
345#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
346
347#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0
348#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
349
350/* -------------------------------------------------------------------- */
351/* -------------------------------------------------------------------- */
352/* ARM PL341 User configuration registers, offset 0x300 */
353/* -------------------------------------------------------------------- */
354/* -------------------------------------------------------------------- */
355
356#define ddrcReg_CTLR_USER_OUTPUT_CNT 2
357
358 typedef struct {
359 uint32_t input;
360 uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
361 uint32_t feature;
362 } ddrcReg_CTLR_USER_REG_t;
363
364#define ddrcReg_CTLR_USER_REG_OFFSET 0x300
365#define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
366
367/* ----------------------------------------------------- */
368
369#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0
370#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
371
372/* ----------------------------------------------------- */
373
374#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0
375#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
376
377#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1
378#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
379#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
380#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
381#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
382
383/* ----------------------------------------------------- */
384
385#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2)
386#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0)
387
388/*********************************************************************/
389/* Broadcom DDR23 PHY register definitions */
390/*********************************************************************/
391
392/* -------------------------------------------------------------------- */
393/* -------------------------------------------------------------------- */
394/* Broadcom DDR23 PHY Address and Control register definitions */
395/* -------------------------------------------------------------------- */
396/* -------------------------------------------------------------------- */
397
398 typedef struct {
399 uint32_t revision;
400 uint32_t pmCtl;
401 REG32_RSVD(0x0008, 0x0010);
402 uint32_t pllStatus;
403 uint32_t pllCfg;
404 uint32_t pllPreDiv;
405 uint32_t pllDiv;
406 uint32_t pllCtl1;
407 uint32_t pllCtl2;
408 uint32_t ssCtl;
409 uint32_t ssCfg;
410 uint32_t vdlStatic;
411 uint32_t vdlDynamic;
412 uint32_t padIdle;
413 uint32_t pvtComp;
414 uint32_t padDrive;
415 uint32_t clkRgltrCtl;
416 } ddrcReg_PHY_ADDR_CTL_REG_t;
417
418#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
419#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
420
421/* @todo These SS definitions are duplicates of ones below */
422
423#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001
424#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000
425#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16
426#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */
427#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF
428#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0
429
430/* ----------------------------------------------------- */
431
432#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8
433#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
434
435#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0
436#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
437
438/* ----------------------------------------------------- */
439
440#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
441
442/* ----------------------------------------------------- */
443
444#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0)
445
446/* ----------------------------------------------------- */
447
448#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31)
449
450#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17
451#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
452
453#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16)
454
455#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12
456#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
457
458#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7)
459#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6)
460#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5)
461#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4)
462#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3)
463#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2)
464#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0)
465
466/* ----------------------------------------------------- */
467
468#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26)
469#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25)
470
471#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20
472#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
473
474#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8
475#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
476
477#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4
478#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
479
480#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0
481#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
482
483/* ----------------------------------------------------- */
484
485#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24
486#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
487
488#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0
489#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
490
491/* ----------------------------------------------------- */
492
493#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30
494#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
495
496#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27
497#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
498
499#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24
500#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
501
502#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22
503#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
504
505#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21)
506
507#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19
508#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
509
510#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17
511#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
512
513#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15
514#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
515
516#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13
517#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
518
519#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10
520#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
521
522#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5
523#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
524
525#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0
526#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
527
528/* ----------------------------------------------------- */
529#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4
530#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
531
532#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2
533#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
534
535#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1)
536#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0)
537
538/* ----------------------------------------------------- */
539
540#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0)
541
542/* ----------------------------------------------------- */
543
544#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16
545#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
546
547#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0
548#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
549
550/* ----------------------------------------------------- */
551
552#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20)
553#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16)
554
555#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12
556#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
557
558#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8
559#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
560
561#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0
562#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
563
564/* ----------------------------------------------------- */
565
566#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16)
567
568#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12
569#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
570
571#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8
572#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
573
574#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0
575#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
576
577/* ----------------------------------------------------- */
578
579#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31)
580#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8)
581#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6)
582#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5)
583#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4)
584#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2)
585#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1)
586#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0)
587
588/* ----------------------------------------------------- */
589
590#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30)
591#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29)
592#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28)
593#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27)
594#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26)
595#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25)
596#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24)
597
598#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20
599#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
600
601#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16
602#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
603
604#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12
605#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
606
607#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8
608#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
609
610#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4
611#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
612
613#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0
614#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
615
616/* ----------------------------------------------------- */
617
618#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4)
619#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3)
620#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2)
621#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1)
622#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0)
623
624/* ----------------------------------------------------- */
625
626#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1)
627#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0)
628
629/* -------------------------------------------------------------------- */
630/* -------------------------------------------------------------------- */
631/* Broadcom DDR23 PHY Byte Lane register definitions */
632/* -------------------------------------------------------------------- */
633/* -------------------------------------------------------------------- */
634
635#define ddrcReg_PHY_BYTE_LANE_CNT 2
636#define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
637
638#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8
639
640 typedef struct {
641 uint32_t revision;
642 uint32_t vdlCalibrate;
643 uint32_t vdlStatus;
644 REG32_RSVD(0x000c, 0x0010);
645 uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
646 uint32_t readCtl;
647 uint32_t readStatus;
648 uint32_t readClear;
649 uint32_t padIdleCtl;
650 uint32_t padDriveCtl;
651 uint32_t padClkCtl;
652 uint32_t writeCtl;
653 uint32_t clkRegCtl;
654 } ddrcReg_PHY_BYTE_LANE_REG_t;
655
656/* There are 2 instances of the byte Lane registers, one for each byte lane. */
657#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500
658#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600
659
660#define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
661#define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
662
663/* ----------------------------------------------------- */
664
665#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8
666#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
667
668#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0
669#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
670
671/* ----------------------------------------------------- */
672
673#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4)
674#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4)
675
676#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3)
677#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2)
678#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1)
679#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0)
680
681/* ----------------------------------------------------- */
682
683/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
684/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
685/* register. The fine rise and fall are no longer used, so add some definitions for just */
686/* the step setting to simplify things. */
687
688#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8
689#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
690
691#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4
692#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
693
694#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1)
695#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0)
696
697/* ----------------------------------------------------- */
698
699#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16)
700
701#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12
702#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
703
704#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8
705#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
706
707#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0
708#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
709
710#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0
711#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1
712#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2
713#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3
714#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4
715#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5
716#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6
717#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7
718
719/* ----------------------------------------------------- */
720
721#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8
722#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
723
724#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3)
725#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2)
726#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1)
727#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0)
728
729/* ----------------------------------------------------- */
730
731#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0
732#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
733
734/* ----------------------------------------------------- */
735
736#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0)
737
738/* ----------------------------------------------------- */
739
740#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31)
741#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19)
742#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18)
743#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17)
744#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16)
745#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15)
746#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14)
747#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13)
748#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12)
749#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11)
750#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10)
751#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9)
752#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8)
753#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7)
754#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6)
755#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5)
756#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4)
757#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3)
758#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2)
759#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1)
760#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0)
761
762/* ----------------------------------------------------- */
763
764#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5)
765#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4)
766#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3)
767#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2)
768#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1)
769#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0)
770
771/* ----------------------------------------------------- */
772
773#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0)
774
775/* ----------------------------------------------------- */
776
777#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0)
778
779/* ----------------------------------------------------- */
780
781#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1)
782#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0)
783
784/*********************************************************************/
785/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
786/*********************************************************************/
787
788 typedef struct {
789 uint32_t cfg;
790 uint32_t actMonCnt;
791 uint32_t ctl;
792 uint32_t lbistCtl;
793 uint32_t lbistSeed;
794 uint32_t lbistStatus;
795 uint32_t tieOff;
796 uint32_t actMonClear;
797 uint32_t status;
798 uint32_t user;
799 } ddrcReg_CTLR_PHY_GLUE_REG_t;
800
801#define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700
802#define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
803
804/* ----------------------------------------------------- */
805
806/* DDR2 / AXI block phase alignment interrupt control */
807#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18
808#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
809#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
810#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
811#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
812#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
813
814#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17
815#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
816#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
817#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
818
819#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16
820#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
821#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
822#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
823#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
824
825#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15
826#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
827#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
828#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
829#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
830
831/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
832/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
833/* controller. If 2 chips selects are being used, then software control must be enabled. */
834#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14)
835#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13)
836
837/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
838#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
839#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
840#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
841
842/* Chip select count */
843#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9
844#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
845#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
846#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
847
848#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8
849#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
850#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
851
852#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7
853#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
854#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
855
856#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6
857#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
858#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
859
860#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0
861#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
862
863/* ----------------------------------------------------- */
864#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0
865#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
866
867/* ---- Public Function Prototypes --------------------------------------- */
868
869#ifdef __cplusplus
870} /* end extern "C" */
871#endif
872#endif /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
new file mode 100644
index 00000000000..d67e2f8c22d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -0,0 +1,145 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_priv.h
18*
19* @brief Private Definitions for low level DMA driver
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_PRIV_H
25#define _DMACHW_PRIV_H
26
27#include <csp/stdint.h>
28
29/* Data type for DMA Link List Item */
30typedef struct {
31 uint32_t sar; /* Source Address Register.
32 Address must be aligned to CTLx.SRC_TR_WIDTH. */
33 uint32_t dar; /* Destination Address Register.
34 Address must be aligned to CTLx.DST_TR_WIDTH. */
35 uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
36 Address MUST be aligned to a 32-bit boundary. */
37 dmacHw_REG64_t ctl; /* Control Register. 64 bits */
38 uint32_t sstat; /* Source Status Register */
39 uint32_t dstat; /* Destination Status Register */
40 uint32_t devCtl; /* Device specific control information */
41 uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
42} dmacHw_DESC_t;
43
44/*
45 * Descriptor ring pointers
46 */
47typedef struct {
48 int num; /* Number of link items */
49 dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
50 dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
51 dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
52 dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
53 dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
54 uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
55} dmacHw_DESC_RING_t;
56
57/*
58 * DMA channel control block
59 */
60typedef struct {
61 uint32_t module; /* DMA controller module (0-1) */
62 uint32_t channel; /* DMA channel (0-7) */
63 volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
64 volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
65 void *userData; /* Channel specifc user data */
66} dmacHw_CBLK_t;
67
68#define dmacHw_ASSERT(a) if (!(a)) while (1)
69#define dmacHw_MAX_CHANNEL_COUNT 16
70#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
71#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
72#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
73#define dmacHw_MAX_BLOCKSIZE 4064
74#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
75#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
76#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
77#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
78#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
79#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
80
81/****************************************************************************/
82/**
83* @brief Get next available transaction width
84*
85*
86* @return On success : Next available transaction width
87* On failure : dmacHw_TRANSACTION_WIDTH_8
88*
89* @note
90* None
91*/
92/****************************************************************************/
93static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
94 ) {
95 if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
96 return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
97 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
98 } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
99 return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
100 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
101 }
102
103 /* Default return */
104 return dmacHw_SRC_TRANSACTION_WIDTH_8;
105}
106
107/****************************************************************************/
108/**
109* @brief Get number of bytes per transaction
110*
111* @return Number of bytes per transaction
112*
113*
114* @note
115* None
116*/
117/****************************************************************************/
118static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
119 ) {
120 int width = 1;
121 switch (tw) {
122 case dmacHw_SRC_TRANSACTION_WIDTH_8:
123 width = 1;
124 break;
125 case dmacHw_SRC_TRANSACTION_WIDTH_16:
126 case dmacHw_DST_TRANSACTION_WIDTH_16:
127 width = 2;
128 break;
129 case dmacHw_SRC_TRANSACTION_WIDTH_32:
130 case dmacHw_DST_TRANSACTION_WIDTH_32:
131 width = 4;
132 break;
133 case dmacHw_SRC_TRANSACTION_WIDTH_64:
134 case dmacHw_DST_TRANSACTION_WIDTH_64:
135 width = 8;
136 break;
137 default:
138 dmacHw_ASSERT(0);
139 }
140
141 /* Default transaction width */
142 return width;
143}
144
145#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
new file mode 100644
index 00000000000..f1ecf96f2da
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -0,0 +1,406 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_reg.h
18*
19* @brief Definitions for low level DMA registers
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_REG_H
25#define _DMACHW_REG_H
26
27#include <csp/stdint.h>
28#include <mach/csp/mm_io.h>
29
30/* Data type for 64 bit little endian register */
31typedef struct {
32 volatile uint32_t lo; /* Lower 32 bit in little endian mode */
33 volatile uint32_t hi; /* Upper 32 bit in little endian mode */
34} dmacHw_REG64_t;
35
36/* Data type representing DMA channel registers */
37typedef struct {
38 dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
39 Address must be aligned to CTLx.SRC_TR_WIDTH.
40 */
41 dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
42 Address must be aligned to CTLx.DST_TR_WIDTH.
43 */
44 dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved)
45 LLP contains the pointer to the next LLI for block chaining using linked lists.
46 If LLPis set to 0x0, then transfers using linked lists are not enabled.
47 Address MUST be aligned to a 32-bit boundary.
48 */
49 dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */
50 dmacHw_REG64_t ChannelSstat; /* Source Status Register */
51 dmacHw_REG64_t ChannelDstat; /* Destination Status Register */
52 dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */
53 dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */
54 dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */
55 dmacHw_REG64_t SrcGather; /* Source gather register */
56 dmacHw_REG64_t DstScatter; /* Destination scatter register */
57} dmacHw_CH_REG_t;
58
59/* Data type for RAW interrupt status registers */
60typedef struct {
61 dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */
62 dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */
63 dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */
64 dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */
65 dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */
66} dmacHw_INT_RAW_t;
67
68/* Data type for interrupt status registers */
69typedef struct {
70 dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */
71 dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */
72 dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */
73 dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */
74 dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */
75} dmacHw_INT_STATUS_t;
76
77/* Data type for interrupt mask registers*/
78typedef struct {
79 dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
80 dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */
81 dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */
82 dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */
83 dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
84} dmacHw_INT_MASK_t;
85
86/* Data type for interrupt clear registers */
87typedef struct {
88 dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */
89 dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */
90 dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */
91 dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */
92 dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */
93 dmacHw_REG64_t StatusInt; /* Status for each interrupt type */
94} dmacHw_INT_CLEAR_t;
95
96/* Data type for software handshaking registers */
97typedef struct {
98 dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */
99 dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */
100 dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */
101 dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */
102 dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */
103 dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */
104} dmacHw_SW_HANDSHAKE_t;
105
106/* Data type for misc. registers */
107typedef struct {
108 dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */
109 dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
110 dmacHw_REG64_t DmaIdReg; /* DMA ID Register */
111 dmacHw_REG64_t DmaTestReg; /* DMA Test Register */
112 dmacHw_REG64_t Reserved0; /* Reserved */
113 dmacHw_REG64_t Reserved1; /* Reserved */
114 dmacHw_REG64_t CompParm6; /* Component Parameter 6 */
115 dmacHw_REG64_t CompParm5; /* Component Parameter 5 */
116 dmacHw_REG64_t CompParm4; /* Component Parameter 4 */
117 dmacHw_REG64_t CompParm3; /* Component Parameter 3 */
118 dmacHw_REG64_t CompParm2; /* Component Parameter 2 */
119 dmacHw_REG64_t CompParm1; /* Component Parameter 1 */
120 dmacHw_REG64_t CompId; /* Compoent ID */
121} dmacHw_MISC_t;
122
123/* Base registers */
124#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
125#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
126
127extern uint32_t dmaChannelCount_0;
128extern uint32_t dmaChannelCount_1;
129
130/* Define channel specific registers */
131#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
132
133/* Raw interrupt status registers */
134#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
135#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
136#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
137#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
138#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
139#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
140
141/* Interrupt status registers */
142#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
143#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
144#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
145#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
146#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
147#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
148
149/* Interrupt status registers */
150#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
151#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
152#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
153#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
154#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
155#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
156
157/* Interrupt clear registers */
158#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
159#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
160#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
161#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
162#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
163#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
164#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
165
166/* Software handshaking registers */
167#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
168#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
169#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
170#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
171#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
172#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
173#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
174
175/* Miscellaneous registers */
176#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
177#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
178#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
179#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
180#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
181#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
182#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
183#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
184#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
185#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
186#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
187#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
188#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
189#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
190#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
191#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
192#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
193
194/* Channel control registers */
195#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
196#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
197#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
198
199#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
200#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
201
202#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
203#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
204#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
205#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
206
207#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
208#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
209
210#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
211#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
212
213#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
214#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
215
216#define INT_STATUS_MASK(channel) (0x00000001 << (channel))
217#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
218
219/* Bit mask for REG_DMACx_CTL_LO */
220
221#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */
222
223#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */
224#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1
225#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */
226#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */
227#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */
228#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */
229
230#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */
231#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4
232#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */
233#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */
234#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */
235#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */
236
237#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */
238#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */
239
240#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */
241#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */
242#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */
243#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */
244
245#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */
246#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */
247#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */
248#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */
249
250#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */
251#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
252#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */
253#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */
254#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */
255
256#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
257#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
258#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */
259#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */
260#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */
261
262#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */
263#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */
264#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */
265#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */
266#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */
267#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */
268#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */
269#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */
270#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */
271
272#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */
273#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */
274#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */
275
276#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */
277#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */
278#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */
279
280#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */
281#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */
282
283/* Bit mask for REG_DMACx_CTL_HI */
284#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */
285#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */
286
287/* Bit mask for REG_DMACx_CFG_LO */
288#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */
289#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */
290#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */
291#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */
292#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */
293#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */
294#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */
295#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */
296#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */
297#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */
298
299#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */
300#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */
301#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */
302#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */
303
304#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */
305#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */
306#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */
307#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */
308#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */
309
310#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */
311#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */
312#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */
313#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */
314#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */
315
316#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */
317#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */
318
319#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */
320
321#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */
322#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */
323
324/* Bit mask for REG_DMACx_CFG_HI */
325#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */
326#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */
327
328#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */
329#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */
330#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */
331#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */
332
333#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */
334#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */
335
336#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */
337#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */
338
339/* DMA Configuration Parameters */
340#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */
341#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */
342#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */
343#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */
344
345/* Define GET/SET macros to program the registers */
346#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
347#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
348#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
349
350#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel)))
351#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel)))
352
353#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
354#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
355
356#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
357#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0)
358#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)))
359
360#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
361#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0)
362#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)))
363
364#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
365#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
366
367#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
368#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0)
369#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)))
370#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
371#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
372#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
373
374#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
375#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0)
376#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)))
377#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
378#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
379#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
380#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
381
382#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
383#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
384#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1)
385#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0)
386
387#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
388#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
389#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
390
391#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
392#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
393#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
394#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
395#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
396
397#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
398#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
399#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
400
401#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
402#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
403#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
404#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
405
406#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
new file mode 100644
index 00000000000..cfa91bed9d3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -0,0 +1,73 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16#ifndef CSP_HW_CFG_H
17#define CSP_HW_CFG_H
18
19/* ---- Include Files ---------------------------------------------------- */
20
21#include <cfg_global.h>
22#include <mach/csp/cap_inline.h>
23
24#if defined(__KERNEL__)
25#include <mach/memory_settings.h>
26#else
27#include <hw_cfg.h>
28#endif
29
30/* Some items that can be defined externally, but will be set to default values */
31/* if they are not defined. */
32/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */
33/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
34/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
35/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
36/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
37/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
38/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
39
40#if defined(CFG_GLOBAL_CHIP)
41 #if (CFG_GLOBAL_CHIP == FPGA11107)
42 #define HW_CFG_BUS_CLK_HZ 5000000
43 #define HW_CFG_DDR_CTLR_CLK_HZ 10000000
44 #define HW_CFG_DDR_PHY_OMIT
45 #define HW_CFG_UART_CLK_HZ 7500000
46 #else
47 #define HW_CFG_PLL_VCO_HZ 2000000000
48 #define HW_CFG_PLL2_VCO_HZ 1800000000
49 #define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ
50 #define HW_CFG_BUS_CLK_HZ 166666666
51 #define HW_CFG_DDR_CTLR_CLK_HZ 333333333
52 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
53 #define HW_CFG_UART_CLK_HZ 142857142
54 #define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ
55 #endif
56#else
57 #define HW_CFG_PLL_VCO_HZ 1800000000
58 #define HW_CFG_PLL2_VCO_HZ 1800000000
59 #define HW_CFG_ARM_CLK_HZ 450000000
60 #define HW_CFG_BUS_CLK_HZ 150000000
61 #define HW_CFG_DDR_CTLR_CLK_HZ 300000000
62 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ)
63 #define HW_CFG_UART_CLK_HZ 150000000
64 #define HW_CFG_VPM_CLK_HZ 300000000
65#endif
66
67/* ---- Public Constants and Types --------------------------------------- */
68/* ---- Public Variable Externs ------------------------------------------ */
69/* ---- Public Function Prototypes --------------------------------------- */
70
71
72#endif /* CSP_HW_CFG_H */
73
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
new file mode 100644
index 00000000000..0aeb6a6fe7f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -0,0 +1,246 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file intcHw_reg.h
18*
19* @brief platform specific interrupt controller bit assignments
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _INTCHW_REG_H
27#define _INTCHW_REG_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <csp/stdint.h>
31#include <csp/reg.h>
32#include <mach/csp/mm_io.h>
33
34/* ---- Public Constants and Types --------------------------------------- */
35
36#define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
37#define INTCHW_NUM_INTC 3
38
39/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
40#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0)
41#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1)
42#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC)
43
44/* INTC0 - interrupt controller 0 */
45#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
46#define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
47#define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
48#define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */
49#define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */
50#define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */
51#define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */
52#define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */
53#define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */
54#define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */
55#define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */
56#define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */
57#define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */
58#define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */
59#define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */
60#define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */
61#define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */
62#define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */
63#define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */
64#define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */
65#define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */
66#define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */
67#define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */
68#define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */
69#define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */
70#define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */
71#define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */
72#define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */
73#define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */
74#define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */
75#define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */
76#define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */
77
78#define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM)
79#define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM)
80#define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM)
81#define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM)
82#define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM)
83#define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM)
84#define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM)
85#define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM)
86#define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM)
87#define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM)
88#define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM)
89#define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM)
90#define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM)
91#define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM)
92#define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM)
93#define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM)
94#define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM)
95#define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM)
96#define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM)
97#define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM)
98#define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM)
99#define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM)
100#define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM)
101#define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM)
102#define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM)
103#define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM)
104#define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM)
105#define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM)
106#define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM)
107#define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM)
108#define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM)
109#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
110
111/* INTC1 - interrupt controller 1 */
112#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
113#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
114#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interrupt (For A0 only)) */
115#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
116#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
117/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
118#define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */
119#define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */
120#define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */
121#define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */
122#define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */
123#define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */
124#define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */
125#define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */
126#define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */
127#define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */
128#define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */
129
130#define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */
131#define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */
132#define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */
133#define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */
134#define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */
135#define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */
136#define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */
137#define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */
138#define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */
139#define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */
140#define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */
141#define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */
142#define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */
143
144#define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
145#define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
146#define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM)
147#define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM)
148#define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM)
149#define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM)
150#define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM)
151#define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM)
152#define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM)
153#define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM)
154#define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM)
155#define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM)
156#define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM)
157#define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM)
158#define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM)
159#define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM)
160#define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM)
161#define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
162#define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM)
163#define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM)
164#define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM)
165#define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM)
166#define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM)
167#define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM)
168#define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM)
169#define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM)
170#define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM)
171#define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM)
172#define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM)
173
174/* SINTC secure int controller */
175#define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */
176#define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */
177#define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */
178#define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */
179#define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */
180#define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */
181#define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */
182#define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */
183#define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */
184#define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */
185#define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */
186#define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */
187#define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */
188#define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */
189#define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */
190#define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */
191
192#define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM)
193#define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM)
194#define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM)
195#define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM)
196#define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM)
197#define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM)
198#define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM)
199#define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM)
200#define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM)
201#define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM)
202#define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM)
203#define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM)
204#define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM)
205#define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM)
206#define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM)
207#define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM)
208
209/* PL192 Vectored Interrupt Controller (VIC) layout */
210#define INTCHW_IRQSTATUS 0x00 /* IRQ status register */
211#define INTCHW_FIQSTATUS 0x04 /* FIQ status register */
212#define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */
213#define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */
214#define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */
215#define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */
216#define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */
217#define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */
218#define INTCHW_PROTECTION 0x20 /* Protection Enable Register */
219#define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */
220#define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */
221#define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */
222#define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */
223#define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */
224#define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */
225#define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */
226
227/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
228/* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
229/* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
230/* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
231
232/* ---- Public Variable Externs ------------------------------------------ */
233/* ---- Public Function Prototypes --------------------------------------- */
234/* Clear one or more IRQ interrupts. */
235static inline void intcHw_irq_disable(void *basep, uint32_t mask)
236{
237 __REG32(basep + INTCHW_INTENCLEAR) = mask;
238}
239
240/* Enables one or more IRQ interrupts. */
241static inline void intcHw_irq_enable(void *basep, uint32_t mask)
242{
243 __REG32(basep + INTCHW_INTENABLE) = mask;
244}
245
246#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
new file mode 100644
index 00000000000..ad58cf87337
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -0,0 +1,101 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_addr.h
18*
19* @brief Memory Map address definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_ADDR_H
27#define _MM_ADDR_H
28
29/* ---- Include Files ---------------------------------------------------- */
30
31#if !defined(CSP_SIMULATION)
32#include <cfg_global.h>
33#endif
34
35/* ---- Public Constants and Types --------------------------------------- */
36
37/* Memory Map address definitions */
38
39#define MM_ADDR_DDR 0x00000000
40
41#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */
42
43#define MM_ADDR_IO_FLASHC 0x20000000
44#define MM_ADDR_IO_BROM 0x30000000
45#define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */
46#define MM_ADDR_IO_DMA0 0x30200000
47#define MM_ADDR_IO_DMA1 0x30300000
48#define MM_ADDR_IO_ESW 0x30400000
49#define MM_ADDR_IO_CLCD 0x30500000
50#define MM_ADDR_IO_PIF 0x30580000
51#define MM_ADDR_IO_APM 0x30600000
52#define MM_ADDR_IO_SPUM 0x30700000
53#define MM_ADDR_IO_VPM_PROG 0x30800000
54#define MM_ADDR_IO_VPM_DATA 0x30A00000
55#define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */
56#define MM_ADDR_IO_CHIPC 0x80000000
57#define MM_ADDR_IO_UMI 0x80001000
58#define MM_ADDR_IO_NAND 0x80001800
59#define MM_ADDR_IO_LEDM 0x80002000
60#define MM_ADDR_IO_PWM 0x80002040
61#define MM_ADDR_IO_VINTC 0x80003000
62#define MM_ADDR_IO_GPIO0 0x80004000
63#define MM_ADDR_IO_GPIO1 0x80004800
64#define MM_ADDR_IO_I2CS 0x80005000
65#define MM_ADDR_IO_SPIS 0x80006000
66#define MM_ADDR_IO_HPM 0x80007400
67#define MM_ADDR_IO_HPM_REMAP 0x80007800
68#define MM_ADDR_IO_TZPC 0x80008000
69#define MM_ADDR_IO_MPU 0x80009000
70#define MM_ADDR_IO_SPUMP 0x8000a000
71#define MM_ADDR_IO_PKA 0x8000b000
72#define MM_ADDR_IO_RNG 0x8000c000
73#define MM_ADDR_IO_KEYC 0x8000d000
74#define MM_ADDR_IO_BBL 0x8000e000
75#define MM_ADDR_IO_OTP 0x8000f000
76#define MM_ADDR_IO_I2S0 0x80010000
77#define MM_ADDR_IO_I2S1 0x80011000
78#define MM_ADDR_IO_UARTA 0x80012000
79#define MM_ADDR_IO_UARTB 0x80013000
80#define MM_ADDR_IO_I2CH 0x80014020
81#define MM_ADDR_IO_SPIH 0x80015000
82#define MM_ADDR_IO_TSC 0x80016000
83#define MM_ADDR_IO_TMR 0x80017000
84#define MM_ADDR_IO_WATCHDOG 0x80017800
85#define MM_ADDR_IO_ETM 0x80018000
86#define MM_ADDR_IO_DDRC 0x80019000
87#define MM_ADDR_IO_SINTC 0x80100000
88#define MM_ADDR_IO_INTC0 0x80200000
89#define MM_ADDR_IO_INTC1 0x80201000
90#define MM_ADDR_IO_GE 0x80300000
91#define MM_ADDR_IO_USB_CTLR0 0x80400000
92#define MM_ADDR_IO_USB_CTLR1 0x80410000
93#define MM_ADDR_IO_USB_PHY 0x80420000
94#define MM_ADDR_IO_SDIOH0 0x80500000
95#define MM_ADDR_IO_SDIOH1 0x80600000
96#define MM_ADDR_IO_VDEC 0x80700000
97
98/* ---- Public Variable Externs ------------------------------------------ */
99/* ---- Public Function Prototypes --------------------------------------- */
100
101#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
new file mode 100644
index 00000000000..de92ec6a01a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -0,0 +1,147 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file mm_io.h
18*
19* @brief Memory Map I/O definitions
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _MM_IO_H
27#define _MM_IO_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <mach/csp/mm_addr.h>
31
32#if !defined(CSP_SIMULATION)
33#include <cfg_global.h>
34#endif
35
36/* ---- Public Constants and Types --------------------------------------- */
37
38#if defined(CONFIG_MMU)
39
40/* This macro is referenced in <mach/io.h>
41 * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
42 * This macro is referenced in <asm/arch/io.h>
43 *
44 * Assume VPM address is the last x MB of memory. For VPM, map to
45 * 0xf0000000 and up.
46 */
47
48#ifndef MM_IO_PHYS_TO_VIRT
49#ifdef __ASSEMBLY__
50#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
51#else
52#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
53 (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
54#endif
55#endif
56
57/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
58
59#ifndef MM_IO_VIRT_TO_PHYS
60#ifdef __ASSEMBLY__
61#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
62#else
63#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
64 ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
65#endif
66#endif
67
68#else
69
70#ifndef MM_IO_PHYS_TO_VIRT
71#define MM_IO_PHYS_TO_VIRT(phys) (phys)
72#endif
73
74#ifndef MM_IO_VIRT_TO_PHYS
75#define MM_IO_VIRT_TO_PHYS(virt) (virt)
76#endif
77
78#endif
79
80/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
81#define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
82#define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
83#define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
84
85#define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */
86#define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */
87
88#define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
89#define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
90#define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
91#define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
92#define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
93#define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
94#define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
95#define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
96#define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
97#define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
98#define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
99
100#define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
101
102#define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
103#define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
104#define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
105#define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
106#define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
107#define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
108#define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
109#define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
110#define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
111#define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
112#define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
113#define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
114#define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
115#define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
116#define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
117#define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
118#define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
119#define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
120#define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
121#define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
122#define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
123#define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
124#define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
125#define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
126#define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
127#define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
128#define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
129#define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
130#define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
131#define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
132#define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
133#define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
134#define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
135#define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
136#define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
137#define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
138#define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
139#define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
140#define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
141
142#define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
143
144/* ---- Public Variable Externs ------------------------------------------ */
145/* ---- Public Function Prototypes --------------------------------------- */
146
147#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
new file mode 100644
index 00000000000..d15f5f3ec2d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
@@ -0,0 +1,100 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw_def.h
18*
19* @brief Definitions for configuring/testing secure blocks
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef SECHW_DEF_H
27#define SECHW_DEF_H
28
29#include <mach/csp/mm_io.h>
30
31/* Bit mask for various secure device */
32#define secHw_BLK_MASK_CHIP_CONTROL 0x00000001
33#define secHw_BLK_MASK_KEY_SCAN 0x00000002
34#define secHw_BLK_MASK_TOUCH_SCREEN 0x00000004
35#define secHw_BLK_MASK_UART0 0x00000008
36#define secHw_BLK_MASK_UART1 0x00000010
37#define secHw_BLK_MASK_WATCHDOG 0x00000020
38#define secHw_BLK_MASK_SPUM 0x00000040
39#define secHw_BLK_MASK_DDR2 0x00000080
40#define secHw_BLK_MASK_EXT_MEM 0x00000100
41#define secHw_BLK_MASK_ESW 0x00000200
42#define secHw_BLK_MASK_SPU 0x00010000
43#define secHw_BLK_MASK_PKA 0x00020000
44#define secHw_BLK_MASK_RNG 0x00040000
45#define secHw_BLK_MASK_RTC 0x00080000
46#define secHw_BLK_MASK_OTP 0x00100000
47#define secHw_BLK_MASK_BOOT 0x00200000
48#define secHw_BLK_MASK_MPU 0x00400000
49#define secHw_BLK_MASK_TZCTRL 0x00800000
50#define secHw_BLK_MASK_INTR 0x01000000
51
52/* Trustzone register set */
53typedef struct {
54 volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */
55 volatile uint32_t setUnsecure; /* write only. reads back as 0 */
56 volatile uint32_t setSecure; /* write only. reads back as 0 */
57} secHw_TZREG_t;
58
59/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
60/* is for the higher 16 bits. */
61
62typedef enum {
63 secHw_IDX_LS = 0,
64 secHw_IDX_MS = 1,
65 secHw_IDX_NUM
66} secHw_IDX_e;
67
68typedef struct {
69 volatile secHw_TZREG_t reg[secHw_IDX_NUM];
70} secHw_REGS_t;
71
72/****************************************************************************/
73/**
74* @brief Configures a device as a secure device
75*
76*/
77/****************************************************************************/
78static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
79 );
80
81/****************************************************************************/
82/**
83* @brief Configures a device as a non-secure device
84*
85*/
86/****************************************************************************/
87static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
88 );
89
90/****************************************************************************/
91/**
92* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
93*
94*/
95/****************************************************************************/
96static inline uint32_t secHw_getStatus(void);
97
98#include <mach/csp/secHw_inline.h>
99
100#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
new file mode 100644
index 00000000000..9cd6a032ab7
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -0,0 +1,79 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file secHw_inline.h
18*
19* @brief Definitions for configuring/testing secure blocks
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef SECHW_INLINE_H
27#define SECHW_INLINE_H
28
29/****************************************************************************/
30/**
31* @brief Configures a device as a secure device
32*
33*/
34/****************************************************************************/
35static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
36 ) {
37 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
38
39 if (mask & 0x0000FFFF) {
40 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
41 }
42
43 if (mask & 0xFFFF0000) {
44 regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
45 }
46}
47
48/****************************************************************************/
49/**
50* @brief Configures a device as a non-secure device
51*
52*/
53/****************************************************************************/
54static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
55 ) {
56 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
57
58 if (mask & 0x0000FFFF) {
59 regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
60 }
61 if (mask & 0xFFFF0000) {
62 regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
63 }
64}
65
66/****************************************************************************/
67/**
68* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure
69*
70*/
71/****************************************************************************/
72static inline uint32_t secHw_getStatus(void)
73{
74 secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
75
76 return (regp->reg[1].status << 16) + regp->reg[0].status;
77}
78
79#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
new file mode 100644
index 00000000000..3080ac7239a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
@@ -0,0 +1,82 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file tmrHw_reg.h
18*
19* @brief Definitions for low level Timer registers
20*
21*/
22/****************************************************************************/
23#ifndef _TMRHW_REG_H
24#define _TMRHW_REG_H
25
26#include <mach/csp/mm_io.h>
27#include <mach/csp/hw_cfg.h>
28/* Base address */
29#define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR
30
31/*
32This platform has four different timers running at different clock speed
33
34Timer one (Timer ID 0) runs at 25 MHz
35Timer two (Timer ID 1) runs at 25 MHz
36Timer three (Timer ID 2) runs at 150 MHz
37Timer four (Timer ID 3) runs at 150 MHz
38*/
39#define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */
40#define tmrHw_LOW_FREQUENCY_HZ 25000000
41
42#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
43#define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */
44#define tmrHw_HIGH_FREQUENCY_HZ 150000000
45#else
46#define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ
47#define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000)
48#endif
49
50#define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ
51#define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ
52#define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */
53#define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */
54
55typedef struct {
56 uint32_t LoadValue; /* Load value for timer */
57 uint32_t CurrentValue; /* Current value for timer */
58 uint32_t Control; /* Control register */
59 uint32_t InterruptClear; /* Interrupt clear register */
60 uint32_t RawInterruptStatus; /* Raw interrupt status */
61 uint32_t InterruptStatus; /* Masked interrupt status */
62 uint32_t BackgroundLoad; /* Background load value */
63 uint32_t padding; /* Padding register */
64} tmrHw_REG_t;
65
66/* Control bot masks */
67#define tmrHw_CONTROL_TIMER_ENABLE 0x00000080
68#define tmrHw_CONTROL_PERIODIC 0x00000040
69#define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020
70#define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C
71#define tmrHw_CONTROL_PRESCALE_1 0x00000000
72#define tmrHw_CONTROL_PRESCALE_16 0x00000004
73#define tmrHw_CONTROL_PRESCALE_256 0x00000008
74#define tmrHw_CONTROL_32BIT 0x00000002
75#define tmrHw_CONTROL_ONESHOT 0x00000001
76#define tmrHw_CONTROL_FREE_RUNNING 0x00000000
77
78#define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
79
80#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
81
82#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
new file mode 100644
index 00000000000..1f2c5319c05
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -0,0 +1,826 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dma.h
18*
19* @brief API definitions for the linux DMA interface.
20*/
21/****************************************************************************/
22
23#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
24#define ASM_ARM_ARCH_BCMRING_DMA_H
25
26/* ---- Include Files ---------------------------------------------------- */
27
28#include <linux/kernel.h>
29#include <linux/wait.h>
30#include <linux/semaphore.h>
31#include <csp/dmacHw.h>
32#include <mach/timer.h>
33#include <linux/scatterlist.h>
34#include <linux/dma-mapping.h>
35#include <linux/mm.h>
36#include <linux/vmalloc.h>
37#include <linux/pagemap.h>
38
39/* ---- Constants and Types ---------------------------------------------- */
40
41/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
42/* and line number of the reservation request will be recorded in the channel table */
43
44#define DMA_DEBUG_TRACK_RESERVATION 1
45
46#define DMA_NUM_CONTROLLERS 2
47#define DMA_NUM_CHANNELS 8 /* per controller */
48
49typedef enum {
50 DMA_DEVICE_MEM_TO_MEM, /* For memory to memory transfers */
51 DMA_DEVICE_I2S0_DEV_TO_MEM,
52 DMA_DEVICE_I2S0_MEM_TO_DEV,
53 DMA_DEVICE_I2S1_DEV_TO_MEM,
54 DMA_DEVICE_I2S1_MEM_TO_DEV,
55 DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
56 DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
57 DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
58 DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
59 DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM, /* Additional mic input for beam-forming */
60 DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
61 DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
62 DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
63 DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
64 DMA_DEVICE_SPUM_DEV_TO_MEM,
65 DMA_DEVICE_SPUM_MEM_TO_DEV,
66 DMA_DEVICE_SPIH_DEV_TO_MEM,
67 DMA_DEVICE_SPIH_MEM_TO_DEV,
68 DMA_DEVICE_UART_A_DEV_TO_MEM,
69 DMA_DEVICE_UART_A_MEM_TO_DEV,
70 DMA_DEVICE_UART_B_DEV_TO_MEM,
71 DMA_DEVICE_UART_B_MEM_TO_DEV,
72 DMA_DEVICE_PIF_MEM_TO_DEV,
73 DMA_DEVICE_PIF_DEV_TO_MEM,
74 DMA_DEVICE_ESW_DEV_TO_MEM,
75 DMA_DEVICE_ESW_MEM_TO_DEV,
76 DMA_DEVICE_VPM_MEM_TO_MEM,
77 DMA_DEVICE_CLCD_MEM_TO_MEM,
78 DMA_DEVICE_NAND_MEM_TO_MEM,
79 DMA_DEVICE_MEM_TO_VRAM,
80 DMA_DEVICE_VRAM_TO_MEM,
81
82 /* Add new entries before this line. */
83
84 DMA_NUM_DEVICE_ENTRIES,
85 DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
86
87} DMA_Device_t;
88
89/****************************************************************************
90*
91* The DMA_Handle_t is the primary object used by callers of the API.
92*
93*****************************************************************************/
94
95#define DMA_INVALID_HANDLE ((DMA_Handle_t) -1)
96
97typedef int DMA_Handle_t;
98
99/****************************************************************************
100*
101* The DMA_DescriptorRing_t contains a ring of descriptors which is used
102* to point to regions of memory.
103*
104*****************************************************************************/
105
106typedef struct {
107 void *virtAddr; /* Virtual Address of the descriptor ring */
108 dma_addr_t physAddr; /* Physical address of the descriptor ring */
109 int descriptorsAllocated; /* Number of descriptors allocated in the descriptor ring */
110 size_t bytesAllocated; /* Number of bytes allocated in the descriptor ring */
111
112} DMA_DescriptorRing_t;
113
114/****************************************************************************
115*
116* The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup
117* DMA chains from a variety of memory sources.
118*
119*****************************************************************************/
120
121#define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */
122 /* off not being DMA'd. */
123
124typedef enum {
125 DMA_MEM_TYPE_NONE, /* Not a valid setting */
126 DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */
127 DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */
128 DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */
129 DMA_MEM_TYPE_USER, /* Memory came from user space. */
130
131} DMA_MemType_t;
132
133/* A segment represents a physically and virtually contiguous chunk of memory. */
134/* i.e. each segment can be DMA'd */
135/* A user of the DMA code will add memory regions. Each region may need to be */
136/* represented by one or more segments. */
137
138typedef struct {
139 void *virtAddr; /* Virtual address used for this segment */
140 dma_addr_t physAddr; /* Physical address this segment maps to */
141 size_t numBytes; /* Size of the segment, in bytes */
142
143} DMA_Segment_t;
144
145/* A region represents a virtually contiguous chunk of memory, which may be */
146/* made up of multiple segments. */
147
148typedef struct {
149 DMA_MemType_t memType;
150 void *virtAddr;
151 size_t numBytes;
152
153 /* Each region (virtually contiguous) consists of one or more segments. Each */
154 /* segment is virtually and physically contiguous. */
155
156 int numSegmentsUsed;
157 int numSegmentsAllocated;
158 DMA_Segment_t *segment;
159
160 /* When a region corresponds to user memory, we need to lock all of the pages */
161 /* down before we can figure out the physical addresses. The lockedPage array contains */
162 /* the pages that were locked, and which subsequently need to be unlocked once the */
163 /* memory is unmapped. */
164
165 unsigned numLockedPages;
166 struct page **lockedPages;
167
168} DMA_Region_t;
169
170typedef struct {
171 int inUse; /* Is this mapping currently being used? */
172 struct semaphore lock; /* Acquired when using this structure */
173 enum dma_data_direction dir; /* Direction this transfer is intended for */
174
175 /* In the event that we're mapping user memory, we need to know which task */
176 /* the memory is for, so that we can obtain the correct mm locks. */
177
178 struct task_struct *userTask;
179
180 int numRegionsUsed;
181 int numRegionsAllocated;
182 DMA_Region_t *region;
183
184} DMA_MemMap_t;
185
186/****************************************************************************
187*
188* The DMA_DeviceAttribute_t contains information which describes a
189* particular DMA device (or peripheral).
190*
191* It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
192* statically initialized.
193*
194*****************************************************************************/
195
196/* The device handler is called whenever a DMA operation completes. The reaon */
197/* for it to be called will be a bitmask with one or more of the following bits */
198/* set. */
199
200#define DMA_HANDLER_REASON_BLOCK_COMPLETE dmacHw_INTERRUPT_STATUS_BLOCK
201#define DMA_HANDLER_REASON_TRANSFER_COMPLETE dmacHw_INTERRUPT_STATUS_TRANS
202#define DMA_HANDLER_REASON_ERROR dmacHw_INTERRUPT_STATUS_ERROR
203
204typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
205 void *userData);
206
207#define DMA_DEVICE_FLAG_ON_DMA0 0x00000001
208#define DMA_DEVICE_FLAG_ON_DMA1 0x00000002
209#define DMA_DEVICE_FLAG_PORT_PER_DMAC 0x00000004 /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
210#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST 0x00000008 /* If set, allocate from DMA1 before allocating from DMA0 */
211#define DMA_DEVICE_FLAG_IS_DEDICATED 0x00000100
212#define DMA_DEVICE_FLAG_NO_ISR 0x00000200
213#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO 0x00000400
214#define DMA_DEVICE_FLAG_IN_USE 0x00000800 /* If set, device is in use on a channel */
215
216/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
217/* determine which DMA controllers a given device can be used from, and the interface */
218/* array determeines the actual interface number to use for a given controller. */
219
220typedef struct {
221 uint32_t flags; /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
222 uint8_t dedicatedController; /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
223 uint8_t dedicatedChannel; /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
224 const char *name; /* Will show up in the /proc entry */
225
226 uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
227
228 dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
229
230 void *userData; /* Passed to the devHandler */
231 DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
232
233 timer_tick_count_t transferStartTime; /* Time the current transfer was started */
234
235 /* The following statistical information will be collected and presented in a proc entry. */
236 /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
237 /* a 64 bit counter. */
238
239 uint64_t numTransfers; /* Number of DMA transfers performed */
240 uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
241 uint64_t transferBytes; /* Total bytes transferred */
242 uint32_t timesBlocked; /* Number of times a channel was unavailable */
243 uint32_t numBytes; /* Last transfer size */
244
245 /* It's not possible to free memory which is allocated for the descriptors from within */
246 /* the ISR. So make the presumption that a given device will tend to use the */
247 /* same sized buffers over and over again, and we keep them around. */
248
249 DMA_DescriptorRing_t ring; /* Ring of descriptors allocated for this device */
250
251 /* We stash away some of the information from the previous transfer. If back-to-back */
252 /* transfers are performed from the same buffer, then we don't have to keep re-initializing */
253 /* the descriptor buffers. */
254
255 uint32_t prevNumBytes;
256 dma_addr_t prevSrcData;
257 dma_addr_t prevDstData;
258
259} DMA_DeviceAttribute_t;
260
261/****************************************************************************
262*
263* DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
264* data structures and don't belong in this header file, but are included
265* merely for discussion.
266*
267* By the time this is implemented, these structures will be moved out into
268* the appropriate C source file instead.
269*
270*****************************************************************************/
271
272/****************************************************************************
273*
274* The DMA_Channel_t contains state information about each DMA channel. Some
275* of the channels are dedicated. Non-dedicated channels are shared
276* amongst the other devices.
277*
278*****************************************************************************/
279
280#define DMA_CHANNEL_FLAG_IN_USE 0x00000001
281#define DMA_CHANNEL_FLAG_IS_DEDICATED 0x00000002
282#define DMA_CHANNEL_FLAG_NO_ISR 0x00000004
283#define DMA_CHANNEL_FLAG_LARGE_FIFO 0x00000008
284
285typedef struct {
286 uint32_t flags; /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
287 DMA_Device_t devType; /* Device this channel is currently reserved for */
288 DMA_Device_t lastDevType; /* Device type that used this previously */
289 char name[20]; /* Name passed onto request_irq */
290
291#if (DMA_DEBUG_TRACK_RESERVATION)
292 const char *fileName; /* Place where channel reservation took place */
293 int lineNum; /* Place where channel reservation took place */
294#endif
295 dmacHw_HANDLE_t dmacHwHandle; /* low level channel handle. */
296
297} DMA_Channel_t;
298
299/****************************************************************************
300*
301* The DMA_Controller_t contains state information about each DMA controller.
302*
303* The freeChannelQ is stored in the controller data structure rather than
304* the channel data structure since several of the devices are accessible
305* from multiple controllers, and there is no way to know which controller
306* will become available first.
307*
308*****************************************************************************/
309
310typedef struct {
311 DMA_Channel_t channel[DMA_NUM_CHANNELS];
312
313} DMA_Controller_t;
314
315/****************************************************************************
316*
317* The DMA_Global_t contains all of the global state information used by
318* the DMA code.
319*
320* Callers which need to allocate a shared channel will be queued up
321* on the freeChannelQ until a channel becomes available.
322*
323*****************************************************************************/
324
325typedef struct {
326 struct semaphore lock; /* acquired when manipulating table entries */
327 wait_queue_head_t freeChannelQ;
328
329 DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
330
331} DMA_Global_t;
332
333/* ---- Variable Externs ------------------------------------------------- */
334
335extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
336
337/* ---- Function Prototypes ---------------------------------------------- */
338
339#if defined(__KERNEL__)
340
341/****************************************************************************/
342/**
343* Initializes the DMA module.
344*
345* @return
346* 0 - Success
347* < 0 - Error
348*/
349/****************************************************************************/
350
351int dma_init(void);
352
353#if (DMA_DEBUG_TRACK_RESERVATION)
354DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
355 int lineNum);
356#define dma_request_channel(dev) dma_request_channel_dbg(dev, __FILE__, __LINE__)
357#else
358
359/****************************************************************************/
360/**
361* Reserves a channel for use with @a dev. If the device is setup to use
362* a shared channel, then this function will block until a free channel
363* becomes available.
364*
365* @return
366* >= 0 - A valid DMA Handle.
367* -EBUSY - Device is currently being used.
368* -ENODEV - Device handed in is invalid.
369*/
370/****************************************************************************/
371
372DMA_Handle_t dma_request_channel(DMA_Device_t dev /* Device to use with the allocated channel. */
373 );
374#endif
375
376/****************************************************************************/
377/**
378* Frees a previously allocated DMA Handle.
379*
380* @return
381* 0 - DMA Handle was released successfully.
382* -EINVAL - Invalid DMA handle
383*/
384/****************************************************************************/
385
386int dma_free_channel(DMA_Handle_t channel /* DMA handle. */
387 );
388
389/****************************************************************************/
390/**
391* Determines if a given device has been configured as using a shared
392* channel.
393*
394* @return boolean
395* 0 Device uses a dedicated channel
396* non-zero Device uses a shared channel
397*/
398/****************************************************************************/
399
400int dma_device_is_channel_shared(DMA_Device_t dev /* Device to check. */
401 );
402
403/****************************************************************************/
404/**
405* Allocates memory to hold a descriptor ring. The descriptor ring then
406* needs to be populated by making one or more calls to
407* dna_add_descriptors.
408*
409* The returned descriptor ring will be automatically initialized.
410*
411* @return
412* 0 Descriptor ring was allocated successfully
413* -ENOMEM Unable to allocate memory for the desired number of descriptors.
414*/
415/****************************************************************************/
416
417int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */
418 int numDescriptors /* Number of descriptors that need to be allocated. */
419 );
420
421/****************************************************************************/
422/**
423* Releases the memory which was previously allocated for a descriptor ring.
424*/
425/****************************************************************************/
426
427void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */
428 );
429
430/****************************************************************************/
431/**
432* Initializes a descriptor ring, so that descriptors can be added to it.
433* Once a descriptor ring has been allocated, it may be reinitialized for
434* use with additional/different regions of memory.
435*
436* Note that if 7 descriptors are allocated, it's perfectly acceptable to
437* initialize the ring with a smaller number of descriptors. The amount
438* of memory allocated for the descriptor ring will not be reduced, and
439* the descriptor ring may be reinitialized later
440*
441* @return
442* 0 Descriptor ring was initialized successfully
443* -ENOMEM The descriptor which was passed in has insufficient space
444* to hold the desired number of descriptors.
445*/
446/****************************************************************************/
447
448int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */
449 int numDescriptors /* Number of descriptors to initialize. */
450 );
451
452/****************************************************************************/
453/**
454* Determines the number of descriptors which would be required for a
455* transfer of the indicated memory region.
456*
457* This function also needs to know which DMA device this transfer will
458* be destined for, so that the appropriate DMA configuration can be retrieved.
459* DMA parameters such as transfer width, and whether this is a memory-to-memory
460* or memory-to-peripheral, etc can all affect the actual number of descriptors
461* required.
462*
463* @return
464* > 0 Returns the number of descriptors required for the indicated transfer
465* -EINVAL Invalid device type for this kind of transfer
466* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
467* -ENOMEM Memory exhausted
468*/
469/****************************************************************************/
470
471int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
472 dma_addr_t srcData, /* Place to get data to write to device */
473 dma_addr_t dstData, /* Pointer to device data address */
474 size_t numBytes /* Number of bytes to transfer to the device */
475 );
476
477/****************************************************************************/
478/**
479* Adds a region of memory to the descriptor ring. Note that it may take
480* multiple descriptors for each region of memory. It is the callers
481* responsibility to allocate a sufficiently large descriptor ring.
482*
483* @return
484* 0 Descriptors were added successfully
485* -EINVAL Invalid device type for this kind of transfer
486* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
487* -ENOMEM Memory exhausted
488*/
489/****************************************************************************/
490
491int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */
492 DMA_Device_t device, /* DMA Device that descriptors are for */
493 dma_addr_t srcData, /* Place to get data (memory or device) */
494 dma_addr_t dstData, /* Place to put data (memory or device) */
495 size_t numBytes /* Number of bytes to transfer to the device */
496 );
497
498/****************************************************************************/
499/**
500* Sets the descriptor ring associated with a device.
501*
502* Once set, the descriptor ring will be associated with the device, even
503* across channel request/free calls. Passing in a NULL descriptor ring
504* will release any descriptor ring currently associated with the device.
505*
506* Note: If you call dma_transfer, or one of the other dma_alloc_ functions
507* the descriptor ring may be released and reallocated.
508*
509* Note: This function will release the descriptor memory for any current
510* descriptor ring associated with this device.
511*/
512/****************************************************************************/
513
514int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
515 DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */
516 );
517
518/****************************************************************************/
519/**
520* Retrieves the descriptor ring associated with a device.
521*/
522/****************************************************************************/
523
524int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
525 DMA_DescriptorRing_t *ring /* Place to store retrieved ring */
526 );
527
528/****************************************************************************/
529/**
530* Allocates buffers for the descriptors. This is normally done automatically
531* but needs to be done explicitly when initiating a dma from interrupt
532* context.
533*
534* @return
535* 0 Descriptors were allocated successfully
536* -EINVAL Invalid device type for this kind of transfer
537* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
538* -ENOMEM Memory exhausted
539*/
540/****************************************************************************/
541
542int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */
543 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
544 dma_addr_t srcData, /* Place to get data to write to device */
545 dma_addr_t dstData, /* Pointer to device data address */
546 size_t numBytes /* Number of bytes to transfer to the device */
547 );
548
549/****************************************************************************/
550/**
551* Allocates and sets up descriptors for a double buffered circular buffer.
552*
553* This is primarily intended to be used for things like the ingress samples
554* from a microphone.
555*
556* @return
557* > 0 Number of descriptors actually allocated.
558* -EINVAL Invalid device type for this kind of transfer
559* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
560* -ENOMEM Memory exhausted
561*/
562/****************************************************************************/
563
564int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
565 dma_addr_t srcData, /* Physical address of source data */
566 dma_addr_t dstData1, /* Physical address of first destination buffer */
567 dma_addr_t dstData2, /* Physical address of second destination buffer */
568 size_t numBytes /* Number of bytes in each destination buffer */
569 );
570
571/****************************************************************************/
572/**
573* Initializes a DMA_MemMap_t data structure
574*/
575/****************************************************************************/
576
577int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
578 );
579
580/****************************************************************************/
581/**
582* Releases any memory currently being held by a memory mapping structure.
583*/
584/****************************************************************************/
585
586int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
587 );
588
589/****************************************************************************/
590/**
591* Looks at a memory address and categorizes it.
592*
593* @return One of the values from the DMA_MemType_t enumeration.
594*/
595/****************************************************************************/
596
597DMA_MemType_t dma_mem_type(void *addr);
598
599/****************************************************************************/
600/**
601* Sets the process (aka userTask) associated with a mem map. This is
602* required if user-mode segments will be added to the mapping.
603*/
604/****************************************************************************/
605
606static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap,
607 struct task_struct *task)
608{
609 memMap->userTask = task;
610}
611
612/****************************************************************************/
613/**
614* Looks at a memory address and determines if we support DMA'ing to/from
615* that type of memory.
616*
617* @return boolean -
618* return value != 0 means dma supported
619* return value == 0 means dma not supported
620*/
621/****************************************************************************/
622
623int dma_mem_supports_dma(void *addr);
624
625/****************************************************************************/
626/**
627* Initializes a memory map for use. Since this function acquires a
628* sempaphore within the memory map, it is VERY important that dma_unmap
629* be called when you're finished using the map.
630*/
631/****************************************************************************/
632
633int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
634 enum dma_data_direction dir /* Direction that the mapping will be going */
635 );
636
637/****************************************************************************/
638/**
639* Adds a segment of memory to a memory map.
640*
641* @return 0 on success, error code otherwise.
642*/
643/****************************************************************************/
644
645int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
646 void *mem, /* Virtual address that we want to get a map of */
647 size_t numBytes /* Number of bytes being mapped */
648 );
649
650/****************************************************************************/
651/**
652* Creates a descriptor ring from a memory mapping.
653*
654* @return 0 on success, error code otherwise.
655*/
656/****************************************************************************/
657
658int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
659 DMA_MemMap_t *memMap, /* Memory map that will be used */
660 dma_addr_t devPhysAddr /* Physical address of device */
661 );
662
663/****************************************************************************/
664/**
665* Maps in a memory region such that it can be used for performing a DMA.
666*
667* @return
668*/
669/****************************************************************************/
670
671int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
672 void *addr, /* Virtual address that we want to get a map of */
673 size_t count, /* Number of bytes being mapped */
674 enum dma_data_direction dir /* Direction that the mapping will be going */
675 );
676
677/****************************************************************************/
678/**
679* Maps in a memory region such that it can be used for performing a DMA.
680*
681* @return
682*/
683/****************************************************************************/
684
685int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
686 int dirtied /* non-zero if any of the pages were modified */
687 );
688
689/****************************************************************************/
690/**
691* Initiates a transfer when the descriptors have already been setup.
692*
693* This is a special case, and normally, the dma_transfer_xxx functions should
694* be used.
695*
696* @return
697* 0 Transfer was started successfully
698* -ENODEV Invalid handle
699*/
700/****************************************************************************/
701
702int dma_start_transfer(DMA_Handle_t handle);
703
704/****************************************************************************/
705/**
706* Stops a previously started DMA transfer.
707*
708* @return
709* 0 Transfer was stopped successfully
710* -ENODEV Invalid handle
711*/
712/****************************************************************************/
713
714int dma_stop_transfer(DMA_Handle_t handle);
715
716/****************************************************************************/
717/**
718* Waits for a DMA to complete by polling. This function is only intended
719* to be used for testing. Interrupts should be used for most DMA operations.
720*/
721/****************************************************************************/
722
723int dma_wait_transfer_done(DMA_Handle_t handle);
724
725/****************************************************************************/
726/**
727* Initiates a DMA transfer
728*
729* @return
730* 0 Transfer was started successfully
731* -EINVAL Invalid device type for this kind of transfer
732* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
733*/
734/****************************************************************************/
735
736int dma_transfer(DMA_Handle_t handle, /* DMA Handle */
737 dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */
738 dma_addr_t srcData, /* Place to get data to write to device */
739 dma_addr_t dstData, /* Pointer to device data address */
740 size_t numBytes /* Number of bytes to transfer to the device */
741 );
742
743/****************************************************************************/
744/**
745* Initiates a transfer from memory to a device.
746*
747* @return
748* 0 Transfer was started successfully
749* -EINVAL Invalid device type for this kind of transfer
750* (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
751*/
752/****************************************************************************/
753
754static inline int dma_transfer_to_device(DMA_Handle_t handle, /* DMA Handle */
755 dma_addr_t srcData, /* Place to get data to write to device (physical address) */
756 dma_addr_t dstData, /* Pointer to device data address (physical address) */
757 size_t numBytes /* Number of bytes to transfer to the device */
758 ) {
759 return dma_transfer(handle,
760 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
761 srcData, dstData, numBytes);
762}
763
764/****************************************************************************/
765/**
766* Initiates a transfer from a device to memory.
767*
768* @return
769* 0 Transfer was started successfully
770* -EINVAL Invalid device type for this kind of transfer
771* (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
772*/
773/****************************************************************************/
774
775static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
776 dma_addr_t srcData, /* Pointer to the device data address (physical address) */
777 dma_addr_t dstData, /* Place to store data retrieved from the device (physical address) */
778 size_t numBytes /* Number of bytes to retrieve from the device */
779 ) {
780 return dma_transfer(handle,
781 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
782 srcData, dstData, numBytes);
783}
784
785/****************************************************************************/
786/**
787* Initiates a memory to memory transfer.
788*
789* @return
790* 0 Transfer was started successfully
791* -EINVAL Invalid device type for this kind of transfer
792* (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
793*/
794/****************************************************************************/
795
796static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle, /* DMA Handle */
797 dma_addr_t srcData, /* Place to transfer data from (physical address) */
798 dma_addr_t dstData, /* Place to transfer data to (physical address) */
799 size_t numBytes /* Number of bytes to transfer */
800 ) {
801 return dma_transfer(handle,
802 dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
803 srcData, dstData, numBytes);
804}
805
806/****************************************************************************/
807/**
808* Set the callback function which will be called when a transfer completes.
809* If a NULL callback function is set, then no callback will occur.
810*
811* @note @a devHandler will be called from IRQ context.
812*
813* @return
814* 0 - Success
815* -ENODEV - Device handed in is invalid.
816*/
817/****************************************************************************/
818
819int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */
820 DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */
821 void *userData /* Pointer which will be passed to devHandler. */
822 );
823
824#endif
825
826#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
new file mode 100644
index 00000000000..94c950d783b
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -0,0 +1,82 @@
1/*****************************************************************************
2* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16 *
17 * Low-level IRQ helper macros for BCMRing-based platforms
18 *
19 */
20#include <mach/irqs.h>
21#include <mach/hardware.h>
22#include <mach/csp/mm_io.h>
23
24 .macro disable_fiq
25 .endm
26
27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
28 ldr \base, =(MM_IO_BASE_INTC0)
29 ldr \irqstat, [\base, #0] @ get status
30 ldr \irqnr, [\base, #0x10] @ mask with enable register
31 ands \irqstat, \irqstat, \irqnr
32 mov \irqnr, #IRQ_INTC0_START
33 cmp \irqstat, #0
34 bne 1001f
35
36 ldr \base, =(MM_IO_BASE_INTC1)
37 ldr \irqstat, [\base, #0] @ get status
38 ldr \irqnr, [\base, #0x10] @ mask with enable register
39 ands \irqstat, \irqstat, \irqnr
40 mov \irqnr, #IRQ_INTC1_START
41 cmp \irqstat, #0
42 bne 1001f
43
44 ldr \base, =(MM_IO_BASE_SINTC)
45 ldr \irqstat, [\base, #0] @ get status
46 ldr \irqnr, [\base, #0x10] @ mask with enable register
47 ands \irqstat, \irqstat, \irqnr
48 mov \irqnr, #0xffffffff @ code meaning no interrupt bits set
49 cmp \irqstat, #0
50 beq 1002f
51
52 mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value
53
541001:
55 movs \tmp, \irqstat, lsl #16
56 movne \irqstat, \tmp
57 addeq \irqnr, \irqnr, #16
58
59 movs \tmp, \irqstat, lsl #8
60 movne \irqstat, \tmp
61 addeq \irqnr, \irqnr, #8
62
63 movs \tmp, \irqstat, lsl #4
64 movne \irqstat, \tmp
65 addeq \irqnr, \irqnr, #4
66
67 movs \tmp, \irqstat, lsl #2
68 movne \irqstat, \tmp
69 addeq \irqnr, \irqnr, #2
70
71 movs \tmp, \irqstat, lsl #1
72 addeq \irqnr, \irqnr, #1
73 orrs \base, \base, #1
74
751002: @ irqnr will be set to 0xffffffff if no irq bits are set
76 .endm
77
78 .macro get_irqnr_preamble, base, tmp
79 .endm
80
81 .macro arch_ret_to_user, tmp1, tmp2
82 .endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
new file mode 100644
index 00000000000..ed78aabb8e9
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -0,0 +1,58 @@
1/*
2 *
3 * This file contains the hardware definitions of the BCMRing.
4 *
5 * Copyright (C) 1999 ARM Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_HARDWARE_H
22#define __ASM_ARCH_HARDWARE_H
23
24#include <asm/sizes.h>
25#include <mach/memory.h>
26#include <cfg_global.h>
27#include <mach/csp/mm_io.h>
28
29/* Hardware addresses of major areas.
30 * *_START is the physical address
31 * *_SIZE is the size of the region
32 * *_BASE is the virtual address
33 */
34#define RAM_START PLAT_PHYS_OFFSET
35
36#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
37#define RAM_BASE PAGE_OFFSET
38
39/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
40/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
41#if defined(__KERNEL__)
42#define HW_DECLARE_SPINLOCK(name) DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
43#define HW_EXTERN_SPINLOCK(name) extern spinlock_t bcmring_##name##_reg_lock;
44#define HW_IRQ_SAVE(name, val) spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
45#define HW_IRQ_RESTORE(name, val) spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
46#else
47#define HW_DECLARE_SPINLOCK(name)
48#define HW_EXTERN_SPINLOCK(name)
49#define HW_IRQ_SAVE(name, val) {(void)(name); (void)(val); }
50#define HW_IRQ_RESTORE(name, val) {(void)(name); (void)(val); }
51#endif
52
53#ifndef HW_IO_PHYS_TO_VIRT
54#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
55#endif
56#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
57
58#endif
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
new file mode 100644
index 00000000000..dae5e9b166e
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -0,0 +1,33 @@
1/*
2 *
3 * Copyright (C) 1999 ARM Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#include <mach/hardware.h>
23
24#define IO_SPACE_LIMIT 0xffffffff
25
26/*
27 * We don't actually have real ISA nor PCI buses, but there is so many
28 * drivers out there that might just work if we fake them...
29 */
30#define __io(a) __typesafe_io(a)
31#define __mem_pci(a) (a)
32
33#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
new file mode 100644
index 00000000000..b279b825d4a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/irqs.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright (C) 2007 Broadcom
3 * Copyright (C) 1999 ARM Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(ARCH_BCMRING_IRQS_H)
21#define ARCH_BCMRING_IRQS_H
22
23/* INTC0 - interrupt controller 0 */
24#define IRQ_INTC0_START 0
25#define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */
26#define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */
27#define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */
28#define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */
29#define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */
30#define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */
31#define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */
32#define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */
33#define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */
34#define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */
35#define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */
36#define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */
37#define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */
38#define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */
39#define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */
40#define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */
41#define IRQ_VPM 16 /* Voice process module interrupt */
42#define IRQ_USBHD2 17 /* USB host2/device2 interrupt */
43#define IRQ_USBH1 18 /* USB1 host interrupt */
44#define IRQ_USBD 19 /* USB device interrupt */
45#define IRQ_SDIOH0 20 /* SDIO0 host interrupt */
46#define IRQ_SDIOH1 21 /* SDIO1 host interrupt */
47#define IRQ_TIMER0 22 /* Timer0 interrupt */
48#define IRQ_TIMER1 23 /* Timer1 interrupt */
49#define IRQ_TIMER2 24 /* Timer2 interrupt */
50#define IRQ_TIMER3 25 /* Timer3 interrupt */
51#define IRQ_SPIH 26 /* SPI host interrupt */
52#define IRQ_ESW 27 /* Ethernet switch interrupt */
53#define IRQ_APM 28 /* Audio process module interrupt */
54#define IRQ_GE 29 /* Graphic engine interrupt */
55#define IRQ_CLCD 30 /* LCD Controller interrupt */
56#define IRQ_PIF 31 /* Peripheral interface interrupt */
57#define IRQ_INTC0_END 31
58
59/* INTC1 - interrupt controller 1 */
60#define IRQ_INTC1_START 32
61#define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */
62#define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */
63#define IRQ_I2S0 34 /* 2 I2S0 interrupt */
64#define IRQ_I2S1 35 /* 3 I2S1 interrupt */
65#define IRQ_I2CH 36 /* 4 I2C host interrupt */
66#define IRQ_I2CS 37 /* 5 I2C slave interrupt */
67#define IRQ_SPIS 38 /* 6 SPI slave interrupt */
68#define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */
69#define IRQ_FLASHC 40 /* 8 Flash controller interrupt */
70#define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */
71#define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */
72#define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */
73#define IRQ_UARTB 44 /* 12 UARTB */
74#define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */
75#define IRQ_UARTA 46 /* 14 UARTA */
76#define IRQ_TSC 47 /* 15 Touch screen controller interrupt */
77#define IRQ_KEYC 48 /* 16 Key pad controller interrupt */
78#define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */
79#define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */
80#define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */
81#define IRQ_RNG 52 /* 20 Random number generator interrupt */
82#define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */
83#define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */
84#define IRQ_SPUM 55 /* 23 Secure process module interrupt */
85#define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */
86#define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */
87#define IRQ_DDRP 58 /* 26 DDR Panic interrupt */
88#define IRQ_INTC1_END 58
89
90/* SINTC secure int controller */
91#define IRQ_SINTC_START 59
92#define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */
93#define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */
94#define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */
95#define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */
96#define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */
97#define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */
98#define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */
99#define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */
100#define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */
101#define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */
102#define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */
103#define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */
104#define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */
105#define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */
106#define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */
107#define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */
108
109#define IRQ_SINTC_END 74
110
111/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
112/* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
113/* to make the mapping easy for humans to decipher. */
114
115#define IRQ_GPIO_0 100
116
117#define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1)
118
119/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
120/* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */
121#define NUM_GPIO_IRQS 62
122
123#define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS)
124
125#define IRQ_UNKNOWN -1
126
127/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
128#define IRQ_INTC0_VALID_MASK 0xffffffff
129#define IRQ_INTC1_VALID_MASK 0x07ffffff
130#define IRQ_SINTC_VALID_MASK 0x0000ffff
131
132#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
new file mode 100644
index 00000000000..15162e4c75f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory.h
@@ -0,0 +1,33 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef __ASM_ARCH_MEMORY_H
16#define __ASM_ARCH_MEMORY_H
17
18#include <cfg_global.h>
19
20/*
21 * Physical vs virtual RAM address space conversion. These are
22 * private definitions which should NOT be used outside memory.h
23 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
24 */
25
26#define PLAT_PHYS_OFFSET CFG_GLOBAL_RAM_BASE
27
28/*
29 * Maximum DMA memory allowed is 14M
30 */
31#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
32
33#endif
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
new file mode 100644
index 00000000000..ce5cd16f2ac
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory_settings.h
@@ -0,0 +1,67 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef MEMORY_SETTINGS_H
16#define MEMORY_SETTINGS_H
17
18/* ---- Include Files ---------------------------------------- */
19/* ---- Constants and Types ---------------------------------- */
20
21/* Memory devices */
22/* NAND Flash timing for 166 MHz setting */
23#define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */
24#define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */
25#define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */
26#define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */
27#define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */
28#define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */
29
30#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
31 | HW_CFG_NAND_tWP \
32 | HW_CFG_NAND_tWR \
33 | HW_CFG_NAND_tAS \
34 | HW_CFG_NAND_tOE \
35 | HW_CFG_NAND_tRC)
36
37/* NOR Flash timing for 166 MHz setting */
38#define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
39#define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */
40#define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */
41#define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */
42#define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */
43#define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */
44#define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */
45
46#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
47 | HW_CFG_NOR_TBTA \
48 | HW_CFG_NOR_TWP \
49 | HW_CFG_NOR_TWR \
50 | HW_CFG_NOR_TAS \
51 | HW_CFG_NOR_TOE \
52 | HW_CFG_NOR_TRC_TLC)
53
54#define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR
55#define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR
56
57/* SDRAM Settings */
58/* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */
59/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */
60/* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */
61/* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */
62#define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */
63
64/* ---- Variable Externs ------------------------------------- */
65/* ---- Function Prototypes ---------------------------------- */
66
67#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
new file mode 100644
index 00000000000..387376ffb56
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h
@@ -0,0 +1,66 @@
1/*****************************************************************************
2* Copyright 2001 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16*
17*****************************************************************************
18*
19* REG_NAND.h
20*
21* PURPOSE:
22*
23* This file contains definitions for the nand registers:
24*
25* NOTES:
26*
27*****************************************************************************/
28
29#if !defined(__ASM_ARCH_REG_NAND_H)
30#define __ASM_ARCH_REG_NAND_H
31
32/* ---- Include Files ---------------------------------------------------- */
33#include <csp/reg.h>
34#include <mach/reg_umi.h>
35
36/* ---- Constants and Types ---------------------------------------------- */
37
38#define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */
39
40/* DMA accesses by the bootstrap need hard nonvirtual addresses */
41#define REG_NAND_CMD __REG16(HW_NAND_BASE + 0)
42#define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4)
43
44#define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8)
45#define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8)
46#define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16)
47#define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8)
48
49/* use appropriate offset to make sure it start at the 1K boundary */
50#define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400)
51#define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA)
52
53/* Linux DMA requires physical address of the data register */
54#define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
55#define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
56#define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
57
58#define NAND_BUS_16BIT() (0)
59#define NAND_BUS_8BIT() (!NAND_BUS_16BIT())
60
61/* Register offsets */
62#define REG_NAND_CMD_OFFSET (0)
63#define REG_NAND_ADDR_OFFSET (4)
64#define REG_NAND_DATA8_OFFSET (8)
65
66#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
new file mode 100644
index 00000000000..0992842caa7
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -0,0 +1,237 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16*
17*****************************************************************************
18*
19* REG_UMI.h
20*
21* PURPOSE:
22*
23* This file contains definitions for the nand registers:
24*
25* NOTES:
26*
27*****************************************************************************/
28
29#if !defined(__ASM_ARCH_REG_UMI_H)
30#define __ASM_ARCH_REG_UMI_H
31
32/* ---- Include Files ---------------------------------------------------- */
33#include <csp/reg.h>
34#include <mach/csp/mm_io.h>
35
36/* ---- Constants and Types ---------------------------------------------- */
37
38/* Unified Memory Interface Ctrl Register */
39#define HW_UMI_BASE MM_IO_BASE_UMI
40
41/* Flash bank 0 timing and control register */
42#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00)
43/* Flash bank 1 timing and control register */
44#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04)
45/* Flash bank 2 timing and control register */
46#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08)
47/* MMD interface and control register */
48#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c)
49/* NAND timing and control register */
50#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18)
51/* NAND ready/chip select register */
52#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c)
53/* NAND ECC control & status register */
54#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20)
55/* NAND ECC data register XXB2B1B0 */
56#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24)
57/* BCH ECC Parameter N */
58#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40)
59/* BCH ECC Parameter T */
60#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44)
61/* BCH ECC Parameter K */
62#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48)
63/* BCH ECC Contro Status */
64#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C)
65/* BCH WR ECC 31:0 */
66#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50)
67/* BCH WR ECC 63:32 */
68#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54)
69/* BCH WR ECC 95:64 */
70#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58)
71/* BCH WR ECC 127:96 */
72#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c)
73/* BCH WR ECC 155:128 */
74#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60)
75/* BCH Read Error Location 1,0 */
76#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64)
77/* BCH Read Error Location 3,2 */
78#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68)
79/* BCH Read Error Location 5,4 */
80#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c)
81/* BCH Read Error Location 7,6 */
82#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70)
83/* BCH Read Error Location 9,8 */
84#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74)
85/* BCH Read Error Location 11,10 */
86#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78)
87
88/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
89/* Enable wait pin during burst write or read */
90#define REG_UMI_TCR_WAITEN 0x80000000
91/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
92#define REG_UMI_TCR_LOWFREQ 0x40000000
93/* 1=synch write, 0=async write */
94#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000
95/* 1=synch read, 0=async read */
96#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000
97/* 1=page mode read, 0=normal mode read */
98#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000
99/* page size/burst size (wrap only) */
100#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000
101/* 4 word */
102#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000
103/* 8 word */
104#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000
105/* 16 word */
106#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000
107/* 32 word */
108#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000
109/* 64 word */
110#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000
111/* 128 word */
112#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000
113/* 256 word */
114#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000
115/* 512 word */
116#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000
117/* Page read access cycle / Burst write latency (n+2 / n+1) */
118#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000
119/* Bus turnaround cycle (n) */
120#define REG_UMI_TCR_TBTA_MASK 0x00070000
121/* Write pulse width cycle (n+1) */
122#define REG_UMI_TCR_TWP_MASK 0x0000f800
123/* Write recovery cycle (n+1) */
124#define REG_UMI_TCR_TWR_MASK 0x00000600
125/* Write address setup cycle (n+1) */
126#define REG_UMI_TCR_TAS_MASK 0x00000180
127/* Output enable delay cycle (n) */
128#define REG_UMI_TCR_TOE_MASK 0x00000060
129/* Read access cycle / Burst read latency (n+2 / n+1) */
130#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f
131
132/* REG_UMI_MMD_ICR bits */
133/* Flash write protection pin control */
134#define REG_UMI_MMD_ICR_FLASH_WP 0x8000
135/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
136#define REG_UMI_MMD_ICR_XHCS 0x4000
137/* Enable SDRAM 2 interface control */
138#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000
139/* Enable merge of flash banks 0/1 to 512 MBit bank */
140#define REG_UMI_MMD_ICR_INST512 0x1000
141/* Enable merge of flash banks 1/2 to 512 MBit bank */
142#define REG_UMI_MMD_ICR_DATA512 0x0800
143/* Enable SDRAM interface control */
144#define REG_UMI_MMD_ICR_SDRAMEN 0x0400
145/* Polarity of busy state of Burst Wait Signal */
146#define REG_UMI_MMD_ICR_WAITPOL 0x0200
147/* Enable burst clock stopped when not accessing external burst flash/sram */
148#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100
149/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
150#define REG_UMI_MMD_ICR_PERI1EN 0x0080
151/* Enable the peri2_csn to replace sdram_csn */
152#define REG_UMI_MMD_ICR_PERI2EN 0x0040
153/* Enable the peri3_csn to replace sdram2_csn */
154#define REG_UMI_MMD_ICR_PERI3EN 0x0020
155/* Enable sram bank1 for H/W controlled MRS */
156#define REG_UMI_MMD_ICR_MRSB1 0x0010
157/* Enable sram bank0 for H/W controlled MRS */
158#define REG_UMI_MMD_ICR_MRSB0 0x0008
159/* Polarity for assert3ed state of H/W controlled MRS */
160#define REG_UMI_MMD_ICR_MRSPOL 0x0004
161/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
162/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
163#define REG_UMI_MMD_ICR_MRSMODE 0x0002
164/* MRS state for S/W controlled mode */
165#define REG_UMI_MMD_ICR_MRSSTATE 0x0001
166
167/* REG_UMI_NAND_TCR bits */
168/* Enable software to control CS */
169#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000
170/* 16-bit nand wordsize if set */
171#define REG_UMI_NAND_TCR_WORD16 0x40000000
172/* Bus turnaround cycle (n) */
173#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000
174/* Write pulse width cycle (n+1) */
175#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800
176/* Write recovery cycle (n+1) */
177#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600
178/* Write address setup cycle (n+1) */
179#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180
180/* Output enable delay cycle (n) */
181#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060
182/* Read access cycle (n+2) */
183#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f
184
185/* REG_UMI_NAND_RCSR bits */
186/* Status: Ready=1, Busy=0 */
187#define REG_UMI_NAND_RCSR_RDY 0x02
188/* Keep CS asserted during operation */
189#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01
190
191/* REG_UMI_NAND_ECC_CSR bits */
192/* Interrupt status - read-only */
193#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000
194/* Read: Status of ECC done, Write: clear ECC interrupt */
195#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000
196/* Read: Status of R/B, Write: clear R/B interrupt */
197#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000
198/* 1 = Enable ECC Interrupt */
199#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000
200/* 1 = Assert interrupt at rising edge of R/B_ */
201#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000
202/* Calculate ECC by 0=512 bytes, 1=256 bytes */
203#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080
204/* Enable ECC in hardware */
205#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001
206
207/* REG_UMI_BCH_CTRL_STATUS bits */
208/* Shift to Indicate Number of correctable errors detected */
209#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
210/* Indicate Number of correctable errors detected */
211#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
212/* Indicate Errors detected during read but uncorrectable */
213#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000
214/* Indicate Errors detected during read and are correctable */
215#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000
216/* Flag indicates BCH's ECC status of read process are valid */
217#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000
218/* Flag indicates BCH's ECC status of write process are valid */
219#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000
220/* Pause ECC calculation */
221#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
222/* Enable Interrupt */
223#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004
224/* Enable ECC during read */
225#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002
226/* Enable ECC during write */
227#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001
228/* Mask for location */
229#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF
230/* location within a byte */
231#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007
232/* location within a word */
233#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
234/* location within a page (512 byte) */
235#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
236#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
237#endif
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
new file mode 100644
index 00000000000..38b37060d42
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/system.h
@@ -0,0 +1,54 @@
1/*
2 *
3 * Copyright (C) 1999 ARM Limited
4 * Copyright (C) 2000 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_SYSTEM_H
21#define __ASM_ARCH_SYSTEM_H
22
23#include <mach/csp/chipcHw_inline.h>
24
25extern int bcmring_arch_warm_reboot;
26
27static inline void arch_idle(void)
28{
29 cpu_do_idle();
30}
31
32static inline void arch_reset(char mode, const char *cmd)
33{
34 printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
35
36 if (mode == 'h') {
37 /* Reboot configured in proc entry */
38 if (bcmring_arch_warm_reboot) {
39 printk("warm reset\n");
40 /* Issue Warm reset (do not reset ethernet switch, keep alive) */
41 chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
42 } else {
43 /* Force reset of everything */
44 printk("force reset\n");
45 chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
46 }
47 } else {
48 /* Force reset of everything */
49 printk("force reset\n");
50 chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
51 }
52}
53
54#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
new file mode 100644
index 00000000000..5a94bbb032b
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/timer.h
@@ -0,0 +1,77 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/*
16*
17*****************************************************************************
18*
19* timer.h
20*
21* PURPOSE:
22*
23*
24*
25* NOTES:
26*
27*****************************************************************************/
28
29#if !defined(BCM_LINUX_TIMER_H)
30#define BCM_LINUX_TIMER_H
31
32#if defined(__KERNEL__)
33
34/* ---- Include Files ---------------------------------------------------- */
35/* ---- Constants and Types ---------------------------------------------- */
36
37typedef unsigned int timer_tick_count_t;
38typedef unsigned int timer_tick_rate_t;
39typedef unsigned int timer_msec_t;
40
41/* ---- Variable Externs ------------------------------------------------- */
42/* ---- Function Prototypes ---------------------------------------------- */
43
44/****************************************************************************
45*
46* timer_get_tick_count
47*
48*
49***************************************************************************/
50timer_tick_count_t timer_get_tick_count(void);
51
52/****************************************************************************
53*
54* timer_get_tick_rate
55*
56*
57***************************************************************************/
58timer_tick_rate_t timer_get_tick_rate(void);
59
60/****************************************************************************
61*
62* timer_get_msec
63*
64*
65***************************************************************************/
66timer_msec_t timer_get_msec(void);
67
68/****************************************************************************
69*
70* timer_ticks_to_msec
71*
72*
73***************************************************************************/
74timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
75
76#endif /* __KERNEL__ */
77#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
new file mode 100644
index 00000000000..40d033ec589
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/timex.h
@@ -0,0 +1,25 @@
1/*
2 *
3 * Integrator architecture timex specifications
4 *
5 * Copyright (C) 1999 ARM Limited
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * Specifies the number of ticks per second
24 */
25#define CLOCK_TICK_RATE 100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
new file mode 100644
index 00000000000..9c9821b7797
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/uncompress.h
@@ -0,0 +1,43 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14#include <mach/csp/mm_addr.h>
15
16#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
17#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
18/*
19 * This does not append a newline
20 */
21static inline void putc(int c)
22{
23 /* Send out UARTA */
24 while (BCMRING_UART_0_FR & (1 << 5))
25 ;
26
27 BCMRING_UART_0_DR = c;
28}
29
30
31static inline void flush(void)
32{
33 /* Wait for the tx fifo to be empty */
34 while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
35 ;
36
37 /* Wait for the final character to be sent on the txd line */
38 while (BCMRING_UART_0_FR & (1 << 3))
39 ;
40}
41
42#define arch_decomp_setup()
43#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
new file mode 100644
index 00000000000..7397bd7817d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -0,0 +1,25 @@
1/*
2 *
3 * Copyright (C) 2000 Russell King.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/*
21 * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
22 * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
23 * larger physical memory designs better.
24 */
25#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
new file mode 100644
index 00000000000..c48feaf4e8e
--- /dev/null
+++ b/arch/arm/mach-bcmring/irq.c
@@ -0,0 +1,127 @@
1/*
2 *
3 * Copyright (C) 1999 ARM Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/stddef.h>
21#include <linux/list.h>
22#include <linux/timer.h>
23#include <linux/version.h>
24#include <linux/io.h>
25
26#include <mach/hardware.h>
27#include <asm/irq.h>
28
29#include <asm/mach/irq.h>
30#include <mach/csp/intcHw_reg.h>
31#include <mach/csp/mm_io.h>
32
33static void bcmring_mask_irq0(struct irq_data *d)
34{
35 writel(1 << (d->irq - IRQ_INTC0_START),
36 MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
37}
38
39static void bcmring_unmask_irq0(struct irq_data *d)
40{
41 writel(1 << (d->irq - IRQ_INTC0_START),
42 MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
43}
44
45static void bcmring_mask_irq1(struct irq_data *d)
46{
47 writel(1 << (d->irq - IRQ_INTC1_START),
48 MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
49}
50
51static void bcmring_unmask_irq1(struct irq_data *d)
52{
53 writel(1 << (d->irq - IRQ_INTC1_START),
54 MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
55}
56
57static void bcmring_mask_irq2(struct irq_data *d)
58{
59 writel(1 << (d->irq - IRQ_SINTC_START),
60 MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
61}
62
63static void bcmring_unmask_irq2(struct irq_data *d)
64{
65 writel(1 << (d->irq - IRQ_SINTC_START),
66 MM_IO_BASE_SINTC + INTCHW_INTENABLE);
67}
68
69static struct irq_chip bcmring_irq0_chip = {
70 .name = "ARM-INTC0",
71 .irq_ack = bcmring_mask_irq0,
72 .irq_mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */
73 .irq_unmask = bcmring_unmask_irq0, /* unmaks an interrupt */
74};
75
76static struct irq_chip bcmring_irq1_chip = {
77 .name = "ARM-INTC1",
78 .irq_ack = bcmring_mask_irq1,
79 .irq_mask = bcmring_mask_irq1,
80 .irq_unmask = bcmring_unmask_irq1,
81};
82
83static struct irq_chip bcmring_irq2_chip = {
84 .name = "ARM-SINTC",
85 .irq_ack = bcmring_mask_irq2,
86 .irq_mask = bcmring_mask_irq2,
87 .irq_unmask = bcmring_unmask_irq2,
88};
89
90static void vic_init(void __iomem *base, struct irq_chip *chip,
91 unsigned int irq_start, unsigned int vic_sources)
92{
93 unsigned int i;
94 for (i = 0; i < 32; i++) {
95 unsigned int irq = irq_start + i;
96 irq_set_chip(irq, chip);
97 irq_set_chip_data(irq, base);
98
99 if (vic_sources & (1 << i)) {
100 irq_set_handler(irq, handle_level_irq);
101 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
102 }
103 }
104 writel(0, base + INTCHW_INTSELECT);
105 writel(0, base + INTCHW_INTENABLE);
106 writel(~0, base + INTCHW_INTENCLEAR);
107 writel(0, base + INTCHW_IRQSTATUS);
108 writel(~0, base + INTCHW_SOFTINTCLEAR);
109}
110
111void __init bcmring_init_irq(void)
112{
113 vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
114 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
115 vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
116 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
117 vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
118 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
119
120 /* special cases */
121 if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
122 irq_set_handler(IRQ_GPIO0, handle_simple_irq);
123 }
124 if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
125 irq_set_handler(IRQ_GPIO1, handle_simple_irq);
126 }
127}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
new file mode 100644
index 00000000000..0f1c37e4523
--- /dev/null
+++ b/arch/arm/mach-bcmring/mm.c
@@ -0,0 +1,56 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/platform_device.h>
16#include <asm/mach/map.h>
17
18#include <mach/hardware.h>
19#include <mach/csp/mm_io.h>
20
21#define IO_DESC(va, sz) { .virtual = va, \
22 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
23 .length = sz, \
24 .type = MT_DEVICE }
25
26#define MEM_DESC(va, sz) { .virtual = va, \
27 .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
28 .length = sz, \
29 .type = MT_MEMORY }
30
31static struct map_desc bcmring_io_desc[] __initdata = {
32 IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */
33 IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */
34
35 IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */
36 MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */
37 IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */
38 IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */
39 IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */
40 IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */
41 IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */
42 IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */
43 IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */
44 IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */
45
46 IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */
47 IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */
48 IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
49 SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */
50};
51
52void __init bcmring_map_io(void)
53{
54
55 iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
56}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
new file mode 100644
index 00000000000..2d415d2a8e6
--- /dev/null
+++ b/arch/arm/mach-bcmring/timer.c
@@ -0,0 +1,62 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#include <linux/version.h>
16#include <linux/types.h>
17#include <linux/module.h>
18#include <csp/tmrHw.h>
19
20#include <mach/timer.h>
21/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
22/* The real time clock should probably be the real linux clocksource. */
23/* In the meantime, this file should agree with core.c as to the */
24/* profiling timer. If the clocksource is moved to rtc later, then */
25/* we can init the profiling timer here instead. */
26
27/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
28/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
29/* affect synchronization with scheduling and APM timing. */
30
31#define PROF_TIMER 1
32
33timer_tick_rate_t timer_get_tick_rate(void)
34{
35 return tmrHw_getCountRate(PROF_TIMER);
36}
37
38timer_tick_count_t timer_get_tick_count(void)
39{
40 return tmrHw_GetCurrentCount(PROF_TIMER); /* change downcounter to upcounter */
41}
42
43timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
44{
45 static int tickRateMsec;
46
47 if (tickRateMsec == 0) {
48 tickRateMsec = timer_get_tick_rate() / 1000;
49 }
50
51 return ticks / tickRateMsec;
52}
53
54timer_msec_t timer_get_msec(void)
55{
56 return timer_ticks_to_msec(timer_get_tick_count());
57}
58
59EXPORT_SYMBOL(timer_get_tick_count);
60EXPORT_SYMBOL(timer_ticks_to_msec);
61EXPORT_SYMBOL(timer_get_tick_rate);
62EXPORT_SYMBOL(timer_get_msec);