diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-05-02 13:11:25 -0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-07-28 11:07:28 -0400 |
| commit | 1ff5b1b411bf8a8157ae949a1b3ed8666d96c1db (patch) | |
| tree | e323223c27e8070412f47f9ae09e62cbc2edf71d /arch/arm/mach-at91/include/mach/debug-macro.S | |
| parent | 92100c12ca1bc5f347ff41c1413f9db07c4d276c (diff) | |
at91: remove AT91_DBGU offset from dbgu register macro
to make the soc base specified at runtime instead of compiled time
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/debug-macro.S')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/debug-macro.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S index 0f959faf74a..bc1e0b2e2f4 100644 --- a/arch/arm/mach-at91/include/mach/debug-macro.S +++ b/arch/arm/mach-at91/include/mach/debug-macro.S | |||
| @@ -15,23 +15,23 @@ | |||
| 15 | #include <mach/at91_dbgu.h> | 15 | #include <mach/at91_dbgu.h> |
| 16 | 16 | ||
| 17 | .macro addruart, rp, rv | 17 | .macro addruart, rp, rv |
| 18 | ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) | 18 | ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) |
| 19 | ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) | 19 | ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) |
| 20 | .endm | 20 | .endm |
| 21 | 21 | ||
| 22 | .macro senduart,rd,rx | 22 | .macro senduart,rd,rx |
| 23 | strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register | 23 | strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register |
| 24 | .endm | 24 | .endm |
| 25 | 25 | ||
| 26 | .macro waituart,rd,rx | 26 | .macro waituart,rd,rx |
| 27 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | 27 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register |
| 28 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit | 28 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit |
| 29 | beq 1001b | 29 | beq 1001b |
| 30 | .endm | 30 | .endm |
| 31 | 31 | ||
| 32 | .macro busyuart,rd,rx | 32 | .macro busyuart,rd,rx |
| 33 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | 33 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register |
| 34 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete | 34 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete |
| 35 | beq 1001b | 35 | beq 1001b |
| 36 | .endm | 36 | .endm |
| 37 | 37 | ||