Merge branch 'depends/rmk/devel-stable' into next/cleanup

10 files changed, 105 insertions, 45 deletions

diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 7a21d0bf713..7f27fab9d40 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -205,6 +205,13 @@ extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
 int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
                 void *, dma_addr_t, size_t);
 
+/*
+ * This can be called during boot to increase the size of the consistent
+ * DMA region above it's default value of 2MB. It must be called before the
+ * memory allocator is initialised, i.e. before any core_initcall.
+ */
+extern void __init init_consistent_dma_size(unsigned long size);
+
 
 #ifdef CONFIG_DMABOUNCE
 /*
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 435d3f86c70..c5627057b1c 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -46,6 +46,14 @@ struct gic_chip_data {
         unsigned int irq_offset;
         void __iomem *dist_base;
         void __iomem *cpu_base;
+#ifdef CONFIG_CPU_PM
+        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+        u32 __percpu *saved_ppi_enable;
+        u32 __percpu *saved_ppi_conf;
+#endif
+        unsigned int gic_irqs;
 };
 #endif
 
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index f389b2704d8..c190bc992f0 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -50,6 +50,7 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DEBUG_ARCH_V6_1     2
 #define ARM_DEBUG_ARCH_V7_ECP14 3
 #define ARM_DEBUG_ARCH_V7_MM    4
+#define ARM_DEBUG_ARCH_V7_1     5
 
 /* Breakpoint */
 #define ARM_BREAKPOINT_EXECUTE  0
@@ -57,6 +58,7 @@ static inline void decode_ctrl_reg(u32 reg,
 /* Watchpoints */
 #define ARM_BREAKPOINT_LOAD     1
 #define ARM_BREAKPOINT_STORE    2
+#define ARM_FSR_ACCESS_MASK     (1 << 11)
 
 /* Privilege Levels */
 #define ARM_BREAKPOINT_PRIV     1
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 217aa1911dd..727da118bcc 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -17,7 +17,7 @@ struct sys_timer;
 struct machine_desc {
         unsigned int            nr;             /* architecture number  */
         const char              *name;          /* architecture name    */
-        unsigned long           boot_params;    /* tagged list          */
+        unsigned long           atag_offset;    /* tagged list (relative) */
         const char              **dt_compat;    /* array of device tree
                                                  * 'compatible' strings */
 
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index d2fedb5aeb1..b36f3654bf5 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -29,6 +29,7 @@ struct map_desc {
 #define MT_MEMORY_NONCACHED     11
 #define MT_MEMORY_DTCM          12
 #define MT_MEMORY_ITCM          13
+#define MT_MEMORY_SO            14
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index b8de516e600..652fccca495 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -77,16 +77,7 @@
  */
 #define IOREMAP_MAX_ORDER       24
 
-/*
- * Size of DMA-consistent memory region.  Must be multiple of 2M,
- * between 2MB and 14MB inclusive.
- */
-#ifndef CONSISTENT_DMA_SIZE
-#define CONSISTENT_DMA_SIZE     SZ_2M
-#endif
-
 #define CONSISTENT_END          (0xffe00000UL)
-#define CONSISTENT_BASE         (CONSISTENT_END - CONSISTENT_DMA_SIZE)
 
 #else /* CONFIG_MMU */
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 5750704e027..f1956b27ae5 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -232,6 +232,9 @@ extern pgprot_t		pgprot_kernel;
 #define pgprot_writecombine(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
 
+#define pgprot_stronglyordered(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
+
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define pgprot_dmacoherent(prot) \
         __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index b7e82c4aced..71d99b83cdb 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -13,7 +13,12 @@
 #define __ARM_PMU_H__
 
 #include <linux/interrupt.h>
+#include <linux/perf_event.h>
 
+/*
+ * Types of PMUs that can be accessed directly and require mutual
+ * exclusion between profiling tools.
+ */
 enum arm_pmu_type {
         ARM_PMU_DEVICE_CPU      = 0,
         ARM_NUM_PMU_DEVICES,
@@ -37,21 +42,17 @@ struct arm_pmu_platdata {
  * reserve_pmu() - reserve the hardware performance counters
  *
  * Reserve the hardware performance counters in the system for exclusive use.
- * The platform_device for the system is returned on success, ERR_PTR()
- * encoded error on failure.
+ * Returns 0 on success or -EBUSY if the lock is already held.
  */
-extern struct platform_device *
+extern int
 reserve_pmu(enum arm_pmu_type type);
 
 /**
  * release_pmu() - Relinquish control of the performance counters
  *
  * Release the performance counters and allow someone else to use them.
- * Callers must have disabled the counters and released IRQs before calling
- * this. The platform_device returned from reserve_pmu() must be passed as
- * a cookie.
  */
-extern int
+extern void
 release_pmu(enum arm_pmu_type type);
 
 /**
@@ -68,24 +69,78 @@ init_pmu(enum arm_pmu_type type);
 
 #include <linux/err.h>
 
-static inline struct platform_device *
-reserve_pmu(enum arm_pmu_type type)
-{
-        return ERR_PTR(-ENODEV);
-}
-
 static inline int
-release_pmu(enum arm_pmu_type type)
+reserve_pmu(enum arm_pmu_type type)
 {
         return -ENODEV;
 }
 
-static inline int
-init_pmu(enum arm_pmu_type type)
-{
-        return -ENODEV;
-}
+static inline void
+release_pmu(enum arm_pmu_type type)     { }
 
 #endif /* CONFIG_CPU_HAS_PMU */
 
+#ifdef CONFIG_HW_PERF_EVENTS
+
+/* The events for a given PMU register set. */
+struct pmu_hw_events {
+        /*
+         * The events that are active on the PMU for the given index.
+         */
+        struct perf_event       **events;
+
+        /*
+         * A 1 bit for an index indicates that the counter is being used for
+         * an event. A 0 means that the counter can be used.
+         */
+        unsigned long           *used_mask;
+
+        /*
+         * Hardware lock to serialize accesses to PMU registers. Needed for the
+         * read/modify/write sequences.
+         */
+        raw_spinlock_t          pmu_lock;
+};
+
+struct arm_pmu {
+        struct pmu      pmu;
+        enum arm_perf_pmu_ids id;
+        enum arm_pmu_type type;
+        cpumask_t       active_irqs;
+        const char      *name;
+        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
+        void            (*enable)(struct hw_perf_event *evt, int idx);
+        void            (*disable)(struct hw_perf_event *evt, int idx);
+        int             (*get_event_idx)(struct pmu_hw_events *hw_events,
+                                         struct hw_perf_event *hwc);
+        int             (*set_event_filter)(struct hw_perf_event *evt,
+                                            struct perf_event_attr *attr);
+        u32             (*read_counter)(int idx);
+        void            (*write_counter)(int idx, u32 val);
+        void            (*start)(void);
+        void            (*stop)(void);
+        void            (*reset)(void *);
+        int             (*map_event)(struct perf_event *event);
+        int             num_events;
+        atomic_t        active_events;
+        struct mutex    reserve_mutex;
+        u64             max_period;
+        struct platform_device  *plat_device;
+        struct pmu_hw_events    *(*get_hw_events)(void);
+};
+
+#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
+
+int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+
+u64 armpmu_event_update(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx, int overflow);
+
+int armpmu_event_set_period(struct perf_event *event,
+                            struct hw_perf_event *hwc,
+                            int idx);
+
+#endif /* CONFIG_HW_PERF_EVENTS */
+
 #endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 633d1cb84d8..9e92cb205e6 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -81,6 +81,10 @@ extern void cpu_dcache_clean_area(void *, int);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
+
+/* These three are private to arch/arm/kernel/suspend.c */
+extern void cpu_do_suspend(void *);
+extern void cpu_do_resume(void *);
 #else
 #define cpu_proc_init                   processor._proc_init
 #define cpu_proc_fin                    processor._proc_fin
@@ -89,6 +93,10 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
 #define cpu_dcache_clean_area           processor.dcache_clean_area
 #define cpu_set_pte_ext                 processor.set_pte_ext
 #define cpu_do_switch_mm                processor.switch_mm
+
+/* These three are private to arch/arm/kernel/suspend.c */
+#define cpu_do_suspend                  processor.do_suspend
+#define cpu_do_resume                   processor.do_resume
 #endif
 
 extern void cpu_resume(void);
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index b0e4e1a0231..1c0a551ae37 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,22 +1,7 @@
 #ifndef __ASM_ARM_SUSPEND_H
 #define __ASM_ARM_SUSPEND_H
 
-#include <asm/memory.h>
-#include <asm/tlbflush.h>
-
 extern void cpu_resume(void);
-
-/*
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-        extern int __cpu_suspend(int, long, unsigned long,
-                                 int (*)(unsigned long));
-        int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
-        flush_tlb_all();
-        return ret;
-}
+extern int cpu_suspend(unsigned long, int (*)(unsigned long));
 
 #endif