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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 16:20:18 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 16:20:18 -0500
commit56012808f4d5606e401539f663d92009d964425b (patch)
treef3736a97725647393a2db7c95462d857115197ca /arch/arm/include
parenta814290e17ae314bd614476cffc6119846eca27e (diff)
parentb2a731aa5cbca7e0252da75e16de7ae5feb1313a (diff)
Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stable
Conflicts: arch/arm/Makefile
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/cacheflush.h20
1 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 730aefcfbee..c77d2fa1f6e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -154,16 +154,16 @@
154 * Please note that the implementation of these, and the required 154 * Please note that the implementation of these, and the required
155 * effects are cache-type (VIVT/VIPT/PIPT) specific. 155 * effects are cache-type (VIVT/VIPT/PIPT) specific.
156 * 156 *
157 * flush_cache_kern_all() 157 * flush_kern_all()
158 * 158 *
159 * Unconditionally clean and invalidate the entire cache. 159 * Unconditionally clean and invalidate the entire cache.
160 * 160 *
161 * flush_cache_user_mm(mm) 161 * flush_user_all()
162 * 162 *
163 * Clean and invalidate all user space cache entries 163 * Clean and invalidate all user space cache entries
164 * before a change of page tables. 164 * before a change of page tables.
165 * 165 *
166 * flush_cache_user_range(start, end, flags) 166 * flush_user_range(start, end, flags)
167 * 167 *
168 * Clean and invalidate a range of cache entries in the 168 * Clean and invalidate a range of cache entries in the
169 * specified address space before a change of page tables. 169 * specified address space before a change of page tables.
@@ -179,6 +179,20 @@
179 * - start - virtual start address 179 * - start - virtual start address
180 * - end - virtual end address 180 * - end - virtual end address
181 * 181 *
182 * coherent_user_range(start, end)
183 *
184 * Ensure coherency between the Icache and the Dcache in the
185 * region described by start, end. If you have non-snooping
186 * Harvard caches, you need to implement this function.
187 * - start - virtual start address
188 * - end - virtual end address
189 *
190 * flush_kern_dcache_area(kaddr, size)
191 *
192 * Ensure that the data held in page is written back.
193 * - kaddr - page address
194 * - size - region size
195 *
182 * DMA Cache Coherency 196 * DMA Cache Coherency
183 * =================== 197 * ===================
184 * 198 *