diff options
author | Will Deacon <will.deacon@arm.com> | 2011-08-31 05:50:37 -0400 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2011-08-31 05:50:37 -0400 |
commit | 4fb0d2ea397ab207fdecbd88ad0e37b36ce68a62 (patch) | |
tree | f0ebe12652b7ad1c2fc5016dfb31b633b7458a3f /arch/arm/include | |
parent | d12443363e590461655d4e9ccc31e40ad9078283 (diff) | |
parent | 7325eaec439cd0cc8c9b61b59d41d99abace1b23 (diff) |
Merge branches 'hwbreak', 'perf/updates' and 'perf/system-pmus' into for-rmk
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/pmu.h | 93 |
1 files changed, 74 insertions, 19 deletions
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h index b7e82c4aced..71d99b83cdb 100644 --- a/arch/arm/include/asm/pmu.h +++ b/arch/arm/include/asm/pmu.h | |||
@@ -13,7 +13,12 @@ | |||
13 | #define __ARM_PMU_H__ | 13 | #define __ARM_PMU_H__ |
14 | 14 | ||
15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
16 | #include <linux/perf_event.h> | ||
16 | 17 | ||
18 | /* | ||
19 | * Types of PMUs that can be accessed directly and require mutual | ||
20 | * exclusion between profiling tools. | ||
21 | */ | ||
17 | enum arm_pmu_type { | 22 | enum arm_pmu_type { |
18 | ARM_PMU_DEVICE_CPU = 0, | 23 | ARM_PMU_DEVICE_CPU = 0, |
19 | ARM_NUM_PMU_DEVICES, | 24 | ARM_NUM_PMU_DEVICES, |
@@ -37,21 +42,17 @@ struct arm_pmu_platdata { | |||
37 | * reserve_pmu() - reserve the hardware performance counters | 42 | * reserve_pmu() - reserve the hardware performance counters |
38 | * | 43 | * |
39 | * Reserve the hardware performance counters in the system for exclusive use. | 44 | * Reserve the hardware performance counters in the system for exclusive use. |
40 | * The platform_device for the system is returned on success, ERR_PTR() | 45 | * Returns 0 on success or -EBUSY if the lock is already held. |
41 | * encoded error on failure. | ||
42 | */ | 46 | */ |
43 | extern struct platform_device * | 47 | extern int |
44 | reserve_pmu(enum arm_pmu_type type); | 48 | reserve_pmu(enum arm_pmu_type type); |
45 | 49 | ||
46 | /** | 50 | /** |
47 | * release_pmu() - Relinquish control of the performance counters | 51 | * release_pmu() - Relinquish control of the performance counters |
48 | * | 52 | * |
49 | * Release the performance counters and allow someone else to use them. | 53 | * Release the performance counters and allow someone else to use them. |
50 | * Callers must have disabled the counters and released IRQs before calling | ||
51 | * this. The platform_device returned from reserve_pmu() must be passed as | ||
52 | * a cookie. | ||
53 | */ | 54 | */ |
54 | extern int | 55 | extern void |
55 | release_pmu(enum arm_pmu_type type); | 56 | release_pmu(enum arm_pmu_type type); |
56 | 57 | ||
57 | /** | 58 | /** |
@@ -68,24 +69,78 @@ init_pmu(enum arm_pmu_type type); | |||
68 | 69 | ||
69 | #include <linux/err.h> | 70 | #include <linux/err.h> |
70 | 71 | ||
71 | static inline struct platform_device * | ||
72 | reserve_pmu(enum arm_pmu_type type) | ||
73 | { | ||
74 | return ERR_PTR(-ENODEV); | ||
75 | } | ||
76 | |||
77 | static inline int | 72 | static inline int |
78 | release_pmu(enum arm_pmu_type type) | 73 | reserve_pmu(enum arm_pmu_type type) |
79 | { | 74 | { |
80 | return -ENODEV; | 75 | return -ENODEV; |
81 | } | 76 | } |
82 | 77 | ||
83 | static inline int | 78 | static inline void |
84 | init_pmu(enum arm_pmu_type type) | 79 | release_pmu(enum arm_pmu_type type) { } |
85 | { | ||
86 | return -ENODEV; | ||
87 | } | ||
88 | 80 | ||
89 | #endif /* CONFIG_CPU_HAS_PMU */ | 81 | #endif /* CONFIG_CPU_HAS_PMU */ |
90 | 82 | ||
83 | #ifdef CONFIG_HW_PERF_EVENTS | ||
84 | |||
85 | /* The events for a given PMU register set. */ | ||
86 | struct pmu_hw_events { | ||
87 | /* | ||
88 | * The events that are active on the PMU for the given index. | ||
89 | */ | ||
90 | struct perf_event **events; | ||
91 | |||
92 | /* | ||
93 | * A 1 bit for an index indicates that the counter is being used for | ||
94 | * an event. A 0 means that the counter can be used. | ||
95 | */ | ||
96 | unsigned long *used_mask; | ||
97 | |||
98 | /* | ||
99 | * Hardware lock to serialize accesses to PMU registers. Needed for the | ||
100 | * read/modify/write sequences. | ||
101 | */ | ||
102 | raw_spinlock_t pmu_lock; | ||
103 | }; | ||
104 | |||
105 | struct arm_pmu { | ||
106 | struct pmu pmu; | ||
107 | enum arm_perf_pmu_ids id; | ||
108 | enum arm_pmu_type type; | ||
109 | cpumask_t active_irqs; | ||
110 | const char *name; | ||
111 | irqreturn_t (*handle_irq)(int irq_num, void *dev); | ||
112 | void (*enable)(struct hw_perf_event *evt, int idx); | ||
113 | void (*disable)(struct hw_perf_event *evt, int idx); | ||
114 | int (*get_event_idx)(struct pmu_hw_events *hw_events, | ||
115 | struct hw_perf_event *hwc); | ||
116 | int (*set_event_filter)(struct hw_perf_event *evt, | ||
117 | struct perf_event_attr *attr); | ||
118 | u32 (*read_counter)(int idx); | ||
119 | void (*write_counter)(int idx, u32 val); | ||
120 | void (*start)(void); | ||
121 | void (*stop)(void); | ||
122 | void (*reset)(void *); | ||
123 | int (*map_event)(struct perf_event *event); | ||
124 | int num_events; | ||
125 | atomic_t active_events; | ||
126 | struct mutex reserve_mutex; | ||
127 | u64 max_period; | ||
128 | struct platform_device *plat_device; | ||
129 | struct pmu_hw_events *(*get_hw_events)(void); | ||
130 | }; | ||
131 | |||
132 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) | ||
133 | |||
134 | int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); | ||
135 | |||
136 | u64 armpmu_event_update(struct perf_event *event, | ||
137 | struct hw_perf_event *hwc, | ||
138 | int idx, int overflow); | ||
139 | |||
140 | int armpmu_event_set_period(struct perf_event *event, | ||
141 | struct hw_perf_event *hwc, | ||
142 | int idx); | ||
143 | |||
144 | #endif /* CONFIG_HW_PERF_EVENTS */ | ||
145 | |||
91 | #endif /* __ARM_PMU_H__ */ | 146 | #endif /* __ARM_PMU_H__ */ |