aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2012-03-16 09:03:23 -0400
committerArnd Bergmann <arnd@arndb.de>2012-03-16 16:19:41 -0400
commit9652e8bd16e73f7a34cabf1ab114aaa5c97db660 (patch)
tree5dc349178f64ef83fe3f2aed87d475b733e513e6 /arch/arm/boot
parentfde7d9049e55ab85a390be7f415d74c9f62dd0f9 (diff)
ARM: SPEAr600: Add device-tree support to SPEAr600 boards
This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree: - VIC interrupts - PL011 UART - PL061 GPIO - Synopsys DW I2C - Synopsys DW ethernet Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will follow in later patches. Only the spear600-evb is currently supported. Other SPEAr600 based boards will follow later. Since the current mainline SPEAr600 code only supports the SPEAr600 evaluation board, with nearly zero peripheral devices (only UART and GPIO), it makes sense to switch over to DT based configuration completely now. So this patch also removes all non-DT stuff, mainly platform device data. The files spear600.c and spear600_evb.c are removed completely. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/spear600-evb.dts47
-rw-r--r--arch/arm/boot/dts/spear600.dtsi174
2 files changed, 221 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 00000000000..636292e18c9
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,47 @@
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "spear600.dtsi"
14
15/ {
16 model = "ST SPEAr600 Evaluation Board";
17 compatible = "st,spear600-evb", "st,spear600";
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 memory {
22 device_type = "memory";
23 reg = <0 0x10000000>;
24 };
25
26 ahb {
27 gmac: ethernet@e0800000 {
28 phy-mode = "gmii";
29 status = "okay";
30 };
31
32 apb {
33 serial@d0000000 {
34 status = "okay";
35 };
36
37 serial@d0080000 {
38 status = "okay";
39 };
40
41 i2c@d0200000 {
42 clock-frequency = <400000>;
43 status = "okay";
44 };
45 };
46 };
47};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 00000000000..ebe0885a2b9
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,174 @@
1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "st,spear600";
16
17 cpus {
18 cpu@0 {
19 compatible = "arm,arm926ejs";
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x40000000>;
26 };
27
28 ahb {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 compatible = "simple-bus";
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
33
34 vic0: interrupt-controller@f1100000 {
35 compatible = "arm,pl190-vic";
36 interrupt-controller;
37 reg = <0xf1100000 0x1000>;
38 #interrupt-cells = <1>;
39 };
40
41 vic1: interrupt-controller@f1000000 {
42 compatible = "arm,pl190-vic";
43 interrupt-controller;
44 reg = <0xf1000000 0x1000>;
45 #interrupt-cells = <1>;
46 };
47
48 gmac: ethernet@e0800000 {
49 compatible = "st,spear600-gmac";
50 reg = <0xe0800000 0x8000>;
51 interrupt-parent = <&vic1>;
52 interrupts = <24 23>;
53 interrupt-names = "macirq", "eth_wake_irq";
54 status = "disabled";
55 };
56
57 fsmc: flash@d1800000 {
58 compatible = "st,spear600-fsmc-nand";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0xd1800000 0x1000 /* FSMC Register */
62 0xd2000000 0x4000>; /* NAND Base */
63 reg-names = "fsmc_regs", "nand_data";
64 st,ale-off = <0x20000>;
65 st,cle-off = <0x10000>;
66 status = "disabled";
67 };
68
69 smi: flash@fc000000 {
70 compatible = "st,spear600-smi";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 reg = <0xfc000000 0x1000>;
74 interrupt-parent = <&vic1>;
75 interrupts = <12>;
76 status = "disabled";
77 };
78
79 ehci@e1800000 {
80 compatible = "st,spear600-ehci", "usb-ehci";
81 reg = <0xe1800000 0x1000>;
82 interrupt-parent = <&vic1>;
83 interrupts = <27>;
84 status = "disabled";
85 };
86
87 ehci@e2000000 {
88 compatible = "st,spear600-ehci", "usb-ehci";
89 reg = <0xe2000000 0x1000>;
90 interrupt-parent = <&vic1>;
91 interrupts = <29>;
92 status = "disabled";
93 };
94
95 ohci@e1900000 {
96 compatible = "st,spear600-ohci", "usb-ohci";
97 reg = <0xe1900000 0x1000>;
98 interrupt-parent = <&vic1>;
99 interrupts = <26>;
100 status = "disabled";
101 };
102
103 ohci@e2100000 {
104 compatible = "st,spear600-ohci", "usb-ohci";
105 reg = <0xe2100000 0x1000>;
106 interrupt-parent = <&vic1>;
107 interrupts = <28>;
108 status = "disabled";
109 };
110
111 apb {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "simple-bus";
115 ranges = <0xd0000000 0xd0000000 0x30000000>;
116
117 serial@d0000000 {
118 compatible = "arm,pl011", "arm,primecell";
119 reg = <0xd0000000 0x1000>;
120 interrupt-parent = <&vic0>;
121 interrupts = <24>;
122 status = "disabled";
123 };
124
125 serial@d0080000 {
126 compatible = "arm,pl011", "arm,primecell";
127 reg = <0xd0080000 0x1000>;
128 interrupt-parent = <&vic0>;
129 interrupts = <25>;
130 status = "disabled";
131 };
132
133 /* local/cpu GPIO */
134 gpio0: gpio@f0100000 {
135 #gpio-cells = <2>;
136 compatible = "arm,pl061", "arm,primecell";
137 gpio-controller;
138 reg = <0xf0100000 0x1000>;
139 interrupt-parent = <&vic0>;
140 interrupts = <18>;
141 };
142
143 /* basic GPIO */
144 gpio1: gpio@fc980000 {
145 #gpio-cells = <2>;
146 compatible = "arm,pl061", "arm,primecell";
147 gpio-controller;
148 reg = <0xfc980000 0x1000>;
149 interrupt-parent = <&vic1>;
150 interrupts = <19>;
151 };
152
153 /* appl GPIO */
154 gpio2: gpio@d8100000 {
155 #gpio-cells = <2>;
156 compatible = "arm,pl061", "arm,primecell";
157 gpio-controller;
158 reg = <0xd8100000 0x1000>;
159 interrupt-parent = <&vic1>;
160 interrupts = <4>;
161 };
162
163 i2c@d0200000 {
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "snps,designware-i2c";
167 reg = <0xd0200000 0x1000>;
168 interrupt-parent = <&vic0>;
169 interrupts = <28>;
170 status = "disabled";
171 };
172 };
173 };
174};