aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2012-11-21 04:06:16 -0500
committerOlof Johansson <olof@lixom.net>2012-11-21 05:13:11 -0500
commit06f31cb0f601728f24b85c51972eee6bdc94a1d1 (patch)
tree5696c77fee6810740f6c8f650fbc2a133d293d9e /arch/arm/boot
parent17bffc78438d010c3e57ad5c1956e3ab50be423a (diff)
parent433683a66401adb0150792e725cc4f631c94de46 (diff)
Merge branch 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux into next/soc
From Pawel Moll: * 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux: ARM: vexpress: Remove motherboard dependencies in the DTS files ARM: vexpress: Start using new Versatile Express infrastructure ARM: vexpress: Add config bus components and clocks to DTs mfd: Versatile Express system registers driver mfd: Versatile Express config infrastructure
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi146
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi146
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts121
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts186
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts84
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts136
6 files changed, 789 insertions, 30 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827bd2bf..ac870fb3fa0 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -17,17 +17,16 @@
17 * CHANGES TO vexpress-v2m.dtsi! 17 * CHANGES TO vexpress-v2m.dtsi!
18 */ 18 */
19 19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard { 20 motherboard {
26 compatible = "simple-bus"; 21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
27 arm,v2m-memory-map = "rs1"; 24 arm,v2m-memory-map = "rs1";
25 compatible = "arm,vexpress,v2m-p1", "simple-bus";
28 #address-cells = <2>; /* SMB chipselect number and offset */ 26 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>; 27 #size-cells = <1>;
30 #interrupt-cells = <1>; 28 #interrupt-cells = <1>;
29 ranges;
31 30
32 flash@0,00000000 { 31 flash@0,00000000 {
33 compatible = "arm,vexpress-flash", "cfi-flash"; 32 compatible = "arm,vexpress-flash", "cfi-flash";
@@ -72,14 +71,20 @@
72 #size-cells = <1>; 71 #size-cells = <1>;
73 ranges = <0 3 0 0x200000>; 72 ranges = <0 3 0 0x200000>;
74 73
75 sysreg@010000 { 74 v2m_sysreg: sysreg@010000 {
76 compatible = "arm,vexpress-sysreg"; 75 compatible = "arm,vexpress-sysreg";
77 reg = <0x010000 0x1000>; 76 reg = <0x010000 0x1000>;
77 gpio-controller;
78 #gpio-cells = <2>;
78 }; 79 };
79 80
80 sysctl@020000 { 81 v2m_sysctl: sysctl@020000 {
81 compatible = "arm,sp810", "arm,primecell"; 82 compatible = "arm,sp810", "arm,primecell";
82 reg = <0x020000 0x1000>; 83 reg = <0x020000 0x1000>;
84 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
85 clock-names = "refclk", "timclk", "apb_pclk";
86 #clock-cells = <1>;
87 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
83 }; 88 };
84 89
85 /* PCI-E I2C bus */ 90 /* PCI-E I2C bus */
@@ -100,66 +105,92 @@
100 compatible = "arm,pl041", "arm,primecell"; 105 compatible = "arm,pl041", "arm,primecell";
101 reg = <0x040000 0x1000>; 106 reg = <0x040000 0x1000>;
102 interrupts = <11>; 107 interrupts = <11>;
108 clocks = <&smbclk>;
109 clock-names = "apb_pclk";
103 }; 110 };
104 111
105 mmci@050000 { 112 mmci@050000 {
106 compatible = "arm,pl180", "arm,primecell"; 113 compatible = "arm,pl180", "arm,primecell";
107 reg = <0x050000 0x1000>; 114 reg = <0x050000 0x1000>;
108 interrupts = <9 10>; 115 interrupts = <9 10>;
116 cd-gpios = <&v2m_sysreg 0 0>;
117 wp-gpios = <&v2m_sysreg 1 0>;
118 max-frequency = <12000000>;
119 vmmc-supply = <&v2m_fixed_3v3>;
120 clocks = <&v2m_clk24mhz>, <&smbclk>;
121 clock-names = "mclk", "apb_pclk";
109 }; 122 };
110 123
111 kmi@060000 { 124 kmi@060000 {
112 compatible = "arm,pl050", "arm,primecell"; 125 compatible = "arm,pl050", "arm,primecell";
113 reg = <0x060000 0x1000>; 126 reg = <0x060000 0x1000>;
114 interrupts = <12>; 127 interrupts = <12>;
128 clocks = <&v2m_clk24mhz>, <&smbclk>;
129 clock-names = "KMIREFCLK", "apb_pclk";
115 }; 130 };
116 131
117 kmi@070000 { 132 kmi@070000 {
118 compatible = "arm,pl050", "arm,primecell"; 133 compatible = "arm,pl050", "arm,primecell";
119 reg = <0x070000 0x1000>; 134 reg = <0x070000 0x1000>;
120 interrupts = <13>; 135 interrupts = <13>;
136 clocks = <&v2m_clk24mhz>, <&smbclk>;
137 clock-names = "KMIREFCLK", "apb_pclk";
121 }; 138 };
122 139
123 v2m_serial0: uart@090000 { 140 v2m_serial0: uart@090000 {
124 compatible = "arm,pl011", "arm,primecell"; 141 compatible = "arm,pl011", "arm,primecell";
125 reg = <0x090000 0x1000>; 142 reg = <0x090000 0x1000>;
126 interrupts = <5>; 143 interrupts = <5>;
144 clocks = <&v2m_oscclk2>, <&smbclk>;
145 clock-names = "uartclk", "apb_pclk";
127 }; 146 };
128 147
129 v2m_serial1: uart@0a0000 { 148 v2m_serial1: uart@0a0000 {
130 compatible = "arm,pl011", "arm,primecell"; 149 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x0a0000 0x1000>; 150 reg = <0x0a0000 0x1000>;
132 interrupts = <6>; 151 interrupts = <6>;
152 clocks = <&v2m_oscclk2>, <&smbclk>;
153 clock-names = "uartclk", "apb_pclk";
133 }; 154 };
134 155
135 v2m_serial2: uart@0b0000 { 156 v2m_serial2: uart@0b0000 {
136 compatible = "arm,pl011", "arm,primecell"; 157 compatible = "arm,pl011", "arm,primecell";
137 reg = <0x0b0000 0x1000>; 158 reg = <0x0b0000 0x1000>;
138 interrupts = <7>; 159 interrupts = <7>;
160 clocks = <&v2m_oscclk2>, <&smbclk>;
161 clock-names = "uartclk", "apb_pclk";
139 }; 162 };
140 163
141 v2m_serial3: uart@0c0000 { 164 v2m_serial3: uart@0c0000 {
142 compatible = "arm,pl011", "arm,primecell"; 165 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x0c0000 0x1000>; 166 reg = <0x0c0000 0x1000>;
144 interrupts = <8>; 167 interrupts = <8>;
168 clocks = <&v2m_oscclk2>, <&smbclk>;
169 clock-names = "uartclk", "apb_pclk";
145 }; 170 };
146 171
147 wdt@0f0000 { 172 wdt@0f0000 {
148 compatible = "arm,sp805", "arm,primecell"; 173 compatible = "arm,sp805", "arm,primecell";
149 reg = <0x0f0000 0x1000>; 174 reg = <0x0f0000 0x1000>;
150 interrupts = <0>; 175 interrupts = <0>;
176 clocks = <&v2m_refclk32khz>, <&smbclk>;
177 clock-names = "wdogclk", "apb_pclk";
151 }; 178 };
152 179
153 v2m_timer01: timer@110000 { 180 v2m_timer01: timer@110000 {
154 compatible = "arm,sp804", "arm,primecell"; 181 compatible = "arm,sp804", "arm,primecell";
155 reg = <0x110000 0x1000>; 182 reg = <0x110000 0x1000>;
156 interrupts = <2>; 183 interrupts = <2>;
184 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
185 clock-names = "timclken1", "timclken2", "apb_pclk";
157 }; 186 };
158 187
159 v2m_timer23: timer@120000 { 188 v2m_timer23: timer@120000 {
160 compatible = "arm,sp804", "arm,primecell"; 189 compatible = "arm,sp804", "arm,primecell";
161 reg = <0x120000 0x1000>; 190 reg = <0x120000 0x1000>;
162 interrupts = <3>; 191 interrupts = <3>;
192 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
193 clock-names = "timclken1", "timclken2", "apb_pclk";
163 }; 194 };
164 195
165 /* DVI I2C bus */ 196 /* DVI I2C bus */
@@ -185,6 +216,8 @@
185 compatible = "arm,pl031", "arm,primecell"; 216 compatible = "arm,pl031", "arm,primecell";
186 reg = <0x170000 0x1000>; 217 reg = <0x170000 0x1000>;
187 interrupts = <4>; 218 interrupts = <4>;
219 clocks = <&smbclk>;
220 clock-names = "apb_pclk";
188 }; 221 };
189 222
190 compact-flash@1a0000 { 223 compact-flash@1a0000 {
@@ -198,6 +231,8 @@
198 compatible = "arm,pl111", "arm,primecell"; 231 compatible = "arm,pl111", "arm,primecell";
199 reg = <0x1f0000 0x1000>; 232 reg = <0x1f0000 0x1000>;
200 interrupts = <14>; 233 interrupts = <14>;
234 clocks = <&v2m_oscclk1>, <&smbclk>;
235 clock-names = "clcdclk", "apb_pclk";
201 }; 236 };
202 }; 237 };
203 238
@@ -208,5 +243,98 @@
208 regulator-max-microvolt = <3300000>; 243 regulator-max-microvolt = <3300000>;
209 regulator-always-on; 244 regulator-always-on;
210 }; 245 };
246
247 v2m_clk24mhz: clk24mhz {
248 compatible = "fixed-clock";
249 #clock-cells = <0>;
250 clock-frequency = <24000000>;
251 clock-output-names = "v2m:clk24mhz";
252 };
253
254 v2m_refclk1mhz: refclk1mhz {
255 compatible = "fixed-clock";
256 #clock-cells = <0>;
257 clock-frequency = <1000000>;
258 clock-output-names = "v2m:refclk1mhz";
259 };
260
261 v2m_refclk32khz: refclk32khz {
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <32768>;
265 clock-output-names = "v2m:refclk32khz";
266 };
267
268 mcc {
269 compatible = "arm,vexpress,config-bus";
270 arm,vexpress,config-bridge = <&v2m_sysreg>;
271
272 osc@0 {
273 /* MCC static memory clock */
274 compatible = "arm,vexpress-osc";
275 arm,vexpress-sysreg,func = <1 0>;
276 freq-range = <25000000 60000000>;
277 #clock-cells = <0>;
278 clock-output-names = "v2m:oscclk0";
279 };
280
281 v2m_oscclk1: osc@1 {
282 /* CLCD clock */
283 compatible = "arm,vexpress-osc";
284 arm,vexpress-sysreg,func = <1 1>;
285 freq-range = <23750000 63500000>;
286 #clock-cells = <0>;
287 clock-output-names = "v2m:oscclk1";
288 };
289
290 v2m_oscclk2: osc@2 {
291 /* IO FPGA peripheral clock */
292 compatible = "arm,vexpress-osc";
293 arm,vexpress-sysreg,func = <1 2>;
294 freq-range = <24000000 24000000>;
295 #clock-cells = <0>;
296 clock-output-names = "v2m:oscclk2";
297 };
298
299 volt@0 {
300 /* Logic level voltage */
301 compatible = "arm,vexpress-volt";
302 arm,vexpress-sysreg,func = <2 0>;
303 regulator-name = "VIO";
304 regulator-always-on;
305 label = "VIO";
306 };
307
308 temp@0 {
309 /* MCC internal operating temperature */
310 compatible = "arm,vexpress-temp";
311 arm,vexpress-sysreg,func = <4 0>;
312 label = "MCC";
313 };
314
315 reset@0 {
316 compatible = "arm,vexpress-reset";
317 arm,vexpress-sysreg,func = <5 0>;
318 };
319
320 muxfpga@0 {
321 compatible = "arm,vexpress-muxfpga";
322 arm,vexpress-sysreg,func = <7 0>;
323 };
324
325 shutdown@0 {
326 compatible = "arm,vexpress-shutdown";
327 arm,vexpress-sysreg,func = <8 0>;
328 };
329
330 reboot@0 {
331 compatible = "arm,vexpress-reboot";
332 arm,vexpress-sysreg,func = <9 0>;
333 };
334
335 dvimode@0 {
336 compatible = "arm,vexpress-dvimode";
337 arm,vexpress-sysreg,func = <11 0>;
338 };
339 };
211 }; 340 };
212};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index dba53fd026b..f1420368355 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -17,16 +17,15 @@
17 * CHANGES TO vexpress-v2m-rs1.dtsi! 17 * CHANGES TO vexpress-v2m-rs1.dtsi!
18 */ 18 */
19 19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard { 20 motherboard {
26 compatible = "simple-bus"; 21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
24 compatible = "arm,vexpress,v2m-p1", "simple-bus";
27 #address-cells = <2>; /* SMB chipselect number and offset */ 25 #address-cells = <2>; /* SMB chipselect number and offset */
28 #size-cells = <1>; 26 #size-cells = <1>;
29 #interrupt-cells = <1>; 27 #interrupt-cells = <1>;
28 ranges;
30 29
31 flash@0,00000000 { 30 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash"; 31 compatible = "arm,vexpress-flash", "cfi-flash";
@@ -71,14 +70,20 @@
71 #size-cells = <1>; 70 #size-cells = <1>;
72 ranges = <0 7 0 0x20000>; 71 ranges = <0 7 0 0x20000>;
73 72
74 sysreg@00000 { 73 v2m_sysreg: sysreg@00000 {
75 compatible = "arm,vexpress-sysreg"; 74 compatible = "arm,vexpress-sysreg";
76 reg = <0x00000 0x1000>; 75 reg = <0x00000 0x1000>;
76 gpio-controller;
77 #gpio-cells = <2>;
77 }; 78 };
78 79
79 sysctl@01000 { 80 v2m_sysctl: sysctl@01000 {
80 compatible = "arm,sp810", "arm,primecell"; 81 compatible = "arm,sp810", "arm,primecell";
81 reg = <0x01000 0x1000>; 82 reg = <0x01000 0x1000>;
83 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
84 clock-names = "refclk", "timclk", "apb_pclk";
85 #clock-cells = <1>;
86 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
82 }; 87 };
83 88
84 /* PCI-E I2C bus */ 89 /* PCI-E I2C bus */
@@ -99,66 +104,92 @@
99 compatible = "arm,pl041", "arm,primecell"; 104 compatible = "arm,pl041", "arm,primecell";
100 reg = <0x04000 0x1000>; 105 reg = <0x04000 0x1000>;
101 interrupts = <11>; 106 interrupts = <11>;
107 clocks = <&smbclk>;
108 clock-names = "apb_pclk";
102 }; 109 };
103 110
104 mmci@05000 { 111 mmci@05000 {
105 compatible = "arm,pl180", "arm,primecell"; 112 compatible = "arm,pl180", "arm,primecell";
106 reg = <0x05000 0x1000>; 113 reg = <0x05000 0x1000>;
107 interrupts = <9 10>; 114 interrupts = <9 10>;
115 cd-gpios = <&v2m_sysreg 0 0>;
116 wp-gpios = <&v2m_sysreg 1 0>;
117 max-frequency = <12000000>;
118 vmmc-supply = <&v2m_fixed_3v3>;
119 clocks = <&v2m_clk24mhz>, <&smbclk>;
120 clock-names = "mclk", "apb_pclk";
108 }; 121 };
109 122
110 kmi@06000 { 123 kmi@06000 {
111 compatible = "arm,pl050", "arm,primecell"; 124 compatible = "arm,pl050", "arm,primecell";
112 reg = <0x06000 0x1000>; 125 reg = <0x06000 0x1000>;
113 interrupts = <12>; 126 interrupts = <12>;
127 clocks = <&v2m_clk24mhz>, <&smbclk>;
128 clock-names = "KMIREFCLK", "apb_pclk";
114 }; 129 };
115 130
116 kmi@07000 { 131 kmi@07000 {
117 compatible = "arm,pl050", "arm,primecell"; 132 compatible = "arm,pl050", "arm,primecell";
118 reg = <0x07000 0x1000>; 133 reg = <0x07000 0x1000>;
119 interrupts = <13>; 134 interrupts = <13>;
135 clocks = <&v2m_clk24mhz>, <&smbclk>;
136 clock-names = "KMIREFCLK", "apb_pclk";
120 }; 137 };
121 138
122 v2m_serial0: uart@09000 { 139 v2m_serial0: uart@09000 {
123 compatible = "arm,pl011", "arm,primecell"; 140 compatible = "arm,pl011", "arm,primecell";
124 reg = <0x09000 0x1000>; 141 reg = <0x09000 0x1000>;
125 interrupts = <5>; 142 interrupts = <5>;
143 clocks = <&v2m_oscclk2>, <&smbclk>;
144 clock-names = "uartclk", "apb_pclk";
126 }; 145 };
127 146
128 v2m_serial1: uart@0a000 { 147 v2m_serial1: uart@0a000 {
129 compatible = "arm,pl011", "arm,primecell"; 148 compatible = "arm,pl011", "arm,primecell";
130 reg = <0x0a000 0x1000>; 149 reg = <0x0a000 0x1000>;
131 interrupts = <6>; 150 interrupts = <6>;
151 clocks = <&v2m_oscclk2>, <&smbclk>;
152 clock-names = "uartclk", "apb_pclk";
132 }; 153 };
133 154
134 v2m_serial2: uart@0b000 { 155 v2m_serial2: uart@0b000 {
135 compatible = "arm,pl011", "arm,primecell"; 156 compatible = "arm,pl011", "arm,primecell";
136 reg = <0x0b000 0x1000>; 157 reg = <0x0b000 0x1000>;
137 interrupts = <7>; 158 interrupts = <7>;
159 clocks = <&v2m_oscclk2>, <&smbclk>;
160 clock-names = "uartclk", "apb_pclk";
138 }; 161 };
139 162
140 v2m_serial3: uart@0c000 { 163 v2m_serial3: uart@0c000 {
141 compatible = "arm,pl011", "arm,primecell"; 164 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x0c000 0x1000>; 165 reg = <0x0c000 0x1000>;
143 interrupts = <8>; 166 interrupts = <8>;
167 clocks = <&v2m_oscclk2>, <&smbclk>;
168 clock-names = "uartclk", "apb_pclk";
144 }; 169 };
145 170
146 wdt@0f000 { 171 wdt@0f000 {
147 compatible = "arm,sp805", "arm,primecell"; 172 compatible = "arm,sp805", "arm,primecell";
148 reg = <0x0f000 0x1000>; 173 reg = <0x0f000 0x1000>;
149 interrupts = <0>; 174 interrupts = <0>;
175 clocks = <&v2m_refclk32khz>, <&smbclk>;
176 clock-names = "wdogclk", "apb_pclk";
150 }; 177 };
151 178
152 v2m_timer01: timer@11000 { 179 v2m_timer01: timer@11000 {
153 compatible = "arm,sp804", "arm,primecell"; 180 compatible = "arm,sp804", "arm,primecell";
154 reg = <0x11000 0x1000>; 181 reg = <0x11000 0x1000>;
155 interrupts = <2>; 182 interrupts = <2>;
183 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
184 clock-names = "timclken1", "timclken2", "apb_pclk";
156 }; 185 };
157 186
158 v2m_timer23: timer@12000 { 187 v2m_timer23: timer@12000 {
159 compatible = "arm,sp804", "arm,primecell"; 188 compatible = "arm,sp804", "arm,primecell";
160 reg = <0x12000 0x1000>; 189 reg = <0x12000 0x1000>;
161 interrupts = <3>; 190 interrupts = <3>;
191 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
192 clock-names = "timclken1", "timclken2", "apb_pclk";
162 }; 193 };
163 194
164 /* DVI I2C bus */ 195 /* DVI I2C bus */
@@ -184,6 +215,8 @@
184 compatible = "arm,pl031", "arm,primecell"; 215 compatible = "arm,pl031", "arm,primecell";
185 reg = <0x17000 0x1000>; 216 reg = <0x17000 0x1000>;
186 interrupts = <4>; 217 interrupts = <4>;
218 clocks = <&smbclk>;
219 clock-names = "apb_pclk";
187 }; 220 };
188 221
189 compact-flash@1a000 { 222 compact-flash@1a000 {
@@ -197,6 +230,8 @@
197 compatible = "arm,pl111", "arm,primecell"; 230 compatible = "arm,pl111", "arm,primecell";
198 reg = <0x1f000 0x1000>; 231 reg = <0x1f000 0x1000>;
199 interrupts = <14>; 232 interrupts = <14>;
233 clocks = <&v2m_oscclk1>, <&smbclk>;
234 clock-names = "clcdclk", "apb_pclk";
200 }; 235 };
201 }; 236 };
202 237
@@ -207,5 +242,98 @@
207 regulator-max-microvolt = <3300000>; 242 regulator-max-microvolt = <3300000>;
208 regulator-always-on; 243 regulator-always-on;
209 }; 244 };
245
246 v2m_clk24mhz: clk24mhz {
247 compatible = "fixed-clock";
248 #clock-cells = <0>;
249 clock-frequency = <24000000>;
250 clock-output-names = "v2m:clk24mhz";
251 };
252
253 v2m_refclk1mhz: refclk1mhz {
254 compatible = "fixed-clock";
255 #clock-cells = <0>;
256 clock-frequency = <1000000>;
257 clock-output-names = "v2m:refclk1mhz";
258 };
259
260 v2m_refclk32khz: refclk32khz {
261 compatible = "fixed-clock";
262 #clock-cells = <0>;
263 clock-frequency = <32768>;
264 clock-output-names = "v2m:refclk32khz";
265 };
266
267 mcc {
268 compatible = "arm,vexpress,config-bus";
269 arm,vexpress,config-bridge = <&v2m_sysreg>;
270
271 osc@0 {
272 /* MCC static memory clock */
273 compatible = "arm,vexpress-osc";
274 arm,vexpress-sysreg,func = <1 0>;
275 freq-range = <25000000 60000000>;
276 #clock-cells = <0>;
277 clock-output-names = "v2m:oscclk0";
278 };
279
280 v2m_oscclk1: osc@1 {
281 /* CLCD clock */
282 compatible = "arm,vexpress-osc";
283 arm,vexpress-sysreg,func = <1 1>;
284 freq-range = <23750000 63500000>;
285 #clock-cells = <0>;
286 clock-output-names = "v2m:oscclk1";
287 };
288
289 v2m_oscclk2: osc@2 {
290 /* IO FPGA peripheral clock */
291 compatible = "arm,vexpress-osc";
292 arm,vexpress-sysreg,func = <1 2>;
293 freq-range = <24000000 24000000>;
294 #clock-cells = <0>;
295 clock-output-names = "v2m:oscclk2";
296 };
297
298 volt@0 {
299 /* Logic level voltage */
300 compatible = "arm,vexpress-volt";
301 arm,vexpress-sysreg,func = <2 0>;
302 regulator-name = "VIO";
303 regulator-always-on;
304 label = "VIO";
305 };
306
307 temp@0 {
308 /* MCC internal operating temperature */
309 compatible = "arm,vexpress-temp";
310 arm,vexpress-sysreg,func = <4 0>;
311 label = "MCC";
312 };
313
314 reset@0 {
315 compatible = "arm,vexpress-reset";
316 arm,vexpress-sysreg,func = <5 0>;
317 };
318
319 muxfpga@0 {
320 compatible = "arm,vexpress-muxfpga";
321 arm,vexpress-sysreg,func = <7 0>;
322 };
323
324 shutdown@0 {
325 compatible = "arm,vexpress-shutdown";
326 arm,vexpress-sysreg,func = <8 0>;
327 };
328
329 reboot@0 {
330 compatible = "arm,vexpress-reboot";
331 arm,vexpress-sysreg,func = <9 0>;
332 };
333
334 dvimode@0 {
335 compatible = "arm,vexpress-dvimode";
336 arm,vexpress-sysreg,func = <11 0>;
337 };
338 };
210 }; 339 };
211};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34ca056..a3d37ec2655 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA15"; 13 model = "V2P-CA15";
14 arm,hbi = <0x237>; 14 arm,hbi = <0x237>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <2>; 18 #address-cells = <2>;
@@ -54,17 +55,24 @@
54 compatible = "arm,hdlcd"; 55 compatible = "arm,hdlcd";
55 reg = <0 0x2b000000 0 0x1000>; 56 reg = <0 0x2b000000 0 0x1000>;
56 interrupts = <0 85 4>; 57 interrupts = <0 85 4>;
58 clocks = <&oscclk5>;
59 clock-names = "pxlclk";
57 }; 60 };
58 61
59 memory-controller@2b0a0000 { 62 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell"; 63 compatible = "arm,pl341", "arm,primecell";
61 reg = <0 0x2b0a0000 0 0x1000>; 64 reg = <0 0x2b0a0000 0 0x1000>;
65 clocks = <&oscclk7>;
66 clock-names = "apb_pclk";
62 }; 67 };
63 68
64 wdt@2b060000 { 69 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell"; 70 compatible = "arm,sp805", "arm,primecell";
71 status = "disabled";
66 reg = <0 0x2b060000 0 0x1000>; 72 reg = <0 0x2b060000 0 0x1000>;
67 interrupts = <98>; 73 interrupts = <98>;
74 clocks = <&oscclk7>;
75 clock-names = "apb_pclk";
68 }; 76 };
69 77
70 gic: interrupt-controller@2c001000 { 78 gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@
84 reg = <0 0x7ffd0000 0 0x1000>; 92 reg = <0 0x7ffd0000 0 0x1000>;
85 interrupts = <0 86 4>, 93 interrupts = <0 86 4>,
86 <0 87 4>; 94 <0 87 4>;
95 clocks = <&oscclk7>;
96 clock-names = "apb_pclk";
87 }; 97 };
88 98
89 dma@7ffb0000 { 99 dma@7ffb0000 {
@@ -94,6 +104,8 @@
94 <0 89 4>, 104 <0 89 4>,
95 <0 90 4>, 105 <0 90 4>,
96 <0 91 4>; 106 <0 91 4>;
107 clocks = <&oscclk7>;
108 clock-names = "apb_pclk";
97 }; 109 };
98 110
99 timer { 111 timer {
@@ -110,7 +122,109 @@
110 <0 69 4>; 122 <0 69 4>;
111 }; 123 };
112 124
113 motherboard { 125 dcc {
126 compatible = "arm,vexpress,config-bus";
127 arm,vexpress,config-bridge = <&v2m_sysreg>;
128
129 osc@0 {
130 /* CPU PLL reference clock */
131 compatible = "arm,vexpress-osc";
132 arm,vexpress-sysreg,func = <1 0>;
133 freq-range = <50000000 60000000>;
134 #clock-cells = <0>;
135 clock-output-names = "oscclk0";
136 };
137
138 osc@4 {
139 /* Multiplexed AXI master clock */
140 compatible = "arm,vexpress-osc";
141 arm,vexpress-sysreg,func = <1 4>;
142 freq-range = <20000000 40000000>;
143 #clock-cells = <0>;
144 clock-output-names = "oscclk4";
145 };
146
147 oscclk5: osc@5 {
148 /* HDLCD PLL reference clock */
149 compatible = "arm,vexpress-osc";
150 arm,vexpress-sysreg,func = <1 5>;
151 freq-range = <23750000 165000000>;
152 #clock-cells = <0>;
153 clock-output-names = "oscclk5";
154 };
155
156 smbclk: osc@6 {
157 /* SMB clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 6>;
160 freq-range = <20000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk6";
163 };
164
165 oscclk7: osc@7 {
166 /* SYS PLL reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 7>;
169 freq-range = <20000000 60000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk7";
172 };
173
174 osc@8 {
175 /* DDR2 PLL reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 8>;
178 freq-range = <40000000 40000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk8";
181 };
182
183 volt@0 {
184 /* CPU core voltage */
185 compatible = "arm,vexpress-volt";
186 arm,vexpress-sysreg,func = <2 0>;
187 regulator-name = "Cores";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1050000>;
190 regulator-always-on;
191 label = "Cores";
192 };
193
194 amp@0 {
195 /* Total current for the two cores */
196 compatible = "arm,vexpress-amp";
197 arm,vexpress-sysreg,func = <3 0>;
198 label = "Cores";
199 };
200
201 temp@0 {
202 /* DCC internal temperature */
203 compatible = "arm,vexpress-temp";
204 arm,vexpress-sysreg,func = <4 0>;
205 label = "DCC";
206 };
207
208 power@0 {
209 /* Total power */
210 compatible = "arm,vexpress-power";
211 arm,vexpress-sysreg,func = <12 0>;
212 label = "Cores";
213 };
214
215 energy@0 {
216 /* Total energy */
217 compatible = "arm,vexpress-energy";
218 arm,vexpress-sysreg,func = <13 0>;
219 label = "Cores";
220 };
221 };
222
223 smb {
224 compatible = "simple-bus";
225
226 #address-cells = <2>;
227 #size-cells = <1>;
114 ranges = <0 0 0 0x08000000 0x04000000>, 228 ranges = <0 0 0 0x08000000 0x04000000>,
115 <1 0 0 0x14000000 0x04000000>, 229 <1 0 0 0x14000000 0x04000000>,
116 <2 0 0 0x18000000 0x04000000>, 230 <2 0 0 0x18000000 0x04000000>,
@@ -118,6 +232,7 @@
118 <4 0 0 0x0c000000 0x04000000>, 232 <4 0 0 0x0c000000 0x04000000>,
119 <5 0 0 0x10000000 0x04000000>; 233 <5 0 0 0x10000000 0x04000000>;
120 234
235 #interrupt-cells = <1>;
121 interrupt-map-mask = <0 0 63>; 236 interrupt-map-mask = <0 0 63>;
122 interrupt-map = <0 0 0 &gic 0 0 4>, 237 interrupt-map = <0 0 0 &gic 0 0 4>,
123 <0 0 1 &gic 0 1 4>, 238 <0 0 1 &gic 0 1 4>,
@@ -162,7 +277,7 @@
162 <0 0 40 &gic 0 40 4>, 277 <0 0 40 &gic 0 40 4>,
163 <0 0 41 &gic 0 41 4>, 278 <0 0 41 &gic 0 41 4>,
164 <0 0 42 &gic 0 42 4>; 279 <0 0 42 &gic 0 42 4>;
280
281 /include/ "vexpress-v2m-rs1.dtsi"
165 }; 282 };
166}; 283};
167
168/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 4890a81c546..1fc405a9ecf 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA15_CA7"; 13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>; 14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <2>; 18 #address-cells = <2>;
@@ -74,17 +75,23 @@
74 compatible = "arm,sp805", "arm,primecell"; 75 compatible = "arm,sp805", "arm,primecell";
75 reg = <0 0x2a490000 0 0x1000>; 76 reg = <0 0x2a490000 0 0x1000>;
76 interrupts = <98>; 77 interrupts = <98>;
78 clocks = <&oscclk6a>, <&oscclk6a>;
79 clock-names = "wdogclk", "apb_pclk";
77 }; 80 };
78 81
79 hdlcd@2b000000 { 82 hdlcd@2b000000 {
80 compatible = "arm,hdlcd"; 83 compatible = "arm,hdlcd";
81 reg = <0 0x2b000000 0 0x1000>; 84 reg = <0 0x2b000000 0 0x1000>;
82 interrupts = <0 85 4>; 85 interrupts = <0 85 4>;
86 clocks = <&oscclk5>;
87 clock-names = "pxlclk";
83 }; 88 };
84 89
85 memory-controller@2b0a0000 { 90 memory-controller@2b0a0000 {
86 compatible = "arm,pl341", "arm,primecell"; 91 compatible = "arm,pl341", "arm,primecell";
87 reg = <0 0x2b0a0000 0 0x1000>; 92 reg = <0 0x2b0a0000 0 0x1000>;
93 clocks = <&oscclk6a>;
94 clock-names = "apb_pclk";
88 }; 95 };
89 96
90 gic: interrupt-controller@2c001000 { 97 gic: interrupt-controller@2c001000 {
@@ -104,6 +111,8 @@
104 reg = <0 0x7ffd0000 0 0x1000>; 111 reg = <0 0x7ffd0000 0 0x1000>;
105 interrupts = <0 86 4>, 112 interrupts = <0 86 4>,
106 <0 87 4>; 113 <0 87 4>;
114 clocks = <&oscclk6a>;
115 clock-names = "apb_pclk";
107 }; 116 };
108 117
109 dma@7ff00000 { 118 dma@7ff00000 {
@@ -114,6 +123,8 @@
114 <0 89 4>, 123 <0 89 4>,
115 <0 90 4>, 124 <0 90 4>,
116 <0 91 4>; 125 <0 91 4>;
126 clocks = <&oscclk6a>;
127 clock-names = "apb_pclk";
117 }; 128 };
118 129
119 timer { 130 timer {
@@ -130,7 +141,175 @@
130 <0 69 4>; 141 <0 69 4>;
131 }; 142 };
132 143
133 motherboard { 144 oscclk6a: oscclk6a {
145 /* Reference 24MHz clock */
146 compatible = "fixed-clock";
147 #clock-cells = <0>;
148 clock-frequency = <24000000>;
149 clock-output-names = "oscclk6a";
150 };
151
152 dcc {
153 compatible = "arm,vexpress,config-bus";
154 arm,vexpress,config-bridge = <&v2m_sysreg>;
155
156 osc@0 {
157 /* A15 PLL 0 reference clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 0>;
160 freq-range = <17000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk0";
163 };
164
165 osc@1 {
166 /* A15 PLL 1 reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 1>;
169 freq-range = <17000000 50000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk1";
172 };
173
174 osc@2 {
175 /* A7 PLL 0 reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 2>;
178 freq-range = <17000000 50000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk2";
181 };
182
183 osc@3 {
184 /* A7 PLL 1 reference clock */
185 compatible = "arm,vexpress-osc";
186 arm,vexpress-sysreg,func = <1 3>;
187 freq-range = <17000000 50000000>;
188 #clock-cells = <0>;
189 clock-output-names = "oscclk3";
190 };
191
192 osc@4 {
193 /* External AXI master clock */
194 compatible = "arm,vexpress-osc";
195 arm,vexpress-sysreg,func = <1 4>;
196 freq-range = <20000000 40000000>;
197 #clock-cells = <0>;
198 clock-output-names = "oscclk4";
199 };
200
201 oscclk5: osc@5 {
202 /* HDLCD PLL reference clock */
203 compatible = "arm,vexpress-osc";
204 arm,vexpress-sysreg,func = <1 5>;
205 freq-range = <23750000 165000000>;
206 #clock-cells = <0>;
207 clock-output-names = "oscclk5";
208 };
209
210 smbclk: osc@6 {
211 /* Static memory controller clock */
212 compatible = "arm,vexpress-osc";
213 arm,vexpress-sysreg,func = <1 6>;
214 freq-range = <20000000 40000000>;
215 #clock-cells = <0>;
216 clock-output-names = "oscclk6";
217 };
218
219 osc@7 {
220 /* SYS PLL reference clock */
221 compatible = "arm,vexpress-osc";
222 arm,vexpress-sysreg,func = <1 7>;
223 freq-range = <17000000 50000000>;
224 #clock-cells = <0>;
225 clock-output-names = "oscclk7";
226 };
227
228 osc@8 {
229 /* DDR2 PLL reference clock */
230 compatible = "arm,vexpress-osc";
231 arm,vexpress-sysreg,func = <1 8>;
232 freq-range = <20000000 50000000>;
233 #clock-cells = <0>;
234 clock-output-names = "oscclk8";
235 };
236
237 volt@0 {
238 /* A15 CPU core voltage */
239 compatible = "arm,vexpress-volt";
240 arm,vexpress-sysreg,func = <2 0>;
241 regulator-name = "A15 Vcore";
242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <1050000>;
244 regulator-always-on;
245 label = "A15 Vcore";
246 };
247
248 volt@1 {
249 /* A7 CPU core voltage */
250 compatible = "arm,vexpress-volt";
251 arm,vexpress-sysreg,func = <2 1>;
252 regulator-name = "A7 Vcore";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1050000>;
255 regulator-always-on;
256 label = "A7 Vcore";
257 };
258
259 amp@0 {
260 /* Total current for the two A15 cores */
261 compatible = "arm,vexpress-amp";
262 arm,vexpress-sysreg,func = <3 0>;
263 label = "A15 Icore";
264 };
265
266 amp@1 {
267 /* Total current for the three A7 cores */
268 compatible = "arm,vexpress-amp";
269 arm,vexpress-sysreg,func = <3 1>;
270 label = "A7 Icore";
271 };
272
273 temp@0 {
274 /* DCC internal temperature */
275 compatible = "arm,vexpress-temp";
276 arm,vexpress-sysreg,func = <4 0>;
277 label = "DCC";
278 };
279
280 power@0 {
281 /* Total power for the two A15 cores */
282 compatible = "arm,vexpress-power";
283 arm,vexpress-sysreg,func = <12 0>;
284 label = "A15 Pcore";
285 };
286 power@1 {
287 /* Total power for the three A7 cores */
288 compatible = "arm,vexpress-power";
289 arm,vexpress-sysreg,func = <12 1>;
290 label = "A7 Pcore";
291 };
292
293 energy@0 {
294 /* Total energy for the two A15 cores */
295 compatible = "arm,vexpress-energy";
296 arm,vexpress-sysreg,func = <13 0>;
297 label = "A15 Jcore";
298 };
299
300 energy@2 {
301 /* Total energy for the three A7 cores */
302 compatible = "arm,vexpress-energy";
303 arm,vexpress-sysreg,func = <13 2>;
304 label = "A7 Jcore";
305 };
306 };
307
308 smb {
309 compatible = "simple-bus";
310
311 #address-cells = <2>;
312 #size-cells = <1>;
134 ranges = <0 0 0 0x08000000 0x04000000>, 313 ranges = <0 0 0 0x08000000 0x04000000>,
135 <1 0 0 0x14000000 0x04000000>, 314 <1 0 0 0x14000000 0x04000000>,
136 <2 0 0 0x18000000 0x04000000>, 315 <2 0 0 0x18000000 0x04000000>,
@@ -138,6 +317,7 @@
138 <4 0 0 0x0c000000 0x04000000>, 317 <4 0 0 0x0c000000 0x04000000>,
139 <5 0 0 0x10000000 0x04000000>; 318 <5 0 0 0x10000000 0x04000000>;
140 319
320 #interrupt-cells = <1>;
141 interrupt-map-mask = <0 0 63>; 321 interrupt-map-mask = <0 0 63>;
142 interrupt-map = <0 0 0 &gic 0 0 4>, 322 interrupt-map = <0 0 0 &gic 0 0 4>,
143 <0 0 1 &gic 0 1 4>, 323 <0 0 1 &gic 0 1 4>,
@@ -182,7 +362,7 @@
182 <0 0 40 &gic 0 40 4>, 362 <0 0 40 &gic 0 40 4>,
183 <0 0 41 &gic 0 41 4>, 363 <0 0 41 &gic 0 41 4>,
184 <0 0 42 &gic 0 42 4>; 364 <0 0 42 &gic 0 42 4>;
365
366 /include/ "vexpress-v2m-rs1.dtsi"
185 }; 367 };
186}; 368};
187
188/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0f860..6328cbc71d3 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA5s"; 13 model = "V2P-CA5s";
14 arm,hbi = <0x225>; 14 arm,hbi = <0x225>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <1>; 18 #address-cells = <1>;
@@ -56,11 +57,15 @@
56 compatible = "arm,hdlcd"; 57 compatible = "arm,hdlcd";
57 reg = <0x2a110000 0x1000>; 58 reg = <0x2a110000 0x1000>;
58 interrupts = <0 85 4>; 59 interrupts = <0 85 4>;
60 clocks = <&oscclk3>;
61 clock-names = "pxlclk";
59 }; 62 };
60 63
61 memory-controller@2a150000 { 64 memory-controller@2a150000 {
62 compatible = "arm,pl341", "arm,primecell"; 65 compatible = "arm,pl341", "arm,primecell";
63 reg = <0x2a150000 0x1000>; 66 reg = <0x2a150000 0x1000>;
67 clocks = <&oscclk1>;
68 clock-names = "apb_pclk";
64 }; 69 };
65 70
66 memory-controller@2a190000 { 71 memory-controller@2a190000 {
@@ -68,6 +73,8 @@
68 reg = <0x2a190000 0x1000>; 73 reg = <0x2a190000 0x1000>;
69 interrupts = <0 86 4>, 74 interrupts = <0 86 4>,
70 <0 87 4>; 75 <0 87 4>;
76 clocks = <&oscclk1>;
77 clock-names = "apb_pclk";
71 }; 78 };
72 79
73 scu@2c000000 { 80 scu@2c000000 {
@@ -109,7 +116,77 @@
109 <0 69 4>; 116 <0 69 4>;
110 }; 117 };
111 118
112 motherboard { 119 dcc {
120 compatible = "arm,vexpress,config-bus";
121 arm,vexpress,config-bridge = <&v2m_sysreg>;
122
123 osc@0 {
124 /* CPU and internal AXI reference clock */
125 compatible = "arm,vexpress-osc";
126 arm,vexpress-sysreg,func = <1 0>;
127 freq-range = <50000000 100000000>;
128 #clock-cells = <0>;
129 clock-output-names = "oscclk0";
130 };
131
132 oscclk1: osc@1 {
133 /* Multiplexed AXI master clock */
134 compatible = "arm,vexpress-osc";
135 arm,vexpress-sysreg,func = <1 1>;
136 freq-range = <5000000 50000000>;
137 #clock-cells = <0>;
138 clock-output-names = "oscclk1";
139 };
140
141 osc@2 {
142 /* DDR2 */
143 compatible = "arm,vexpress-osc";
144 arm,vexpress-sysreg,func = <1 2>;
145 freq-range = <80000000 120000000>;
146 #clock-cells = <0>;
147 clock-output-names = "oscclk2";
148 };
149
150 oscclk3: osc@3 {
151 /* HDLCD */
152 compatible = "arm,vexpress-osc";
153 arm,vexpress-sysreg,func = <1 3>;
154 freq-range = <23750000 165000000>;
155 #clock-cells = <0>;
156 clock-output-names = "oscclk3";
157 };
158
159 osc@4 {
160 /* Test chip gate configuration */
161 compatible = "arm,vexpress-osc";
162 arm,vexpress-sysreg,func = <1 4>;
163 freq-range = <80000000 80000000>;
164 #clock-cells = <0>;
165 clock-output-names = "oscclk4";
166 };
167
168 smbclk: osc@5 {
169 /* SMB clock */
170 compatible = "arm,vexpress-osc";
171 arm,vexpress-sysreg,func = <1 5>;
172 freq-range = <25000000 60000000>;
173 #clock-cells = <0>;
174 clock-output-names = "oscclk5";
175 };
176
177 temp@0 {
178 /* DCC internal operating temperature */
179 compatible = "arm,vexpress-temp";
180 arm,vexpress-sysreg,func = <4 0>;
181 label = "DCC";
182 };
183 };
184
185 smb {
186 compatible = "simple-bus";
187
188 #address-cells = <2>;
189 #size-cells = <1>;
113 ranges = <0 0 0x08000000 0x04000000>, 190 ranges = <0 0 0x08000000 0x04000000>,
114 <1 0 0x14000000 0x04000000>, 191 <1 0 0x14000000 0x04000000>,
115 <2 0 0x18000000 0x04000000>, 192 <2 0 0x18000000 0x04000000>,
@@ -117,6 +194,7 @@
117 <4 0 0x0c000000 0x04000000>, 194 <4 0 0x0c000000 0x04000000>,
118 <5 0 0x10000000 0x04000000>; 195 <5 0 0x10000000 0x04000000>;
119 196
197 #interrupt-cells = <1>;
120 interrupt-map-mask = <0 0 63>; 198 interrupt-map-mask = <0 0 63>;
121 interrupt-map = <0 0 0 &gic 0 0 4>, 199 interrupt-map = <0 0 0 &gic 0 0 4>,
122 <0 0 1 &gic 0 1 4>, 200 <0 0 1 &gic 0 1 4>,
@@ -161,7 +239,7 @@
161 <0 0 40 &gic 0 40 4>, 239 <0 0 40 &gic 0 40 4>,
162 <0 0 41 &gic 0 41 4>, 240 <0 0 41 &gic 0 41 4>,
163 <0 0 42 &gic 0 42 4>; 241 <0 0 42 &gic 0 42 4>;
242
243 /include/ "vexpress-v2m-rs1.dtsi"
164 }; 244 };
165}; 245};
166
167/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736d31d..1420bb14d95 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA9"; 13 model = "V2P-CA9";
14 arm,hbi = <0x191>; 14 arm,hbi = <0x191>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <1>; 18 #address-cells = <1>;
@@ -70,11 +71,15 @@
70 compatible = "arm,pl111", "arm,primecell"; 71 compatible = "arm,pl111", "arm,primecell";
71 reg = <0x10020000 0x1000>; 72 reg = <0x10020000 0x1000>;
72 interrupts = <0 44 4>; 73 interrupts = <0 44 4>;
74 clocks = <&oscclk1>, <&oscclk2>;
75 clock-names = "clcdclk", "apb_pclk";
73 }; 76 };
74 77
75 memory-controller@100e0000 { 78 memory-controller@100e0000 {
76 compatible = "arm,pl341", "arm,primecell"; 79 compatible = "arm,pl341", "arm,primecell";
77 reg = <0x100e0000 0x1000>; 80 reg = <0x100e0000 0x1000>;
81 clocks = <&oscclk2>;
82 clock-names = "apb_pclk";
78 }; 83 };
79 84
80 memory-controller@100e1000 { 85 memory-controller@100e1000 {
@@ -82,6 +87,8 @@
82 reg = <0x100e1000 0x1000>; 87 reg = <0x100e1000 0x1000>;
83 interrupts = <0 45 4>, 88 interrupts = <0 45 4>,
84 <0 46 4>; 89 <0 46 4>;
90 clocks = <&oscclk2>;
91 clock-names = "apb_pclk";
85 }; 92 };
86 93
87 timer@100e4000 { 94 timer@100e4000 {
@@ -89,12 +96,16 @@
89 reg = <0x100e4000 0x1000>; 96 reg = <0x100e4000 0x1000>;
90 interrupts = <0 48 4>, 97 interrupts = <0 48 4>,
91 <0 49 4>; 98 <0 49 4>;
99 clocks = <&oscclk2>, <&oscclk2>;
100 clock-names = "timclk", "apb_pclk";
92 }; 101 };
93 102
94 watchdog@100e5000 { 103 watchdog@100e5000 {
95 compatible = "arm,sp805", "arm,primecell"; 104 compatible = "arm,sp805", "arm,primecell";
96 reg = <0x100e5000 0x1000>; 105 reg = <0x100e5000 0x1000>;
97 interrupts = <0 51 4>; 106 interrupts = <0 51 4>;
107 clocks = <&oscclk2>, <&oscclk2>;
108 clock-names = "wdogclk", "apb_pclk";
98 }; 109 };
99 110
100 scu@1e000000 { 111 scu@1e000000 {
@@ -140,13 +151,132 @@
140 <0 63 4>; 151 <0 63 4>;
141 }; 152 };
142 153
143 motherboard { 154 dcc {
155 compatible = "arm,vexpress,config-bus";
156 arm,vexpress,config-bridge = <&v2m_sysreg>;
157
158 osc@0 {
159 /* ACLK clock to the AXI master port on the test chip */
160 compatible = "arm,vexpress-osc";
161 arm,vexpress-sysreg,func = <1 0>;
162 freq-range = <30000000 50000000>;
163 #clock-cells = <0>;
164 clock-output-names = "extsaxiclk";
165 };
166
167 oscclk1: osc@1 {
168 /* Reference clock for the CLCD */
169 compatible = "arm,vexpress-osc";
170 arm,vexpress-sysreg,func = <1 1>;
171 freq-range = <10000000 80000000>;
172 #clock-cells = <0>;
173 clock-output-names = "clcdclk";
174 };
175
176 smbclk: oscclk2: osc@2 {
177 /* Reference clock for the test chip internal PLLs */
178 compatible = "arm,vexpress-osc";
179 arm,vexpress-sysreg,func = <1 2>;
180 freq-range = <33000000 100000000>;
181 #clock-cells = <0>;
182 clock-output-names = "tcrefclk";
183 };
184
185 volt@0 {
186 /* Test Chip internal logic voltage */
187 compatible = "arm,vexpress-volt";
188 arm,vexpress-sysreg,func = <2 0>;
189 regulator-name = "VD10";
190 regulator-always-on;
191 label = "VD10";
192 };
193
194 volt@1 {
195 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
196 compatible = "arm,vexpress-volt";
197 arm,vexpress-sysreg,func = <2 1>;
198 regulator-name = "VD10_S2";
199 regulator-always-on;
200 label = "VD10_S2";
201 };
202
203 volt@2 {
204 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
205 compatible = "arm,vexpress-volt";
206 arm,vexpress-sysreg,func = <2 2>;
207 regulator-name = "VD10_S3";
208 regulator-always-on;
209 label = "VD10_S3";
210 };
211
212 volt@3 {
213 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
214 compatible = "arm,vexpress-volt";
215 arm,vexpress-sysreg,func = <2 3>;
216 regulator-name = "VCC1V8";
217 regulator-always-on;
218 label = "VCC1V8";
219 };
220
221 volt@4 {
222 /* DDR2 SDRAM VTT termination voltage */
223 compatible = "arm,vexpress-volt";
224 arm,vexpress-sysreg,func = <2 4>;
225 regulator-name = "DDR2VTT";
226 regulator-always-on;
227 label = "DDR2VTT";
228 };
229
230 volt@5 {
231 /* Local board supply for miscellaneous logic external to the Test Chip */
232 arm,vexpress-sysreg,func = <2 5>;
233 compatible = "arm,vexpress-volt";
234 regulator-name = "VCC3V3";
235 regulator-always-on;
236 label = "VCC3V3";
237 };
238
239 amp@0 {
240 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
241 compatible = "arm,vexpress-amp";
242 arm,vexpress-sysreg,func = <3 0>;
243 label = "VD10_S2";
244 };
245
246 amp@1 {
247 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
248 compatible = "arm,vexpress-amp";
249 arm,vexpress-sysreg,func = <3 1>;
250 label = "VD10_S3";
251 };
252
253 power@0 {
254 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
255 compatible = "arm,vexpress-power";
256 arm,vexpress-sysreg,func = <12 0>;
257 label = "PVD10_S2";
258 };
259
260 power@1 {
261 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
262 compatible = "arm,vexpress-power";
263 arm,vexpress-sysreg,func = <12 1>;
264 label = "PVD10_S3";
265 };
266 };
267
268 smb {
269 compatible = "simple-bus";
270
271 #address-cells = <2>;
272 #size-cells = <1>;
144 ranges = <0 0 0x40000000 0x04000000>, 273 ranges = <0 0 0x40000000 0x04000000>,
145 <1 0 0x44000000 0x04000000>, 274 <1 0 0x44000000 0x04000000>,
146 <2 0 0x48000000 0x04000000>, 275 <2 0 0x48000000 0x04000000>,
147 <3 0 0x4c000000 0x04000000>, 276 <3 0 0x4c000000 0x04000000>,
148 <7 0 0x10000000 0x00020000>; 277 <7 0 0x10000000 0x00020000>;
149 278
279 #interrupt-cells = <1>;
150 interrupt-map-mask = <0 0 63>; 280 interrupt-map-mask = <0 0 63>;
151 interrupt-map = <0 0 0 &gic 0 0 4>, 281 interrupt-map = <0 0 0 &gic 0 0 4>,
152 <0 0 1 &gic 0 1 4>, 282 <0 0 1 &gic 0 1 4>,
@@ -191,7 +321,7 @@
191 <0 0 40 &gic 0 40 4>, 321 <0 0 40 &gic 0 40 4>,
192 <0 0 41 &gic 0 41 4>, 322 <0 0 41 &gic 0 41 4>,
193 <0 0 42 &gic 0 42 4>; 323 <0 0 42 &gic 0 42 4>;
324
325 /include/ "vexpress-v2m.dtsi"
194 }; 326 };
195}; 327};
196
197/include/ "vexpress-v2m.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 00:51:39 -0400